/*
 * Copyright (C) 2016 MediaTek Inc.

 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.

 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See http://www.gnu.org/licenses/gpl-2.0.html for more details.
 */

#include <linuxboot/driverapi.h>

#include <mach/upmu_sw.h>
#include <mach/upmu_hw.h>
#include <mt-plat/upmu_common.h>

const PMU_FLAG_TABLE_ENTRY pmu_flags_table[] = {
	{PMIC_USBDL, PMIC_USBDL_ADDR, PMIC_USBDL_MASK, PMIC_USBDL_SHIFT},
	{PMIC_VTCXO_CONFIG, PMIC_VTCXO_CONFIG_ADDR, PMIC_VTCXO_CONFIG_MASK,
	 PMIC_VTCXO_CONFIG_SHIFT},
	{PMIC_RG_THR_DET_DIS, PMIC_RG_THR_DET_DIS_ADDR, PMIC_RG_THR_DET_DIS_MASK,
	 PMIC_RG_THR_DET_DIS_SHIFT},
	{PMIC_RG_THR_TEST, PMIC_RG_THR_TEST_ADDR, PMIC_RG_THR_TEST_MASK,
	 PMIC_RG_THR_TEST_SHIFT},
	{PMIC_RG_STRUP_THER_DEB_RMAX, PMIC_RG_STRUP_THER_DEB_RMAX_ADDR,
	 PMIC_RG_STRUP_THER_DEB_RMAX_MASK, PMIC_RG_STRUP_THER_DEB_RMAX_SHIFT},
	{PMIC_RG_STRUP_THER_DEB_FMAX, PMIC_RG_STRUP_THER_DEB_FMAX_ADDR,
	 PMIC_RG_STRUP_THER_DEB_FMAX_MASK, PMIC_RG_STRUP_THER_DEB_FMAX_SHIFT},
	{PMIC_DDUVLO_DEB_EN, PMIC_DDUVLO_DEB_EN_ADDR, PMIC_DDUVLO_DEB_EN_MASK,
	 PMIC_DDUVLO_DEB_EN_SHIFT},
	{PMIC_RG_PWRBB_DEB_EN, PMIC_RG_PWRBB_DEB_EN_ADDR, PMIC_RG_PWRBB_DEB_EN_MASK,
	 PMIC_RG_PWRBB_DEB_EN_SHIFT},
	{PMIC_RG_STRUP_OSC_EN, PMIC_RG_STRUP_OSC_EN_ADDR, PMIC_RG_STRUP_OSC_EN_MASK,
	 PMIC_RG_STRUP_OSC_EN_SHIFT},
	{PMIC_RG_STRUP_OSC_EN_SEL, PMIC_RG_STRUP_OSC_EN_SEL_ADDR,
	 PMIC_RG_STRUP_OSC_EN_SEL_MASK, PMIC_RG_STRUP_OSC_EN_SEL_SHIFT},
	{PMIC_RG_STRUP_FT_CTRL, PMIC_RG_STRUP_FT_CTRL_ADDR,
	 PMIC_RG_STRUP_FT_CTRL_MASK, PMIC_RG_STRUP_FT_CTRL_SHIFT},
	{PMIC_RG_STRUP_PWRON_FORCE, PMIC_RG_STRUP_PWRON_FORCE_ADDR,
	 PMIC_RG_STRUP_PWRON_FORCE_MASK, PMIC_RG_STRUP_PWRON_FORCE_SHIFT},
	{PMIC_RG_BIASGEN_FORCE, PMIC_RG_BIASGEN_FORCE_ADDR,
	 PMIC_RG_BIASGEN_FORCE_MASK, PMIC_RG_BIASGEN_FORCE_SHIFT},
	{PMIC_RG_STRUP_PWRON, PMIC_RG_STRUP_PWRON_ADDR, PMIC_RG_STRUP_PWRON_MASK,
	 PMIC_RG_STRUP_PWRON_SHIFT},
	{PMIC_RG_STRUP_PWRON_SEL, PMIC_RG_STRUP_PWRON_SEL_ADDR,
	 PMIC_RG_STRUP_PWRON_SEL_MASK, PMIC_RG_STRUP_PWRON_SEL_SHIFT},
	{PMIC_RG_BIASGEN, PMIC_RG_BIASGEN_ADDR, PMIC_RG_BIASGEN_MASK,
	 PMIC_RG_BIASGEN_SHIFT},
	{PMIC_RG_BIASGEN_SEL, PMIC_RG_BIASGEN_SEL_ADDR, PMIC_RG_BIASGEN_SEL_MASK,
	 PMIC_RG_BIASGEN_SEL_SHIFT},
	{PMIC_RG_RTC_XOSC32_ENB, PMIC_RG_RTC_XOSC32_ENB_ADDR,
	 PMIC_RG_RTC_XOSC32_ENB_MASK, PMIC_RG_RTC_XOSC32_ENB_SHIFT},
	{PMIC_RG_RTC_XOSC32_ENB_SEL, PMIC_RG_RTC_XOSC32_ENB_SEL_ADDR,
	 PMIC_RG_RTC_XOSC32_ENB_SEL_MASK, PMIC_RG_RTC_XOSC32_ENB_SEL_SHIFT},
	{PMIC_STRUP_DIG_IO_PG_FORCE, PMIC_STRUP_DIG_IO_PG_FORCE_ADDR,
	 PMIC_STRUP_DIG_IO_PG_FORCE_MASK, PMIC_STRUP_DIG_IO_PG_FORCE_SHIFT},
	{PMIC_CLR_JUST_RST, PMIC_CLR_JUST_RST_ADDR, PMIC_CLR_JUST_RST_MASK,
	 PMIC_CLR_JUST_RST_SHIFT},
	{PMIC_UVLO_L2H_DEB_EN, PMIC_UVLO_L2H_DEB_EN_ADDR, PMIC_UVLO_L2H_DEB_EN_MASK,
	 PMIC_UVLO_L2H_DEB_EN_SHIFT},
	{PMIC_JUST_PWRKEY_RST, PMIC_JUST_PWRKEY_RST_ADDR, PMIC_JUST_PWRKEY_RST_MASK,
	 PMIC_JUST_PWRKEY_RST_SHIFT},
	{PMIC_DA_QI_OSC_EN, PMIC_DA_QI_OSC_EN_ADDR, PMIC_DA_QI_OSC_EN_MASK,
	 PMIC_DA_QI_OSC_EN_SHIFT},
	{PMIC_RG_STRUP_EXT_PMIC_EN, PMIC_RG_STRUP_EXT_PMIC_EN_ADDR,
	 PMIC_RG_STRUP_EXT_PMIC_EN_MASK, PMIC_RG_STRUP_EXT_PMIC_EN_SHIFT},
	{PMIC_RG_STRUP_EXT_PMIC_SEL, PMIC_RG_STRUP_EXT_PMIC_SEL_ADDR,
	 PMIC_RG_STRUP_EXT_PMIC_SEL_MASK, PMIC_RG_STRUP_EXT_PMIC_SEL_SHIFT},
	{PMIC_STRUP_CON8_RSV0, PMIC_STRUP_CON8_RSV0_ADDR, PMIC_STRUP_CON8_RSV0_MASK,
	 PMIC_STRUP_CON8_RSV0_SHIFT},
	{PMIC_DA_QI_EXT_PMIC_EN, PMIC_DA_QI_EXT_PMIC_EN_ADDR,
	 PMIC_DA_QI_EXT_PMIC_EN_MASK, PMIC_DA_QI_EXT_PMIC_EN_SHIFT},
	{PMIC_RG_STRUP_AUXADC_START_SW, PMIC_RG_STRUP_AUXADC_START_SW_ADDR,
	 PMIC_RG_STRUP_AUXADC_START_SW_MASK, PMIC_RG_STRUP_AUXADC_START_SW_SHIFT},
	{PMIC_RG_STRUP_AUXADC_RSTB_SW, PMIC_RG_STRUP_AUXADC_RSTB_SW_ADDR,
	 PMIC_RG_STRUP_AUXADC_RSTB_SW_MASK, PMIC_RG_STRUP_AUXADC_RSTB_SW_SHIFT},
	{PMIC_RG_STRUP_AUXADC_START_SEL, PMIC_RG_STRUP_AUXADC_START_SEL_ADDR,
	 PMIC_RG_STRUP_AUXADC_START_SEL_MASK, PMIC_RG_STRUP_AUXADC_START_SEL_SHIFT},
	{PMIC_RG_STRUP_AUXADC_RSTB_SEL, PMIC_RG_STRUP_AUXADC_RSTB_SEL_ADDR,
	 PMIC_RG_STRUP_AUXADC_RSTB_SEL_MASK, PMIC_RG_STRUP_AUXADC_RSTB_SEL_SHIFT},
	{PMIC_RG_STRUP_AUXADC_RPCNT_MAX, PMIC_RG_STRUP_AUXADC_RPCNT_MAX_ADDR,
	 PMIC_RG_STRUP_AUXADC_RPCNT_MAX_MASK, PMIC_RG_STRUP_AUXADC_RPCNT_MAX_SHIFT},
	{PMIC_STRUP_PWROFF_SEQ_EN, PMIC_STRUP_PWROFF_SEQ_EN_ADDR,
	 PMIC_STRUP_PWROFF_SEQ_EN_MASK, PMIC_STRUP_PWROFF_SEQ_EN_SHIFT},
	{PMIC_STRUP_PWROFF_PREOFF_EN, PMIC_STRUP_PWROFF_PREOFF_EN_ADDR,
	 PMIC_STRUP_PWROFF_PREOFF_EN_MASK, PMIC_STRUP_PWROFF_PREOFF_EN_SHIFT},
	{PMIC_STRUP_DIG0_RSV0, PMIC_STRUP_DIG0_RSV0_ADDR, PMIC_STRUP_DIG0_RSV0_MASK,
	 PMIC_STRUP_DIG0_RSV0_SHIFT},
	{PMIC_STRUP_DIG1_RSV0, PMIC_STRUP_DIG1_RSV0_ADDR, PMIC_STRUP_DIG1_RSV0_MASK,
	 PMIC_STRUP_DIG1_RSV0_SHIFT},
	{PMIC_RG_RSV_SWREG, PMIC_RG_RSV_SWREG_ADDR, PMIC_RG_RSV_SWREG_MASK,
	 PMIC_RG_RSV_SWREG_SHIFT},
	{PMIC_RG_STRUP_UVLO_U1U2_SEL, PMIC_RG_STRUP_UVLO_U1U2_SEL_ADDR,
	 PMIC_RG_STRUP_UVLO_U1U2_SEL_MASK, PMIC_RG_STRUP_UVLO_U1U2_SEL_SHIFT},
	{PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL, PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL_ADDR,
	 PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL_MASK,
	 PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL_SHIFT},
	{PMIC_RG_STRUP_THR_CLR, PMIC_RG_STRUP_THR_CLR_ADDR,
	 PMIC_RG_STRUP_THR_CLR_MASK, PMIC_RG_STRUP_THR_CLR_SHIFT},
	{PMIC_RG_STRUP_LONG_PRESS_EXT_SEL, PMIC_RG_STRUP_LONG_PRESS_EXT_SEL_ADDR,
	 PMIC_RG_STRUP_LONG_PRESS_EXT_SEL_MASK,
	 PMIC_RG_STRUP_LONG_PRESS_EXT_SEL_SHIFT},
	{PMIC_RG_STRUP_LONG_PRESS_EXT_TD, PMIC_RG_STRUP_LONG_PRESS_EXT_TD_ADDR,
	 PMIC_RG_STRUP_LONG_PRESS_EXT_TD_MASK, PMIC_RG_STRUP_LONG_PRESS_EXT_TD_SHIFT},
	{PMIC_RG_STRUP_LONG_PRESS_EXT_EN, PMIC_RG_STRUP_LONG_PRESS_EXT_EN_ADDR,
	 PMIC_RG_STRUP_LONG_PRESS_EXT_EN_MASK, PMIC_RG_STRUP_LONG_PRESS_EXT_EN_SHIFT},
	{PMIC_RG_STRUP_LONG_PRESS_EXT_CHR_CTRL, PMIC_RG_STRUP_LONG_PRESS_EXT_CHR_CTRL_ADDR,
	 PMIC_RG_STRUP_LONG_PRESS_EXT_CHR_CTRL_MASK,
	 PMIC_RG_STRUP_LONG_PRESS_EXT_CHR_CTRL_SHIFT},
	{PMIC_RG_STRUP_LONG_PRESS_EXT_PWRKEY_CTRL,
	 PMIC_RG_STRUP_LONG_PRESS_EXT_PWRKEY_CTRL_ADDR,
	 PMIC_RG_STRUP_LONG_PRESS_EXT_PWRKEY_CTRL_MASK,
	 PMIC_RG_STRUP_LONG_PRESS_EXT_PWRKEY_CTRL_SHIFT},
	{PMIC_RG_STRUP_LONG_PRESS_EXT_PWRBB_CTRL,
	 PMIC_RG_STRUP_LONG_PRESS_EXT_PWRBB_CTRL_ADDR,
	 PMIC_RG_STRUP_LONG_PRESS_EXT_PWRBB_CTRL_MASK,
	 PMIC_RG_STRUP_LONG_PRESS_EXT_PWRBB_CTRL_SHIFT},
	{PMIC_RG_STRUP_ENVTEM, PMIC_RG_STRUP_ENVTEM_ADDR, PMIC_RG_STRUP_ENVTEM_MASK,
	 PMIC_RG_STRUP_ENVTEM_SHIFT},
	{PMIC_RG_STRUP_ENVTEM_CTRL, PMIC_RG_STRUP_ENVTEM_CTRL_ADDR,
	 PMIC_RG_STRUP_ENVTEM_CTRL_MASK, PMIC_RG_STRUP_ENVTEM_CTRL_SHIFT},
	{PMIC_RG_STRUP_PWRKEY_COUNT_RESET, PMIC_RG_STRUP_PWRKEY_COUNT_RESET_ADDR,
	 PMIC_RG_STRUP_PWRKEY_COUNT_RESET_MASK,
	 PMIC_RG_STRUP_PWRKEY_COUNT_RESET_SHIFT},
	{PMIC_RG_STRUP_VCORE2_PG_H2L_EN, PMIC_RG_STRUP_VCORE2_PG_H2L_EN_ADDR,
	 PMIC_RG_STRUP_VCORE2_PG_H2L_EN_MASK, PMIC_RG_STRUP_VCORE2_PG_H2L_EN_SHIFT},
	{PMIC_RG_STRUP_VMCH_PG_H2L_EN, PMIC_RG_STRUP_VMCH_PG_H2L_EN_ADDR,
	 PMIC_RG_STRUP_VMCH_PG_H2L_EN_MASK, PMIC_RG_STRUP_VMCH_PG_H2L_EN_SHIFT},
	{PMIC_RG_STRUP_VMC_PG_H2L_EN, PMIC_RG_STRUP_VMC_PG_H2L_EN_ADDR,
	 PMIC_RG_STRUP_VMC_PG_H2L_EN_MASK, PMIC_RG_STRUP_VMC_PG_H2L_EN_SHIFT},
	{PMIC_RG_STRUP_VUSB33_PG_H2L_EN, PMIC_RG_STRUP_VUSB33_PG_H2L_EN_ADDR,
	 PMIC_RG_STRUP_VUSB33_PG_H2L_EN_MASK, PMIC_RG_STRUP_VUSB33_PG_H2L_EN_SHIFT},
	{PMIC_RG_STRUP_VSRAM_PROC_PG_H2L_EN, PMIC_RG_STRUP_VSRAM_PROC_PG_H2L_EN_ADDR,
	 PMIC_RG_STRUP_VSRAM_PROC_PG_H2L_EN_MASK,
	 PMIC_RG_STRUP_VSRAM_PROC_PG_H2L_EN_SHIFT},
	{PMIC_RG_STRUP_VPROC_PG_H2L_EN, PMIC_RG_STRUP_VPROC_PG_H2L_EN_ADDR,
	 PMIC_RG_STRUP_VPROC_PG_H2L_EN_MASK, PMIC_RG_STRUP_VPROC_PG_H2L_EN_SHIFT},
	{PMIC_RG_STRUP_VDRAM_PG_H2L_EN, PMIC_RG_STRUP_VDRAM_PG_H2L_EN_ADDR,
	 PMIC_RG_STRUP_VDRAM_PG_H2L_EN_MASK, PMIC_RG_STRUP_VDRAM_PG_H2L_EN_SHIFT},
	{PMIC_RG_STRUP_VAUD28_PG_H2L_EN, PMIC_RG_STRUP_VAUD28_PG_H2L_EN_ADDR,
	 PMIC_RG_STRUP_VAUD28_PG_H2L_EN_MASK, PMIC_RG_STRUP_VAUD28_PG_H2L_EN_SHIFT},
	{PMIC_RG_STRUP_VEMC_PG_H2L_EN, PMIC_RG_STRUP_VEMC_PG_H2L_EN_ADDR,
	 PMIC_RG_STRUP_VEMC_PG_H2L_EN_MASK, PMIC_RG_STRUP_VEMC_PG_H2L_EN_SHIFT},
	{PMIC_RG_STRUP_VS1_PG_H2L_EN, PMIC_RG_STRUP_VS1_PG_H2L_EN_ADDR,
	 PMIC_RG_STRUP_VS1_PG_H2L_EN_MASK, PMIC_RG_STRUP_VS1_PG_H2L_EN_SHIFT},
	{PMIC_RG_STRUP_VCORE_PG_H2L_EN, PMIC_RG_STRUP_VCORE_PG_H2L_EN_ADDR,
	 PMIC_RG_STRUP_VCORE_PG_H2L_EN_MASK, PMIC_RG_STRUP_VCORE_PG_H2L_EN_SHIFT},
	{PMIC_RG_STRUP_VAUX18_PG_H2L_EN, PMIC_RG_STRUP_VAUX18_PG_H2L_EN_ADDR,
	 PMIC_RG_STRUP_VAUX18_PG_H2L_EN_MASK, PMIC_RG_STRUP_VAUX18_PG_H2L_EN_SHIFT},
	{PMIC_RG_STRUP_VCORE2_PG_ENB, PMIC_RG_STRUP_VCORE2_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VCORE2_PG_ENB_MASK, PMIC_RG_STRUP_VCORE2_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VMCH_PG_ENB, PMIC_RG_STRUP_VMCH_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VMCH_PG_ENB_MASK, PMIC_RG_STRUP_VMCH_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VMC_PG_ENB, PMIC_RG_STRUP_VMC_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VMC_PG_ENB_MASK, PMIC_RG_STRUP_VMC_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VXO22_PG_ENB, PMIC_RG_STRUP_VXO22_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VXO22_PG_ENB_MASK, PMIC_RG_STRUP_VXO22_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VTCXO_PG_ENB, PMIC_RG_STRUP_VTCXO_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VTCXO_PG_ENB_MASK, PMIC_RG_STRUP_VTCXO_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VUSB33_PG_ENB, PMIC_RG_STRUP_VUSB33_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VUSB33_PG_ENB_MASK, PMIC_RG_STRUP_VUSB33_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VSRAM_PROC_PG_ENB, PMIC_RG_STRUP_VSRAM_PROC_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VSRAM_PROC_PG_ENB_MASK, PMIC_RG_STRUP_VSRAM_PROC_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VPROC_PG_ENB, PMIC_RG_STRUP_VPROC_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VPROC_PG_ENB_MASK, PMIC_RG_STRUP_VPROC_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VDRAM_PG_ENB, PMIC_RG_STRUP_VDRAM_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VDRAM_PG_ENB_MASK, PMIC_RG_STRUP_VDRAM_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VAUD28_PG_ENB, PMIC_RG_STRUP_VAUD28_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VAUD28_PG_ENB_MASK, PMIC_RG_STRUP_VAUD28_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VIO28_PG_ENB, PMIC_RG_STRUP_VIO28_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VIO28_PG_ENB_MASK, PMIC_RG_STRUP_VIO28_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VEMC_PG_ENB, PMIC_RG_STRUP_VEMC_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VEMC_PG_ENB_MASK, PMIC_RG_STRUP_VEMC_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VIO18_PG_ENB, PMIC_RG_STRUP_VIO18_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VIO18_PG_ENB_MASK, PMIC_RG_STRUP_VIO18_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VS1_PG_ENB, PMIC_RG_STRUP_VS1_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VS1_PG_ENB_MASK, PMIC_RG_STRUP_VS1_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VCORE_PG_ENB, PMIC_RG_STRUP_VCORE_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VCORE_PG_ENB_MASK, PMIC_RG_STRUP_VCORE_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VAUX18_PG_ENB, PMIC_RG_STRUP_VAUX18_PG_ENB_ADDR,
	 PMIC_RG_STRUP_VAUX18_PG_ENB_MASK, PMIC_RG_STRUP_VAUX18_PG_ENB_SHIFT},
	{PMIC_RG_STRUP_VCORE2_OC_ENB, PMIC_RG_STRUP_VCORE2_OC_ENB_ADDR,
	 PMIC_RG_STRUP_VCORE2_OC_ENB_MASK, PMIC_RG_STRUP_VCORE2_OC_ENB_SHIFT},
	{PMIC_RG_STRUP_VPROC_OC_ENB, PMIC_RG_STRUP_VPROC_OC_ENB_ADDR,
	 PMIC_RG_STRUP_VPROC_OC_ENB_MASK, PMIC_RG_STRUP_VPROC_OC_ENB_SHIFT},
	{PMIC_RG_STRUP_VS1_OC_ENB, PMIC_RG_STRUP_VS1_OC_ENB_ADDR,
	 PMIC_RG_STRUP_VS1_OC_ENB_MASK, PMIC_RG_STRUP_VS1_OC_ENB_SHIFT},
	{PMIC_RG_STRUP_VCORE_OC_ENB, PMIC_RG_STRUP_VCORE_OC_ENB_ADDR,
	 PMIC_RG_STRUP_VCORE_OC_ENB_MASK, PMIC_RG_STRUP_VCORE_OC_ENB_SHIFT},
	{PMIC_RG_STRUP_LONG_PRESS_RESET_EXTEND, PMIC_RG_STRUP_LONG_PRESS_RESET_EXTEND_ADDR,
	 PMIC_RG_STRUP_LONG_PRESS_RESET_EXTEND_MASK,
	 PMIC_RG_STRUP_LONG_PRESS_RESET_EXTEND_SHIFT},
	{PMIC_RG_THRDET_SEL, PMIC_RG_THRDET_SEL_ADDR, PMIC_RG_THRDET_SEL_MASK,
	 PMIC_RG_THRDET_SEL_SHIFT},
	{PMIC_RG_STRUP_THR_SEL, PMIC_RG_STRUP_THR_SEL_ADDR,
	 PMIC_RG_STRUP_THR_SEL_MASK, PMIC_RG_STRUP_THR_SEL_SHIFT},
	{PMIC_RG_THR_TMODE, PMIC_RG_THR_TMODE_ADDR, PMIC_RG_THR_TMODE_MASK,
	 PMIC_RG_THR_TMODE_SHIFT},
	{PMIC_RG_VREF_BG, PMIC_RG_VREF_BG_ADDR, PMIC_RG_VREF_BG_MASK,
	 PMIC_RG_VREF_BG_SHIFT},
	{PMIC_RG_STRUP_IREF_TRIM, PMIC_RG_STRUP_IREF_TRIM_ADDR,
	 PMIC_RG_STRUP_IREF_TRIM_MASK, PMIC_RG_STRUP_IREF_TRIM_SHIFT},
	{PMIC_RG_RST_DRVSEL, PMIC_RG_RST_DRVSEL_ADDR, PMIC_RG_RST_DRVSEL_MASK,
	 PMIC_RG_RST_DRVSEL_SHIFT},
	{PMIC_RG_EN_DRVSEL, PMIC_RG_EN_DRVSEL_ADDR, PMIC_RG_EN_DRVSEL_MASK,
	 PMIC_RG_EN_DRVSEL_SHIFT},
	{PMIC_RG_FCHR_KEYDET_EN, PMIC_RG_FCHR_KEYDET_EN_ADDR,
	 PMIC_RG_FCHR_KEYDET_EN_MASK, PMIC_RG_FCHR_KEYDET_EN_SHIFT},
	{PMIC_RG_FCHR_PU_EN, PMIC_RG_FCHR_PU_EN_ADDR, PMIC_RG_FCHR_PU_EN_MASK,
	 PMIC_RG_FCHR_PU_EN_SHIFT},
	{PMIC_RG_PMU_RSV, PMIC_RG_PMU_RSV_ADDR, PMIC_RG_PMU_RSV_MASK,
	 PMIC_RG_PMU_RSV_SHIFT},
	{PMIC_TYPE_C_PHY_RG_CC_RP_SEL, PMIC_TYPE_C_PHY_RG_CC_RP_SEL_ADDR,
	 PMIC_TYPE_C_PHY_RG_CC_RP_SEL_MASK, PMIC_TYPE_C_PHY_RG_CC_RP_SEL_SHIFT},
	{PMIC_REG_TYPE_C_PHY_RG_PD_TX_SLEW_CALEN,
	 PMIC_REG_TYPE_C_PHY_RG_PD_TX_SLEW_CALEN_ADDR,
	 PMIC_REG_TYPE_C_PHY_RG_PD_TX_SLEW_CALEN_MASK,
	 PMIC_REG_TYPE_C_PHY_RG_PD_TX_SLEW_CALEN_SHIFT},
	{PMIC_REG_TYPE_C_PHY_RG_PD_TXSLEW_I, PMIC_REG_TYPE_C_PHY_RG_PD_TXSLEW_I_ADDR,
	 PMIC_REG_TYPE_C_PHY_RG_PD_TXSLEW_I_MASK,
	 PMIC_REG_TYPE_C_PHY_RG_PD_TXSLEW_I_SHIFT},
	{PMIC_REG_TYPE_C_PHY_RG_CC_MPX_SEL, PMIC_REG_TYPE_C_PHY_RG_CC_MPX_SEL_ADDR,
	 PMIC_REG_TYPE_C_PHY_RG_CC_MPX_SEL_MASK,
	 PMIC_REG_TYPE_C_PHY_RG_CC_MPX_SEL_SHIFT},
	{PMIC_REG_TYPE_C_PHY_RG_CC_RESERVE, PMIC_REG_TYPE_C_PHY_RG_CC_RESERVE_ADDR,
	 PMIC_REG_TYPE_C_PHY_RG_CC_RESERVE_MASK,
	 PMIC_REG_TYPE_C_PHY_RG_CC_RESERVE_SHIFT},
	{PMIC_REG_TYPE_C_VCMP_CC2_SW_SEL_ST_CNT_VAL,
	 PMIC_REG_TYPE_C_VCMP_CC2_SW_SEL_ST_CNT_VAL_ADDR,
	 PMIC_REG_TYPE_C_VCMP_CC2_SW_SEL_ST_CNT_VAL_MASK,
	 PMIC_REG_TYPE_C_VCMP_CC2_SW_SEL_ST_CNT_VAL_SHIFT},
	{PMIC_REG_TYPE_C_VCMP_BIAS_EN_ST_CNT_VAL,
	 PMIC_REG_TYPE_C_VCMP_BIAS_EN_ST_CNT_VAL_ADDR,
	 PMIC_REG_TYPE_C_VCMP_BIAS_EN_ST_CNT_VAL_MASK,
	 PMIC_REG_TYPE_C_VCMP_BIAS_EN_ST_CNT_VAL_SHIFT},
	{PMIC_REG_TYPE_C_VCMP_DAC_EN_ST_CNT_VAL, PMIC_REG_TYPE_C_VCMP_DAC_EN_ST_CNT_VAL_ADDR,
	 PMIC_REG_TYPE_C_VCMP_DAC_EN_ST_CNT_VAL_MASK,
	 PMIC_REG_TYPE_C_VCMP_DAC_EN_ST_CNT_VAL_SHIFT},
	{PMIC_REG_TYPE_C_PORT_SUPPORT_ROLE, PMIC_REG_TYPE_C_PORT_SUPPORT_ROLE_ADDR,
	 PMIC_REG_TYPE_C_PORT_SUPPORT_ROLE_MASK,
	 PMIC_REG_TYPE_C_PORT_SUPPORT_ROLE_SHIFT},
	{PMIC_REG_TYPE_C_ADC_EN, PMIC_REG_TYPE_C_ADC_EN_ADDR,
	 PMIC_REG_TYPE_C_ADC_EN_MASK, PMIC_REG_TYPE_C_ADC_EN_SHIFT},
	{PMIC_REG_TYPE_C_ACC_EN, PMIC_REG_TYPE_C_ACC_EN_ADDR,
	 PMIC_REG_TYPE_C_ACC_EN_MASK, PMIC_REG_TYPE_C_ACC_EN_SHIFT},
	{PMIC_REG_TYPE_C_AUDIO_ACC_EN, PMIC_REG_TYPE_C_AUDIO_ACC_EN_ADDR,
	 PMIC_REG_TYPE_C_AUDIO_ACC_EN_MASK, PMIC_REG_TYPE_C_AUDIO_ACC_EN_SHIFT},
	{PMIC_REG_TYPE_C_DEBUG_ACC_EN, PMIC_REG_TYPE_C_DEBUG_ACC_EN_ADDR,
	 PMIC_REG_TYPE_C_DEBUG_ACC_EN_MASK, PMIC_REG_TYPE_C_DEBUG_ACC_EN_SHIFT},
	{PMIC_REG_TYPE_C_TRY_SRC_ST_EN, PMIC_REG_TYPE_C_TRY_SRC_ST_EN_ADDR,
	 PMIC_REG_TYPE_C_TRY_SRC_ST_EN_MASK, PMIC_REG_TYPE_C_TRY_SRC_ST_EN_SHIFT},
	{PMIC_REG_TYPE_C_ATTACH_SRC_2_TRY_WAIT_SNK_ST_EN,
	 PMIC_REG_TYPE_C_ATTACH_SRC_2_TRY_WAIT_SNK_ST_EN_ADDR,
	 PMIC_REG_TYPE_C_ATTACH_SRC_2_TRY_WAIT_SNK_ST_EN_MASK,
	 PMIC_REG_TYPE_C_ATTACH_SRC_2_TRY_WAIT_SNK_ST_EN_SHIFT},
	{PMIC_REG_TYPE_C_PD2CC_DET_DISABLE_EN, PMIC_REG_TYPE_C_PD2CC_DET_DISABLE_EN_ADDR,
	 PMIC_REG_TYPE_C_PD2CC_DET_DISABLE_EN_MASK,
	 PMIC_REG_TYPE_C_PD2CC_DET_DISABLE_EN_SHIFT},
	{PMIC_REG_TYPE_C_ATTACH_SRC_OPEN_PDDEBOUNCE_EN,
	 PMIC_REG_TYPE_C_ATTACH_SRC_OPEN_PDDEBOUNCE_EN_ADDR,
	 PMIC_REG_TYPE_C_ATTACH_SRC_OPEN_PDDEBOUNCE_EN_MASK,
	 PMIC_REG_TYPE_C_ATTACH_SRC_OPEN_PDDEBOUNCE_EN_SHIFT},
	{PMIC_REG_TYPE_C_DISABLE_ST_RD_EN, PMIC_REG_TYPE_C_DISABLE_ST_RD_EN_ADDR,
	 PMIC_REG_TYPE_C_DISABLE_ST_RD_EN_MASK,
	 PMIC_REG_TYPE_C_DISABLE_ST_RD_EN_SHIFT},
	{PMIC_W1_TYPE_C_SW_ENT_DISABLE_CMD, PMIC_W1_TYPE_C_SW_ENT_DISABLE_CMD_ADDR,
	 PMIC_W1_TYPE_C_SW_ENT_DISABLE_CMD_MASK,
	 PMIC_W1_TYPE_C_SW_ENT_DISABLE_CMD_SHIFT},
	{PMIC_W1_TYPE_C_SW_ENT_UNATCH_SRC_CMD, PMIC_W1_TYPE_C_SW_ENT_UNATCH_SRC_CMD_ADDR,
	 PMIC_W1_TYPE_C_SW_ENT_UNATCH_SRC_CMD_MASK,
	 PMIC_W1_TYPE_C_SW_ENT_UNATCH_SRC_CMD_SHIFT},
	{PMIC_W1_TYPE_C_SW_ENT_UNATCH_SNK_CMD, PMIC_W1_TYPE_C_SW_ENT_UNATCH_SNK_CMD_ADDR,
	 PMIC_W1_TYPE_C_SW_ENT_UNATCH_SNK_CMD_MASK,
	 PMIC_W1_TYPE_C_SW_ENT_UNATCH_SNK_CMD_SHIFT},
	{PMIC_W1_TYPE_C_SW_PR_SWAP_INDICATE_CMD, PMIC_W1_TYPE_C_SW_PR_SWAP_INDICATE_CMD_ADDR,
	 PMIC_W1_TYPE_C_SW_PR_SWAP_INDICATE_CMD_MASK,
	 PMIC_W1_TYPE_C_SW_PR_SWAP_INDICATE_CMD_SHIFT},
	{PMIC_W1_TYPE_C_SW_VCONN_SWAP_INDICATE_CMD,
	 PMIC_W1_TYPE_C_SW_VCONN_SWAP_INDICATE_CMD_ADDR,
	 PMIC_W1_TYPE_C_SW_VCONN_SWAP_INDICATE_CMD_MASK,
	 PMIC_W1_TYPE_C_SW_VCONN_SWAP_INDICATE_CMD_SHIFT},
	{PMIC_W1_TYPE_C_SW_ADC_RESULT_MET_VRD_DEFAULT_CMD,
	 PMIC_W1_TYPE_C_SW_ADC_RESULT_MET_VRD_DEFAULT_CMD_ADDR,
	 PMIC_W1_TYPE_C_SW_ADC_RESULT_MET_VRD_DEFAULT_CMD_MASK,
	 PMIC_W1_TYPE_C_SW_ADC_RESULT_MET_VRD_DEFAULT_CMD_SHIFT},
	{PMIC_W1_TYPE_C_SW_ADC_RESULT_MET_VRD_15_CMD,
	 PMIC_W1_TYPE_C_SW_ADC_RESULT_MET_VRD_15_CMD_ADDR,
	 PMIC_W1_TYPE_C_SW_ADC_RESULT_MET_VRD_15_CMD_MASK,
	 PMIC_W1_TYPE_C_SW_ADC_RESULT_MET_VRD_15_CMD_SHIFT},
	{PMIC_W1_TYPE_C_SW_ADC_RESULT_MET_VRD_30_CMD,
	 PMIC_W1_TYPE_C_SW_ADC_RESULT_MET_VRD_30_CMD_ADDR,
	 PMIC_W1_TYPE_C_SW_ADC_RESULT_MET_VRD_30_CMD_MASK,
	 PMIC_W1_TYPE_C_SW_ADC_RESULT_MET_VRD_30_CMD_SHIFT},
	{PMIC_TYPE_C_SW_VBUS_PRESENT, PMIC_TYPE_C_SW_VBUS_PRESENT_ADDR,
	 PMIC_TYPE_C_SW_VBUS_PRESENT_MASK, PMIC_TYPE_C_SW_VBUS_PRESENT_SHIFT},
	{PMIC_TYPE_C_SW_DA_DRIVE_VCONN_EN, PMIC_TYPE_C_SW_DA_DRIVE_VCONN_EN_ADDR,
	 PMIC_TYPE_C_SW_DA_DRIVE_VCONN_EN_MASK,
	 PMIC_TYPE_C_SW_DA_DRIVE_VCONN_EN_SHIFT},
	{PMIC_TYPE_C_SW_VBUS_DET_DIS, PMIC_TYPE_C_SW_VBUS_DET_DIS_ADDR,
	 PMIC_TYPE_C_SW_VBUS_DET_DIS_MASK, PMIC_TYPE_C_SW_VBUS_DET_DIS_SHIFT},
	{PMIC_TYPE_C_SW_CC_DET_DIS, PMIC_TYPE_C_SW_CC_DET_DIS_ADDR,
	 PMIC_TYPE_C_SW_CC_DET_DIS_MASK, PMIC_TYPE_C_SW_CC_DET_DIS_SHIFT},
	{PMIC_TYPE_C_SW_PD_EN, PMIC_TYPE_C_SW_PD_EN_ADDR, PMIC_TYPE_C_SW_PD_EN_MASK,
	 PMIC_TYPE_C_SW_PD_EN_SHIFT},
	{PMIC_W1_TYPE_C_SW_ENT_SNK_PWR_REDETECT_CMD,
	 PMIC_W1_TYPE_C_SW_ENT_SNK_PWR_REDETECT_CMD_ADDR,
	 PMIC_W1_TYPE_C_SW_ENT_SNK_PWR_REDETECT_CMD_MASK,
	 PMIC_W1_TYPE_C_SW_ENT_SNK_PWR_REDETECT_CMD_SHIFT},
	{PMIC_REG_TYPE_C_CC_VOL_PERIODIC_MEAS_VAL,
	 PMIC_REG_TYPE_C_CC_VOL_PERIODIC_MEAS_VAL_ADDR,
	 PMIC_REG_TYPE_C_CC_VOL_PERIODIC_MEAS_VAL_MASK,
	 PMIC_REG_TYPE_C_CC_VOL_PERIODIC_MEAS_VAL_SHIFT},
	{PMIC_REG_TYPE_C_CC_VOL_CC_DEBOUNCE_CNT_VAL,
	 PMIC_REG_TYPE_C_CC_VOL_CC_DEBOUNCE_CNT_VAL_ADDR,
	 PMIC_REG_TYPE_C_CC_VOL_CC_DEBOUNCE_CNT_VAL_MASK,
	 PMIC_REG_TYPE_C_CC_VOL_CC_DEBOUNCE_CNT_VAL_SHIFT},
	{PMIC_REG_TYPE_C_CC_VOL_PD_DEBOUNCE_CNT_VAL,
	 PMIC_REG_TYPE_C_CC_VOL_PD_DEBOUNCE_CNT_VAL_ADDR,
	 PMIC_REG_TYPE_C_CC_VOL_PD_DEBOUNCE_CNT_VAL_MASK,
	 PMIC_REG_TYPE_C_CC_VOL_PD_DEBOUNCE_CNT_VAL_SHIFT},
	{PMIC_REG_TYPE_C_DRP_SRC_CNT_VAL_0, PMIC_REG_TYPE_C_DRP_SRC_CNT_VAL_0_ADDR,
	 PMIC_REG_TYPE_C_DRP_SRC_CNT_VAL_0_MASK,
	 PMIC_REG_TYPE_C_DRP_SRC_CNT_VAL_0_SHIFT},
	{PMIC_REG_TYPE_C_DRP_SNK_CNT_VAL_0, PMIC_REG_TYPE_C_DRP_SNK_CNT_VAL_0_ADDR,
	 PMIC_REG_TYPE_C_DRP_SNK_CNT_VAL_0_MASK,
	 PMIC_REG_TYPE_C_DRP_SNK_CNT_VAL_0_SHIFT},
	{PMIC_REG_TYPE_C_DRP_TRY_CNT_VAL_0, PMIC_REG_TYPE_C_DRP_TRY_CNT_VAL_0_ADDR,
	 PMIC_REG_TYPE_C_DRP_TRY_CNT_VAL_0_MASK,
	 PMIC_REG_TYPE_C_DRP_TRY_CNT_VAL_0_SHIFT},
	{PMIC_REG_TYPE_C_DRP_TRY_WAIT_CNT_VAL_0, PMIC_REG_TYPE_C_DRP_TRY_WAIT_CNT_VAL_0_ADDR,
	 PMIC_REG_TYPE_C_DRP_TRY_WAIT_CNT_VAL_0_MASK,
	 PMIC_REG_TYPE_C_DRP_TRY_WAIT_CNT_VAL_0_SHIFT},
	{PMIC_REG_TYPE_C_DRP_TRY_WAIT_CNT_VAL_1, PMIC_REG_TYPE_C_DRP_TRY_WAIT_CNT_VAL_1_ADDR,
	 PMIC_REG_TYPE_C_DRP_TRY_WAIT_CNT_VAL_1_MASK,
	 PMIC_REG_TYPE_C_DRP_TRY_WAIT_CNT_VAL_1_SHIFT},
	{PMIC_REG_TYPE_C_CC_SRC_VOPEN_DEFAULT_DAC_VAL,
	 PMIC_REG_TYPE_C_CC_SRC_VOPEN_DEFAULT_DAC_VAL_ADDR,
	 PMIC_REG_TYPE_C_CC_SRC_VOPEN_DEFAULT_DAC_VAL_MASK,
	 PMIC_REG_TYPE_C_CC_SRC_VOPEN_DEFAULT_DAC_VAL_SHIFT},
	{PMIC_REG_TYPE_C_CC_SRC_VRD_DEFAULT_DAC_VAL,
	 PMIC_REG_TYPE_C_CC_SRC_VRD_DEFAULT_DAC_VAL_ADDR,
	 PMIC_REG_TYPE_C_CC_SRC_VRD_DEFAULT_DAC_VAL_MASK,
	 PMIC_REG_TYPE_C_CC_SRC_VRD_DEFAULT_DAC_VAL_SHIFT},
	{PMIC_REG_TYPE_C_CC_SRC_VOPEN_15_DAC_VAL,
	 PMIC_REG_TYPE_C_CC_SRC_VOPEN_15_DAC_VAL_ADDR,
	 PMIC_REG_TYPE_C_CC_SRC_VOPEN_15_DAC_VAL_MASK,
	 PMIC_REG_TYPE_C_CC_SRC_VOPEN_15_DAC_VAL_SHIFT},
	{PMIC_REG_TYPE_C_CC_SRC_VRD_15_DAC_VAL, PMIC_REG_TYPE_C_CC_SRC_VRD_15_DAC_VAL_ADDR,
	 PMIC_REG_TYPE_C_CC_SRC_VRD_15_DAC_VAL_MASK,
	 PMIC_REG_TYPE_C_CC_SRC_VRD_15_DAC_VAL_SHIFT},
	{PMIC_REG_TYPE_C_CC_SRC_VOPEN_30_DAC_VAL,
	 PMIC_REG_TYPE_C_CC_SRC_VOPEN_30_DAC_VAL_ADDR,
	 PMIC_REG_TYPE_C_CC_SRC_VOPEN_30_DAC_VAL_MASK,
	 PMIC_REG_TYPE_C_CC_SRC_VOPEN_30_DAC_VAL_SHIFT},
	{PMIC_REG_TYPE_C_CC_SRC_VRD_30_DAC_VAL, PMIC_REG_TYPE_C_CC_SRC_VRD_30_DAC_VAL_ADDR,
	 PMIC_REG_TYPE_C_CC_SRC_VRD_30_DAC_VAL_MASK,
	 PMIC_REG_TYPE_C_CC_SRC_VRD_30_DAC_VAL_SHIFT},
	{PMIC_REG_TYPE_C_CC_SNK_VRP30_DAC_VAL, PMIC_REG_TYPE_C_CC_SNK_VRP30_DAC_VAL_ADDR,
	 PMIC_REG_TYPE_C_CC_SNK_VRP30_DAC_VAL_MASK,
	 PMIC_REG_TYPE_C_CC_SNK_VRP30_DAC_VAL_SHIFT},
	{PMIC_REG_TYPE_C_CC_SNK_VRP15_DAC_VAL, PMIC_REG_TYPE_C_CC_SNK_VRP15_DAC_VAL_ADDR,
	 PMIC_REG_TYPE_C_CC_SNK_VRP15_DAC_VAL_MASK,
	 PMIC_REG_TYPE_C_CC_SNK_VRP15_DAC_VAL_SHIFT},
	{PMIC_REG_TYPE_C_CC_SNK_VRPUSB_DAC_VAL, PMIC_REG_TYPE_C_CC_SNK_VRPUSB_DAC_VAL_ADDR,
	 PMIC_REG_TYPE_C_CC_SNK_VRPUSB_DAC_VAL_MASK,
	 PMIC_REG_TYPE_C_CC_SNK_VRPUSB_DAC_VAL_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_ATTACH_SRC_INTR_EN,
	 PMIC_REG_TYPE_C_CC_ENT_ATTACH_SRC_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_ATTACH_SRC_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_ATTACH_SRC_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_ATTACH_SNK_INTR_EN,
	 PMIC_REG_TYPE_C_CC_ENT_ATTACH_SNK_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_ATTACH_SNK_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_ATTACH_SNK_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_AUDIO_ACC_INTR_EN,
	 PMIC_REG_TYPE_C_CC_ENT_AUDIO_ACC_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_AUDIO_ACC_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_AUDIO_ACC_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_DBG_ACC_INTR_EN, PMIC_REG_TYPE_C_CC_ENT_DBG_ACC_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_DBG_ACC_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_DBG_ACC_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_DISABLE_INTR_EN, PMIC_REG_TYPE_C_CC_ENT_DISABLE_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_DISABLE_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_DISABLE_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_UNATTACH_SRC_INTR_EN,
	 PMIC_REG_TYPE_C_CC_ENT_UNATTACH_SRC_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_UNATTACH_SRC_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_UNATTACH_SRC_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_UNATTACH_SNK_INTR_EN,
	 PMIC_REG_TYPE_C_CC_ENT_UNATTACH_SNK_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_UNATTACH_SNK_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_UNATTACH_SNK_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_ATTACH_WAIT_SRC_INTR_EN,
	 PMIC_REG_TYPE_C_CC_ENT_ATTACH_WAIT_SRC_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_ATTACH_WAIT_SRC_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_ATTACH_WAIT_SRC_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_ATTACH_WAIT_SNK_INTR_EN,
	 PMIC_REG_TYPE_C_CC_ENT_ATTACH_WAIT_SNK_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_ATTACH_WAIT_SNK_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_ATTACH_WAIT_SNK_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_TRY_SRC_INTR_EN, PMIC_REG_TYPE_C_CC_ENT_TRY_SRC_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_TRY_SRC_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_TRY_SRC_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_TRY_WAIT_SNK_INTR_EN,
	 PMIC_REG_TYPE_C_CC_ENT_TRY_WAIT_SNK_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_TRY_WAIT_SNK_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_TRY_WAIT_SNK_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_UNATTACH_ACC_INTR_EN,
	 PMIC_REG_TYPE_C_CC_ENT_UNATTACH_ACC_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_UNATTACH_ACC_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_UNATTACH_ACC_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_ATTACH_WAIT_ACC_INTR_EN,
	 PMIC_REG_TYPE_C_CC_ENT_ATTACH_WAIT_ACC_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_ATTACH_WAIT_ACC_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_ATTACH_WAIT_ACC_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_IDLE_INTR_EN,
	 PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_IDLE_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_IDLE_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_IDLE_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_DEFAULT_INTR_EN,
	 PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_DEFAULT_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_DEFAULT_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_DEFAULT_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_15_INTR_EN,
	 PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_15_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_15_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_15_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_30_INTR_EN,
	 PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_30_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_30_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_30_INTR_EN_SHIFT},
	{PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_REDETECT_INTR_EN,
	 PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_REDETECT_INTR_EN_ADDR,
	 PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_REDETECT_INTR_EN_MASK,
	 PMIC_REG_TYPE_C_CC_ENT_SNK_PWR_REDETECT_INTR_EN_SHIFT},
	{PMIC_TYPE_C_CC_ENT_ATTACH_SRC_INTR, PMIC_TYPE_C_CC_ENT_ATTACH_SRC_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_ATTACH_SRC_INTR_MASK,
	 PMIC_TYPE_C_CC_ENT_ATTACH_SRC_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_ATTACH_SNK_INTR, PMIC_TYPE_C_CC_ENT_ATTACH_SNK_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_ATTACH_SNK_INTR_MASK,
	 PMIC_TYPE_C_CC_ENT_ATTACH_SNK_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_AUDIO_ACC_INTR, PMIC_TYPE_C_CC_ENT_AUDIO_ACC_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_AUDIO_ACC_INTR_MASK,
	 PMIC_TYPE_C_CC_ENT_AUDIO_ACC_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_DBG_ACC_INTR, PMIC_TYPE_C_CC_ENT_DBG_ACC_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_DBG_ACC_INTR_MASK, PMIC_TYPE_C_CC_ENT_DBG_ACC_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_DISABLE_INTR, PMIC_TYPE_C_CC_ENT_DISABLE_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_DISABLE_INTR_MASK, PMIC_TYPE_C_CC_ENT_DISABLE_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_UNATTACH_SRC_INTR, PMIC_TYPE_C_CC_ENT_UNATTACH_SRC_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_UNATTACH_SRC_INTR_MASK,
	 PMIC_TYPE_C_CC_ENT_UNATTACH_SRC_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_UNATTACH_SNK_INTR, PMIC_TYPE_C_CC_ENT_UNATTACH_SNK_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_UNATTACH_SNK_INTR_MASK,
	 PMIC_TYPE_C_CC_ENT_UNATTACH_SNK_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_ATTACH_WAIT_SRC_INTR,
	 PMIC_TYPE_C_CC_ENT_ATTACH_WAIT_SRC_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_ATTACH_WAIT_SRC_INTR_MASK,
	 PMIC_TYPE_C_CC_ENT_ATTACH_WAIT_SRC_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_ATTACH_WAIT_SNK_INTR,
	 PMIC_TYPE_C_CC_ENT_ATTACH_WAIT_SNK_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_ATTACH_WAIT_SNK_INTR_MASK,
	 PMIC_TYPE_C_CC_ENT_ATTACH_WAIT_SNK_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_TRY_SRC_INTR, PMIC_TYPE_C_CC_ENT_TRY_SRC_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_TRY_SRC_INTR_MASK, PMIC_TYPE_C_CC_ENT_TRY_SRC_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_TRY_WAIT_SNK_INTR, PMIC_TYPE_C_CC_ENT_TRY_WAIT_SNK_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_TRY_WAIT_SNK_INTR_MASK,
	 PMIC_TYPE_C_CC_ENT_TRY_WAIT_SNK_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_UNATTACH_ACC_INTR, PMIC_TYPE_C_CC_ENT_UNATTACH_ACC_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_UNATTACH_ACC_INTR_MASK,
	 PMIC_TYPE_C_CC_ENT_UNATTACH_ACC_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_ATTACH_WAIT_ACC_INTR,
	 PMIC_TYPE_C_CC_ENT_ATTACH_WAIT_ACC_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_ATTACH_WAIT_ACC_INTR_MASK,
	 PMIC_TYPE_C_CC_ENT_ATTACH_WAIT_ACC_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_SNK_PWR_IDLE_INTR, PMIC_TYPE_C_CC_ENT_SNK_PWR_IDLE_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_SNK_PWR_IDLE_INTR_MASK,
	 PMIC_TYPE_C_CC_ENT_SNK_PWR_IDLE_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_SNK_PWR_DEFAULT_INTR,
	 PMIC_TYPE_C_CC_ENT_SNK_PWR_DEFAULT_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_SNK_PWR_DEFAULT_INTR_MASK,
	 PMIC_TYPE_C_CC_ENT_SNK_PWR_DEFAULT_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_SNK_PWR_15_INTR, PMIC_TYPE_C_CC_ENT_SNK_PWR_15_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_SNK_PWR_15_INTR_MASK,
	 PMIC_TYPE_C_CC_ENT_SNK_PWR_15_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_SNK_PWR_30_INTR, PMIC_TYPE_C_CC_ENT_SNK_PWR_30_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_SNK_PWR_30_INTR_MASK,
	 PMIC_TYPE_C_CC_ENT_SNK_PWR_30_INTR_SHIFT},
	{PMIC_TYPE_C_CC_ENT_SNK_PWR_REDETECT_INTR,
	 PMIC_TYPE_C_CC_ENT_SNK_PWR_REDETECT_INTR_ADDR,
	 PMIC_TYPE_C_CC_ENT_SNK_PWR_REDETECT_INTR_MASK,
	 PMIC_TYPE_C_CC_ENT_SNK_PWR_REDETECT_INTR_SHIFT},
	{PMIC_RO_TYPE_C_CC_ST, PMIC_RO_TYPE_C_CC_ST_ADDR, PMIC_RO_TYPE_C_CC_ST_MASK,
	 PMIC_RO_TYPE_C_CC_ST_SHIFT},
	{PMIC_RO_TYPE_C_ROUTED_CC, PMIC_RO_TYPE_C_ROUTED_CC_ADDR,
	 PMIC_RO_TYPE_C_ROUTED_CC_MASK, PMIC_RO_TYPE_C_ROUTED_CC_SHIFT},
	{PMIC_RO_TYPE_C_CC_SNK_PWR_ST, PMIC_RO_TYPE_C_CC_SNK_PWR_ST_ADDR,
	 PMIC_RO_TYPE_C_CC_SNK_PWR_ST_MASK, PMIC_RO_TYPE_C_CC_SNK_PWR_ST_SHIFT},
	{PMIC_RO_TYPE_C_CC_PWR_ROLE, PMIC_RO_TYPE_C_CC_PWR_ROLE_ADDR,
	 PMIC_RO_TYPE_C_CC_PWR_ROLE_MASK, PMIC_RO_TYPE_C_CC_PWR_ROLE_SHIFT},
	{PMIC_RO_TYPE_C_DRIVE_VCONN_CAPABLE, PMIC_RO_TYPE_C_DRIVE_VCONN_CAPABLE_ADDR,
	 PMIC_RO_TYPE_C_DRIVE_VCONN_CAPABLE_MASK,
	 PMIC_RO_TYPE_C_DRIVE_VCONN_CAPABLE_SHIFT},
	{PMIC_RO_TYPE_C_AD_CC_CMP_OUT, PMIC_RO_TYPE_C_AD_CC_CMP_OUT_ADDR,
	 PMIC_RO_TYPE_C_AD_CC_CMP_OUT_MASK, PMIC_RO_TYPE_C_AD_CC_CMP_OUT_SHIFT},
	{PMIC_RO_AD_CC_VUSB33_RDY, PMIC_RO_AD_CC_VUSB33_RDY_ADDR,
	 PMIC_RO_AD_CC_VUSB33_RDY_MASK, PMIC_RO_AD_CC_VUSB33_RDY_SHIFT},
	{PMIC_REG_TYPE_C_PHY_RG_CC1_RPDE, PMIC_REG_TYPE_C_PHY_RG_CC1_RPDE_ADDR,
	 PMIC_REG_TYPE_C_PHY_RG_CC1_RPDE_MASK, PMIC_REG_TYPE_C_PHY_RG_CC1_RPDE_SHIFT},
	{PMIC_REG_TYPE_C_PHY_RG_CC1_RP15, PMIC_REG_TYPE_C_PHY_RG_CC1_RP15_ADDR,
	 PMIC_REG_TYPE_C_PHY_RG_CC1_RP15_MASK, PMIC_REG_TYPE_C_PHY_RG_CC1_RP15_SHIFT},
	{PMIC_REG_TYPE_C_PHY_RG_CC1_RP3, PMIC_REG_TYPE_C_PHY_RG_CC1_RP3_ADDR,
	 PMIC_REG_TYPE_C_PHY_RG_CC1_RP3_MASK, PMIC_REG_TYPE_C_PHY_RG_CC1_RP3_SHIFT},
	{PMIC_REG_TYPE_C_PHY_RG_CC1_RD, PMIC_REG_TYPE_C_PHY_RG_CC1_RD_ADDR,
	 PMIC_REG_TYPE_C_PHY_RG_CC1_RD_MASK, PMIC_REG_TYPE_C_PHY_RG_CC1_RD_SHIFT},
	{PMIC_REG_TYPE_C_PHY_RG_CC2_RPDE, PMIC_REG_TYPE_C_PHY_RG_CC2_RPDE_ADDR,
	 PMIC_REG_TYPE_C_PHY_RG_CC2_RPDE_MASK, PMIC_REG_TYPE_C_PHY_RG_CC2_RPDE_SHIFT},
	{PMIC_REG_TYPE_C_PHY_RG_CC2_RP15, PMIC_REG_TYPE_C_PHY_RG_CC2_RP15_ADDR,
	 PMIC_REG_TYPE_C_PHY_RG_CC2_RP15_MASK, PMIC_REG_TYPE_C_PHY_RG_CC2_RP15_SHIFT},
	{PMIC_REG_TYPE_C_PHY_RG_CC2_RP3, PMIC_REG_TYPE_C_PHY_RG_CC2_RP3_ADDR,
	 PMIC_REG_TYPE_C_PHY_RG_CC2_RP3_MASK, PMIC_REG_TYPE_C_PHY_RG_CC2_RP3_SHIFT},
	{PMIC_REG_TYPE_C_PHY_RG_CC2_RD, PMIC_REG_TYPE_C_PHY_RG_CC2_RD_ADDR,
	 PMIC_REG_TYPE_C_PHY_RG_CC2_RD_MASK, PMIC_REG_TYPE_C_PHY_RG_CC2_RD_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_RCC1,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_RCC1_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_RCC1_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_RCC1_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_RCC2,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_RCC2_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_RCC2_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_RCC2_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_LEV_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_LEV_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_LEV_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_LEV_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_SW_SEL,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_SW_SEL_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_SW_SEL_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_SW_SEL_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_BIAS_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_BIAS_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_BIAS_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_BIAS_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_LPF_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_LPF_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_LPF_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_LPF_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_ADCSW_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_ADCSW_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_ADCSW_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_ADCSW_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_SASW_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_SASW_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_SASW_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_SASW_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_SACLK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_SACLK_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_SACLK_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_SACLK_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_IN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_IN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_IN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_IN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_CAL,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_CAL_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_CAL_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_CAL_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_GAIN_CAL,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_GAIN_CAL_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_GAIN_CAL_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_EN_DA_CC_DAC_GAIN_CAL_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RPCC1_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RPCC1_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RPCC1_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RPCC1_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RDCC1_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RDCC1_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RDCC1_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RDCC1_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RACC1_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RACC1_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RACC1_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RACC1_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RPCC2_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RPCC2_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RPCC2_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RPCC2_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RDCC2_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RDCC2_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RDCC2_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RDCC2_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RACC2_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RACC2_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RACC2_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_RACC2_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_LEV_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_LEV_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_LEV_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_LEV_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_SW_SEL,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_SW_SEL_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_SW_SEL_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_SW_SEL_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_BIAS_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_BIAS_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_BIAS_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_BIAS_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_LPF_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_LPF_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_LPF_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_LPF_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_ADCSW_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_ADCSW_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_ADCSW_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_ADCSW_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_SASW_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_SASW_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_SASW_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_SASW_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_EN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_EN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_EN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_EN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_SACLK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_SACLK_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_SACLK_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_SACLK_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_IN,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_IN_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_IN_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_IN_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_CAL,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_CAL_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_CAL_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_CAL_SHIFT},
	{PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_GAIN_CAL,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_GAIN_CAL_ADDR,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_GAIN_CAL_MASK,
	 PMIC_REG_TYPE_C_SW_FORCE_MODE_DA_CC_DAC_GAIN_CAL_SHIFT},
	{PMIC_TYPE_C_DAC_CAL_START, PMIC_TYPE_C_DAC_CAL_START_ADDR,
	 PMIC_TYPE_C_DAC_CAL_START_MASK, PMIC_TYPE_C_DAC_CAL_START_SHIFT},
	{PMIC_REG_TYPE_C_DAC_CAL_STAGE, PMIC_REG_TYPE_C_DAC_CAL_STAGE_ADDR,
	 PMIC_REG_TYPE_C_DAC_CAL_STAGE_MASK, PMIC_REG_TYPE_C_DAC_CAL_STAGE_SHIFT},
	{PMIC_RO_TYPE_C_DAC_OK, PMIC_RO_TYPE_C_DAC_OK_ADDR,
	 PMIC_RO_TYPE_C_DAC_OK_MASK, PMIC_RO_TYPE_C_DAC_OK_SHIFT},
	{PMIC_RO_TYPE_C_DAC_FAIL, PMIC_RO_TYPE_C_DAC_FAIL_ADDR,
	 PMIC_RO_TYPE_C_DAC_FAIL_MASK, PMIC_RO_TYPE_C_DAC_FAIL_SHIFT},
	{PMIC_RO_DA_CC_DAC_CAL, PMIC_RO_DA_CC_DAC_CAL_ADDR,
	 PMIC_RO_DA_CC_DAC_CAL_MASK, PMIC_RO_DA_CC_DAC_CAL_SHIFT},
	{PMIC_RO_DA_CC_DAC_GAIN_CAL, PMIC_RO_DA_CC_DAC_GAIN_CAL_ADDR,
	 PMIC_RO_DA_CC_DAC_GAIN_CAL_MASK, PMIC_RO_DA_CC_DAC_GAIN_CAL_SHIFT},
	{PMIC_REG_TYPE_C_DBG_PORT_SEL_0, PMIC_REG_TYPE_C_DBG_PORT_SEL_0_ADDR,
	 PMIC_REG_TYPE_C_DBG_PORT_SEL_0_MASK, PMIC_REG_TYPE_C_DBG_PORT_SEL_0_SHIFT},
	{PMIC_REG_TYPE_C_DBG_PORT_SEL_1, PMIC_REG_TYPE_C_DBG_PORT_SEL_1_ADDR,
	 PMIC_REG_TYPE_C_DBG_PORT_SEL_1_MASK, PMIC_REG_TYPE_C_DBG_PORT_SEL_1_SHIFT},
	{PMIC_REG_TYPE_C_DBG_MOD_SEL, PMIC_REG_TYPE_C_DBG_MOD_SEL_ADDR,
	 PMIC_REG_TYPE_C_DBG_MOD_SEL_MASK, PMIC_REG_TYPE_C_DBG_MOD_SEL_SHIFT},
	{PMIC_RO_TYPE_C_DBG_OUT_READ_0, PMIC_RO_TYPE_C_DBG_OUT_READ_0_ADDR,
	 PMIC_RO_TYPE_C_DBG_OUT_READ_0_MASK, PMIC_RO_TYPE_C_DBG_OUT_READ_0_SHIFT},
	{PMIC_RO_TYPE_C_DBG_OUT_READ_1, PMIC_RO_TYPE_C_DBG_OUT_READ_1_ADDR,
	 PMIC_RO_TYPE_C_DBG_OUT_READ_1_MASK, PMIC_RO_TYPE_C_DBG_OUT_READ_1_SHIFT},
	{PMIC_HWCID, PMIC_HWCID_ADDR, PMIC_HWCID_MASK, PMIC_HWCID_SHIFT},
	{PMIC_SWCID, PMIC_SWCID_ADDR, PMIC_SWCID_MASK, PMIC_SWCID_SHIFT},
	{PMIC_RG_SRCLKEN_IN0_EN, PMIC_RG_SRCLKEN_IN0_EN_ADDR,
	 PMIC_RG_SRCLKEN_IN0_EN_MASK, PMIC_RG_SRCLKEN_IN0_EN_SHIFT},
	{PMIC_RG_SRCLKEN_IN1_EN, PMIC_RG_SRCLKEN_IN1_EN_ADDR,
	 PMIC_RG_SRCLKEN_IN1_EN_MASK, PMIC_RG_SRCLKEN_IN1_EN_SHIFT},
	{PMIC_RG_OSC_SEL, PMIC_RG_OSC_SEL_ADDR, PMIC_RG_OSC_SEL_MASK,
	 PMIC_RG_OSC_SEL_SHIFT},
	{PMIC_RG_SRCLKEN_IN2_EN, PMIC_RG_SRCLKEN_IN2_EN_ADDR,
	 PMIC_RG_SRCLKEN_IN2_EN_MASK, PMIC_RG_SRCLKEN_IN2_EN_SHIFT},
	{PMIC_RG_SRCLKEN_IN0_HW_MODE, PMIC_RG_SRCLKEN_IN0_HW_MODE_ADDR,
	 PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT},
	{PMIC_RG_SRCLKEN_IN1_HW_MODE, PMIC_RG_SRCLKEN_IN1_HW_MODE_ADDR,
	 PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT},
	{PMIC_RG_OSC_SEL_HW_MODE, PMIC_RG_OSC_SEL_HW_MODE_ADDR,
	 PMIC_RG_OSC_SEL_HW_MODE_MASK, PMIC_RG_OSC_SEL_HW_MODE_SHIFT},
	{PMIC_RG_SRCLKEN_IN_SYNC_EN, PMIC_RG_SRCLKEN_IN_SYNC_EN_ADDR,
	 PMIC_RG_SRCLKEN_IN_SYNC_EN_MASK, PMIC_RG_SRCLKEN_IN_SYNC_EN_SHIFT},
	{PMIC_RG_OSC_EN_AUTO_OFF, PMIC_RG_OSC_EN_AUTO_OFF_ADDR,
	 PMIC_RG_OSC_EN_AUTO_OFF_MASK, PMIC_RG_OSC_EN_AUTO_OFF_SHIFT},
	{PMIC_TEST_OUT, PMIC_TEST_OUT_ADDR, PMIC_TEST_OUT_MASK,
	 PMIC_TEST_OUT_SHIFT},
	{PMIC_RG_MON_FLAG_SEL, PMIC_RG_MON_FLAG_SEL_ADDR, PMIC_RG_MON_FLAG_SEL_MASK,
	 PMIC_RG_MON_FLAG_SEL_SHIFT},
	{PMIC_RG_MON_GRP_SEL, PMIC_RG_MON_GRP_SEL_ADDR, PMIC_RG_MON_GRP_SEL_MASK,
	 PMIC_RG_MON_GRP_SEL_SHIFT},
	{PMIC_RG_NANDTREE_MODE, PMIC_RG_NANDTREE_MODE_ADDR,
	 PMIC_RG_NANDTREE_MODE_MASK, PMIC_RG_NANDTREE_MODE_SHIFT},
	{PMIC_RG_TEST_AUXADC, PMIC_RG_TEST_AUXADC_ADDR, PMIC_RG_TEST_AUXADC_MASK,
	 PMIC_RG_TEST_AUXADC_SHIFT},
	{PMIC_RG_EFUSE_MODE, PMIC_RG_EFUSE_MODE_ADDR, PMIC_RG_EFUSE_MODE_MASK,
	 PMIC_RG_EFUSE_MODE_SHIFT},
	{PMIC_RG_TEST_STRUP, PMIC_RG_TEST_STRUP_ADDR, PMIC_RG_TEST_STRUP_MASK,
	 PMIC_RG_TEST_STRUP_SHIFT},
	{PMIC_TESTMODE_SW, PMIC_TESTMODE_SW_ADDR, PMIC_TESTMODE_SW_MASK,
	 PMIC_TESTMODE_SW_SHIFT},
	{PMIC_EN_STATUS_VDRAM, PMIC_EN_STATUS_VDRAM_ADDR, PMIC_EN_STATUS_VDRAM_MASK,
	 PMIC_EN_STATUS_VDRAM_SHIFT},
	{PMIC_EN_STATUS_VSRAM_PROC, PMIC_EN_STATUS_VSRAM_PROC_ADDR,
	 PMIC_EN_STATUS_VSRAM_PROC_MASK, PMIC_EN_STATUS_VSRAM_PROC_SHIFT},
	{PMIC_EN_STATUS_VAUD28, PMIC_EN_STATUS_VAUD28_ADDR,
	 PMIC_EN_STATUS_VAUD28_MASK, PMIC_EN_STATUS_VAUD28_SHIFT},
	{PMIC_EN_STATUS_VAUX18, PMIC_EN_STATUS_VAUX18_ADDR,
	 PMIC_EN_STATUS_VAUX18_MASK, PMIC_EN_STATUS_VAUX18_SHIFT},
	{PMIC_EN_STATUS_VCAMD, PMIC_EN_STATUS_VCAMD_ADDR, PMIC_EN_STATUS_VCAMD_MASK,
	 PMIC_EN_STATUS_VCAMD_SHIFT},
	{PMIC_EN_STATUS_VLDO28, PMIC_EN_STATUS_VLDO28_ADDR,
	 PMIC_EN_STATUS_VLDO28_MASK, PMIC_EN_STATUS_VLDO28_SHIFT},
	{PMIC_EN_STATUS_VCAMIO, PMIC_EN_STATUS_VCAMIO_ADDR,
	 PMIC_EN_STATUS_VCAMIO_MASK, PMIC_EN_STATUS_VCAMIO_SHIFT},
	{PMIC_EN_STATUS_VCAMA, PMIC_EN_STATUS_VCAMA_ADDR, PMIC_EN_STATUS_VCAMA_MASK,
	 PMIC_EN_STATUS_VCAMA_SHIFT},
	{PMIC_EN_STATUS_VCN18, PMIC_EN_STATUS_VCN18_ADDR, PMIC_EN_STATUS_VCN18_MASK,
	 PMIC_EN_STATUS_VCN18_SHIFT},
	{PMIC_EN_STATUS_VCN28, PMIC_EN_STATUS_VCN28_ADDR, PMIC_EN_STATUS_VCN28_MASK,
	 PMIC_EN_STATUS_VCN28_SHIFT},
	{PMIC_EN_STATUS_VCN33, PMIC_EN_STATUS_VCN33_ADDR, PMIC_EN_STATUS_VCN33_MASK,
	 PMIC_EN_STATUS_VCN33_SHIFT},
	{PMIC_EN_STATUS_VRF12, PMIC_EN_STATUS_VRF12_ADDR, PMIC_EN_STATUS_VRF12_MASK,
	 PMIC_EN_STATUS_VRF12_SHIFT},
	{PMIC_EN_STATUS_VRF18, PMIC_EN_STATUS_VRF18_ADDR, PMIC_EN_STATUS_VRF18_MASK,
	 PMIC_EN_STATUS_VRF18_SHIFT},
	{PMIC_EN_STATUS_VXO22, PMIC_EN_STATUS_VXO22_ADDR, PMIC_EN_STATUS_VXO22_MASK,
	 PMIC_EN_STATUS_VXO22_SHIFT},
	{PMIC_EN_STATUS_VTCXO24, PMIC_EN_STATUS_VTCXO24_ADDR,
	 PMIC_EN_STATUS_VTCXO24_MASK, PMIC_EN_STATUS_VTCXO24_SHIFT},
	{PMIC_EN_STATUS_VTCXO28, PMIC_EN_STATUS_VTCXO28_ADDR,
	 PMIC_EN_STATUS_VTCXO28_MASK, PMIC_EN_STATUS_VTCXO28_SHIFT},
	{PMIC_EN_STATUS_VS1, PMIC_EN_STATUS_VS1_ADDR, PMIC_EN_STATUS_VS1_MASK,
	 PMIC_EN_STATUS_VS1_SHIFT},
	{PMIC_EN_STATUS_VCORE, PMIC_EN_STATUS_VCORE_ADDR, PMIC_EN_STATUS_VCORE_MASK,
	 PMIC_EN_STATUS_VCORE_SHIFT},
	{PMIC_EN_STATUS_VPROC, PMIC_EN_STATUS_VPROC_ADDR, PMIC_EN_STATUS_VPROC_MASK,
	 PMIC_EN_STATUS_VPROC_SHIFT},
	{PMIC_EN_STATUS_VPA, PMIC_EN_STATUS_VPA_ADDR, PMIC_EN_STATUS_VPA_MASK,
	 PMIC_EN_STATUS_VPA_SHIFT},
	{PMIC_EN_STATUS_VRTC, PMIC_EN_STATUS_VRTC_ADDR, PMIC_EN_STATUS_VRTC_MASK,
	 PMIC_EN_STATUS_VRTC_SHIFT},
	{PMIC_EN_STATUS_TREF, PMIC_EN_STATUS_TREF_ADDR, PMIC_EN_STATUS_TREF_MASK,
	 PMIC_EN_STATUS_TREF_SHIFT},
	{PMIC_EN_STATUS_VIBR, PMIC_EN_STATUS_VIBR_ADDR, PMIC_EN_STATUS_VIBR_MASK,
	 PMIC_EN_STATUS_VIBR_SHIFT},
	{PMIC_EN_STATUS_VIO18, PMIC_EN_STATUS_VIO18_ADDR, PMIC_EN_STATUS_VIO18_MASK,
	 PMIC_EN_STATUS_VIO18_SHIFT},
	{PMIC_EN_STATUS_VEMC33, PMIC_EN_STATUS_VEMC33_ADDR,
	 PMIC_EN_STATUS_VEMC33_MASK, PMIC_EN_STATUS_VEMC33_SHIFT},
	{PMIC_EN_STATUS_VUSB33, PMIC_EN_STATUS_VUSB33_ADDR,
	 PMIC_EN_STATUS_VUSB33_MASK, PMIC_EN_STATUS_VUSB33_SHIFT},
	{PMIC_EN_STATUS_VMCH, PMIC_EN_STATUS_VMCH_ADDR, PMIC_EN_STATUS_VMCH_MASK,
	 PMIC_EN_STATUS_VMCH_SHIFT},
	{PMIC_EN_STATUS_VMC, PMIC_EN_STATUS_VMC_ADDR, PMIC_EN_STATUS_VMC_MASK,
	 PMIC_EN_STATUS_VMC_SHIFT},
	{PMIC_EN_STATUS_VIO28, PMIC_EN_STATUS_VIO28_ADDR, PMIC_EN_STATUS_VIO28_MASK,
	 PMIC_EN_STATUS_VIO28_SHIFT},
	{PMIC_EN_STATUS_VSIM2, PMIC_EN_STATUS_VSIM2_ADDR, PMIC_EN_STATUS_VSIM2_MASK,
	 PMIC_EN_STATUS_VSIM2_SHIFT},
	{PMIC_EN_STATUS_VSIM1, PMIC_EN_STATUS_VSIM1_ADDR, PMIC_EN_STATUS_VSIM1_MASK,
	 PMIC_EN_STATUS_VSIM1_SHIFT},
	{PMIC_OC_STATUS_VDRAM, PMIC_OC_STATUS_VDRAM_ADDR, PMIC_OC_STATUS_VDRAM_MASK,
	 PMIC_OC_STATUS_VDRAM_SHIFT},
	{PMIC_OC_STATUS_VSRAM_PROC, PMIC_OC_STATUS_VSRAM_PROC_ADDR,
	 PMIC_OC_STATUS_VSRAM_PROC_MASK, PMIC_OC_STATUS_VSRAM_PROC_SHIFT},
	{PMIC_OC_STATUS_VAUD28, PMIC_OC_STATUS_VAUD28_ADDR,
	 PMIC_OC_STATUS_VAUD28_MASK, PMIC_OC_STATUS_VAUD28_SHIFT},
	{PMIC_OC_STATUS_VAUX18, PMIC_OC_STATUS_VAUX18_ADDR,
	 PMIC_OC_STATUS_VAUX18_MASK, PMIC_OC_STATUS_VAUX18_SHIFT},
	{PMIC_OC_STATUS_VCAMD, PMIC_OC_STATUS_VCAMD_ADDR, PMIC_OC_STATUS_VCAMD_MASK,
	 PMIC_OC_STATUS_VCAMD_SHIFT},
	{PMIC_OC_STATUS_VLDO28, PMIC_OC_STATUS_VLDO28_ADDR,
	 PMIC_OC_STATUS_VLDO28_MASK, PMIC_OC_STATUS_VLDO28_SHIFT},
	{PMIC_OC_STATUS_VCAMIO, PMIC_OC_STATUS_VCAMIO_ADDR,
	 PMIC_OC_STATUS_VCAMIO_MASK, PMIC_OC_STATUS_VCAMIO_SHIFT},
	{PMIC_OC_STATUS_VCAMA, PMIC_OC_STATUS_VCAMA_ADDR, PMIC_OC_STATUS_VCAMA_MASK,
	 PMIC_OC_STATUS_VCAMA_SHIFT},
	{PMIC_OC_STATUS_VCN18, PMIC_OC_STATUS_VCN18_ADDR, PMIC_OC_STATUS_VCN18_MASK,
	 PMIC_OC_STATUS_VCN18_SHIFT},
	{PMIC_OC_STATUS_VCN28, PMIC_OC_STATUS_VCN28_ADDR, PMIC_OC_STATUS_VCN28_MASK,
	 PMIC_OC_STATUS_VCN28_SHIFT},
	{PMIC_OC_STATUS_VCN33, PMIC_OC_STATUS_VCN33_ADDR, PMIC_OC_STATUS_VCN33_MASK,
	 PMIC_OC_STATUS_VCN33_SHIFT},
	{PMIC_OC_STATUS_VRF12, PMIC_OC_STATUS_VRF12_ADDR, PMIC_OC_STATUS_VRF12_MASK,
	 PMIC_OC_STATUS_VRF12_SHIFT},
	{PMIC_OC_STATUS_VRF18, PMIC_OC_STATUS_VRF18_ADDR, PMIC_OC_STATUS_VRF18_MASK,
	 PMIC_OC_STATUS_VRF18_SHIFT},
	{PMIC_OC_STATUS_VXO22, PMIC_OC_STATUS_VXO22_ADDR, PMIC_OC_STATUS_VXO22_MASK,
	 PMIC_OC_STATUS_VXO22_SHIFT},
	{PMIC_OC_STATUS_VTCXO24, PMIC_OC_STATUS_VTCXO24_ADDR,
	 PMIC_OC_STATUS_VTCXO24_MASK, PMIC_OC_STATUS_VTCXO24_SHIFT},
	{PMIC_OC_STATUS_VTCXO28, PMIC_OC_STATUS_VTCXO28_ADDR,
	 PMIC_OC_STATUS_VTCXO28_MASK, PMIC_OC_STATUS_VTCXO28_SHIFT},
	{PMIC_OC_STATUS_VS1, PMIC_OC_STATUS_VS1_ADDR, PMIC_OC_STATUS_VS1_MASK,
	 PMIC_OC_STATUS_VS1_SHIFT},
	{PMIC_OC_STATUS_VCORE, PMIC_OC_STATUS_VCORE_ADDR, PMIC_OC_STATUS_VCORE_MASK,
	 PMIC_OC_STATUS_VCORE_SHIFT},
	{PMIC_OC_STATUS_VPROC, PMIC_OC_STATUS_VPROC_ADDR, PMIC_OC_STATUS_VPROC_MASK,
	 PMIC_OC_STATUS_VPROC_SHIFT},
	{PMIC_OC_STATUS_VPA, PMIC_OC_STATUS_VPA_ADDR, PMIC_OC_STATUS_VPA_MASK,
	 PMIC_OC_STATUS_VPA_SHIFT},
	{PMIC_OC_STATUS_TREF, PMIC_OC_STATUS_TREF_ADDR, PMIC_OC_STATUS_TREF_MASK,
	 PMIC_OC_STATUS_TREF_SHIFT},
	{PMIC_OC_STATUS_VIBR, PMIC_OC_STATUS_VIBR_ADDR, PMIC_OC_STATUS_VIBR_MASK,
	 PMIC_OC_STATUS_VIBR_SHIFT},
	{PMIC_OC_STATUS_VIO18, PMIC_OC_STATUS_VIO18_ADDR, PMIC_OC_STATUS_VIO18_MASK,
	 PMIC_OC_STATUS_VIO18_SHIFT},
	{PMIC_OC_STATUS_VEMC33, PMIC_OC_STATUS_VEMC33_ADDR,
	 PMIC_OC_STATUS_VEMC33_MASK, PMIC_OC_STATUS_VEMC33_SHIFT},
	{PMIC_OC_STATUS_VUSB33, PMIC_OC_STATUS_VUSB33_ADDR,
	 PMIC_OC_STATUS_VUSB33_MASK, PMIC_OC_STATUS_VUSB33_SHIFT},
	{PMIC_OC_STATUS_VMCH, PMIC_OC_STATUS_VMCH_ADDR, PMIC_OC_STATUS_VMCH_MASK,
	 PMIC_OC_STATUS_VMCH_SHIFT},
	{PMIC_OC_STATUS_VMC, PMIC_OC_STATUS_VMC_ADDR, PMIC_OC_STATUS_VMC_MASK,
	 PMIC_OC_STATUS_VMC_SHIFT},
	{PMIC_OC_STATUS_VIO28, PMIC_OC_STATUS_VIO28_ADDR, PMIC_OC_STATUS_VIO28_MASK,
	 PMIC_OC_STATUS_VIO28_SHIFT},
	{PMIC_OC_STATUS_VSIM2, PMIC_OC_STATUS_VSIM2_ADDR, PMIC_OC_STATUS_VSIM2_MASK,
	 PMIC_OC_STATUS_VSIM2_SHIFT},
	{PMIC_OC_STATUS_VSIM1, PMIC_OC_STATUS_VSIM1_ADDR, PMIC_OC_STATUS_VSIM1_MASK,
	 PMIC_OC_STATUS_VSIM1_SHIFT},
	{PMIC_VCORE2_PG_DEB, PMIC_VCORE2_PG_DEB_ADDR, PMIC_VCORE2_PG_DEB_MASK,
	 PMIC_VCORE2_PG_DEB_SHIFT},
	{PMIC_VS1_PG_DEB, PMIC_VS1_PG_DEB_ADDR, PMIC_VS1_PG_DEB_MASK,
	 PMIC_VS1_PG_DEB_SHIFT},
	{PMIC_VCORE_PG_DEB, PMIC_VCORE_PG_DEB_ADDR, PMIC_VCORE_PG_DEB_MASK,
	 PMIC_VCORE_PG_DEB_SHIFT},
	{PMIC_VPROC_PG_DEB, PMIC_VPROC_PG_DEB_ADDR, PMIC_VPROC_PG_DEB_MASK,
	 PMIC_VPROC_PG_DEB_SHIFT},
	{PMIC_VIO18_PG_DEB, PMIC_VIO18_PG_DEB_ADDR, PMIC_VIO18_PG_DEB_MASK,
	 PMIC_VIO18_PG_DEB_SHIFT},
	{PMIC_VEMC33_PG_DEB, PMIC_VEMC33_PG_DEB_ADDR, PMIC_VEMC33_PG_DEB_MASK,
	 PMIC_VEMC33_PG_DEB_SHIFT},
	{PMIC_VUSB33_PG_DEB, PMIC_VUSB33_PG_DEB_ADDR, PMIC_VUSB33_PG_DEB_MASK,
	 PMIC_VUSB33_PG_DEB_SHIFT},
	{PMIC_VMCH_PG_DEB, PMIC_VMCH_PG_DEB_ADDR, PMIC_VMCH_PG_DEB_MASK,
	 PMIC_VMCH_PG_DEB_SHIFT},
	{PMIC_VMC_PG_DEB, PMIC_VMC_PG_DEB_ADDR, PMIC_VMC_PG_DEB_MASK,
	 PMIC_VMC_PG_DEB_SHIFT},
	{PMIC_VIO28_PG_DEB, PMIC_VIO28_PG_DEB_ADDR, PMIC_VIO28_PG_DEB_MASK,
	 PMIC_VIO28_PG_DEB_SHIFT},
	{PMIC_VDRAM_PG_DEB, PMIC_VDRAM_PG_DEB_ADDR, PMIC_VDRAM_PG_DEB_MASK,
	 PMIC_VDRAM_PG_DEB_SHIFT},
	{PMIC_VSRAM_PROC_PG_DEB, PMIC_VSRAM_PROC_PG_DEB_ADDR,
	 PMIC_VSRAM_PROC_PG_DEB_MASK, PMIC_VSRAM_PROC_PG_DEB_SHIFT},
	{PMIC_VAUD28_PG_DEB, PMIC_VAUD28_PG_DEB_ADDR, PMIC_VAUD28_PG_DEB_MASK,
	 PMIC_VAUD28_PG_DEB_SHIFT},
	{PMIC_VAUX18_PG_DEB, PMIC_VAUX18_PG_DEB_ADDR, PMIC_VAUX18_PG_DEB_MASK,
	 PMIC_VAUX18_PG_DEB_SHIFT},
	{PMIC_VXO22_PG_DEB, PMIC_VXO22_PG_DEB_ADDR, PMIC_VXO22_PG_DEB_MASK,
	 PMIC_VXO22_PG_DEB_SHIFT},
	{PMIC_VTCXO24_PG_DEB, PMIC_VTCXO24_PG_DEB_ADDR, PMIC_VTCXO24_PG_DEB_MASK,
	 PMIC_VTCXO24_PG_DEB_SHIFT},
	{PMIC_STRUP_VMCH_PG_STATUS_GATED, PMIC_STRUP_VMCH_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VMCH_PG_STATUS_GATED_MASK, PMIC_STRUP_VMCH_PG_STATUS_GATED_SHIFT},
	{PMIC_STRUP_VMC_PG_STATUS_GATED, PMIC_STRUP_VMC_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VMC_PG_STATUS_GATED_MASK, PMIC_STRUP_VMC_PG_STATUS_GATED_SHIFT},
	{PMIC_STRUP_VXO22_PG_STATUS_GATED, PMIC_STRUP_VXO22_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VXO22_PG_STATUS_GATED_MASK,
	 PMIC_STRUP_VXO22_PG_STATUS_GATED_SHIFT},
	{PMIC_STRUP_VTCXO24_PG_STATUS_GATED, PMIC_STRUP_VTCXO24_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VTCXO24_PG_STATUS_GATED_MASK,
	 PMIC_STRUP_VTCXO24_PG_STATUS_GATED_SHIFT},
	{PMIC_STRUP_VUSB33_PG_STATUS_GATED, PMIC_STRUP_VUSB33_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VUSB33_PG_STATUS_GATED_MASK,
	 PMIC_STRUP_VUSB33_PG_STATUS_GATED_SHIFT},
	{PMIC_STRUP_VSRAM_PROC_PG_STATUS_GATED, PMIC_STRUP_VSRAM_PROC_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VSRAM_PROC_PG_STATUS_GATED_MASK,
	 PMIC_STRUP_VSRAM_PROC_PG_STATUS_GATED_SHIFT},
	{PMIC_STRUP_VPROC_PG_STATUS_GATED, PMIC_STRUP_VPROC_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VPROC_PG_STATUS_GATED_MASK,
	 PMIC_STRUP_VPROC_PG_STATUS_GATED_SHIFT},
	{PMIC_STRUP_VDRAM_PG_STATUS_GATED, PMIC_STRUP_VDRAM_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VDRAM_PG_STATUS_GATED_MASK,
	 PMIC_STRUP_VDRAM_PG_STATUS_GATED_SHIFT},
	{PMIC_STRUP_VAUD28_PG_STATUS_GATED, PMIC_STRUP_VAUD28_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VAUD28_PG_STATUS_GATED_MASK,
	 PMIC_STRUP_VAUD28_PG_STATUS_GATED_SHIFT},
	{PMIC_STRUP_VIO28_PG_STATUS_GATED, PMIC_STRUP_VIO28_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VIO28_PG_STATUS_GATED_MASK,
	 PMIC_STRUP_VIO28_PG_STATUS_GATED_SHIFT},
	{PMIC_STRUP_VEMC33_PG_STATUS_GATED, PMIC_STRUP_VEMC33_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VEMC33_PG_STATUS_GATED_MASK,
	 PMIC_STRUP_VEMC33_PG_STATUS_GATED_SHIFT},
	{PMIC_STRUP_VIO18_PG_STATUS_GATED, PMIC_STRUP_VIO18_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VIO18_PG_STATUS_GATED_MASK,
	 PMIC_STRUP_VIO18_PG_STATUS_GATED_SHIFT},
	{PMIC_STRUP_VS1_PG_STATUS_GATED, PMIC_STRUP_VS1_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VS1_PG_STATUS_GATED_MASK, PMIC_STRUP_VS1_PG_STATUS_GATED_SHIFT},
	{PMIC_STRUP_VCORE_PG_STATUS_GATED, PMIC_STRUP_VCORE_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VCORE_PG_STATUS_GATED_MASK,
	 PMIC_STRUP_VCORE_PG_STATUS_GATED_SHIFT},
	{PMIC_STRUP_VAUX18_PG_STATUS_GATED, PMIC_STRUP_VAUX18_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VAUX18_PG_STATUS_GATED_MASK,
	 PMIC_STRUP_VAUX18_PG_STATUS_GATED_SHIFT},
	{PMIC_STRUP_VCORE2_PG_STATUS_GATED, PMIC_STRUP_VCORE2_PG_STATUS_GATED_ADDR,
	 PMIC_STRUP_VCORE2_PG_STATUS_GATED_MASK,
	 PMIC_STRUP_VCORE2_PG_STATUS_GATED_SHIFT},
	{PMIC_PMU_THERMAL_DEB, PMIC_PMU_THERMAL_DEB_ADDR, PMIC_PMU_THERMAL_DEB_MASK,
	 PMIC_PMU_THERMAL_DEB_SHIFT},
	{PMIC_STRUP_THERMAL_STATUS, PMIC_STRUP_THERMAL_STATUS_ADDR,
	 PMIC_STRUP_THERMAL_STATUS_MASK, PMIC_STRUP_THERMAL_STATUS_SHIFT},
	{PMIC_PMU_TEST_MODE_SCAN, PMIC_PMU_TEST_MODE_SCAN_ADDR,
	 PMIC_PMU_TEST_MODE_SCAN_MASK, PMIC_PMU_TEST_MODE_SCAN_SHIFT},
	{PMIC_PWRKEY_DEB, PMIC_PWRKEY_DEB_ADDR, PMIC_PWRKEY_DEB_MASK,
	 PMIC_PWRKEY_DEB_SHIFT},
	{PMIC_HOMEKEY_DEB, PMIC_HOMEKEY_DEB_ADDR, PMIC_HOMEKEY_DEB_MASK,
	 PMIC_HOMEKEY_DEB_SHIFT},
	{PMIC_RTC_XTAL_DET_DONE, PMIC_RTC_XTAL_DET_DONE_ADDR,
	 PMIC_RTC_XTAL_DET_DONE_MASK, PMIC_RTC_XTAL_DET_DONE_SHIFT},
	{PMIC_XOSC32_ENB_DET, PMIC_XOSC32_ENB_DET_ADDR, PMIC_XOSC32_ENB_DET_MASK,
	 PMIC_XOSC32_ENB_DET_SHIFT},
	{PMIC_RTC_XTAL_DET_RSV, PMIC_RTC_XTAL_DET_RSV_ADDR,
	 PMIC_RTC_XTAL_DET_RSV_MASK, PMIC_RTC_XTAL_DET_RSV_SHIFT},
	{PMIC_RG_PMU_TDSEL, PMIC_RG_PMU_TDSEL_ADDR, PMIC_RG_PMU_TDSEL_MASK,
	 PMIC_RG_PMU_TDSEL_SHIFT},
	{PMIC_RG_SPI_TDSEL, PMIC_RG_SPI_TDSEL_ADDR, PMIC_RG_SPI_TDSEL_MASK,
	 PMIC_RG_SPI_TDSEL_SHIFT},
	{PMIC_RG_AUD_TDSEL, PMIC_RG_AUD_TDSEL_ADDR, PMIC_RG_AUD_TDSEL_MASK,
	 PMIC_RG_AUD_TDSEL_SHIFT},
	{PMIC_RG_E32CAL_TDSEL, PMIC_RG_E32CAL_TDSEL_ADDR, PMIC_RG_E32CAL_TDSEL_MASK,
	 PMIC_RG_E32CAL_TDSEL_SHIFT},
	{PMIC_RG_PMU_RDSEL, PMIC_RG_PMU_RDSEL_ADDR, PMIC_RG_PMU_RDSEL_MASK,
	 PMIC_RG_PMU_RDSEL_SHIFT},
	{PMIC_RG_SPI_RDSEL, PMIC_RG_SPI_RDSEL_ADDR, PMIC_RG_SPI_RDSEL_MASK,
	 PMIC_RG_SPI_RDSEL_SHIFT},
	{PMIC_RG_AUD_RDSEL, PMIC_RG_AUD_RDSEL_ADDR, PMIC_RG_AUD_RDSEL_MASK,
	 PMIC_RG_AUD_RDSEL_SHIFT},
	{PMIC_RG_E32CAL_RDSEL, PMIC_RG_E32CAL_RDSEL_ADDR, PMIC_RG_E32CAL_RDSEL_MASK,
	 PMIC_RG_E32CAL_RDSEL_SHIFT},
	{PMIC_RG_SMT_WDTRSTB_IN, PMIC_RG_SMT_WDTRSTB_IN_ADDR,
	 PMIC_RG_SMT_WDTRSTB_IN_MASK, PMIC_RG_SMT_WDTRSTB_IN_SHIFT},
	{PMIC_RG_SMT_HOMEKEY, PMIC_RG_SMT_HOMEKEY_ADDR, PMIC_RG_SMT_HOMEKEY_MASK,
	 PMIC_RG_SMT_HOMEKEY_SHIFT},
	{PMIC_RG_SMT_SRCLKEN_IN0, PMIC_RG_SMT_SRCLKEN_IN0_ADDR,
	 PMIC_RG_SMT_SRCLKEN_IN0_MASK, PMIC_RG_SMT_SRCLKEN_IN0_SHIFT},
	{PMIC_RG_SMT_SRCLKEN_IN1, PMIC_RG_SMT_SRCLKEN_IN1_ADDR,
	 PMIC_RG_SMT_SRCLKEN_IN1_MASK, PMIC_RG_SMT_SRCLKEN_IN1_SHIFT},
	{PMIC_RG_SMT_RTC_32K1V8_0, PMIC_RG_SMT_RTC_32K1V8_0_ADDR,
	 PMIC_RG_SMT_RTC_32K1V8_0_MASK, PMIC_RG_SMT_RTC_32K1V8_0_SHIFT},
	{PMIC_RG_SMT_RTC_32K1V8_1, PMIC_RG_SMT_RTC_32K1V8_1_ADDR,
	 PMIC_RG_SMT_RTC_32K1V8_1_MASK, PMIC_RG_SMT_RTC_32K1V8_1_SHIFT},
	{PMIC_RG_SMT_SPI_CLK, PMIC_RG_SMT_SPI_CLK_ADDR, PMIC_RG_SMT_SPI_CLK_MASK,
	 PMIC_RG_SMT_SPI_CLK_SHIFT},
	{PMIC_RG_SMT_SPI_CSN, PMIC_RG_SMT_SPI_CSN_ADDR, PMIC_RG_SMT_SPI_CSN_MASK,
	 PMIC_RG_SMT_SPI_CSN_SHIFT},
	{PMIC_RG_SMT_SPI_MOSI, PMIC_RG_SMT_SPI_MOSI_ADDR, PMIC_RG_SMT_SPI_MOSI_MASK,
	 PMIC_RG_SMT_SPI_MOSI_SHIFT},
	{PMIC_RG_SMT_SPI_MISO, PMIC_RG_SMT_SPI_MISO_ADDR, PMIC_RG_SMT_SPI_MISO_MASK,
	 PMIC_RG_SMT_SPI_MISO_SHIFT},
	{PMIC_RG_SMT_AUD_CLK, PMIC_RG_SMT_AUD_CLK_ADDR, PMIC_RG_SMT_AUD_CLK_MASK,
	 PMIC_RG_SMT_AUD_CLK_SHIFT},
	{PMIC_RG_SMT_AUD_DAT_MOSI, PMIC_RG_SMT_AUD_DAT_MOSI_ADDR,
	 PMIC_RG_SMT_AUD_DAT_MOSI_MASK, PMIC_RG_SMT_AUD_DAT_MOSI_SHIFT},
	{PMIC_RG_SMT_AUD_DAT_MISO, PMIC_RG_SMT_AUD_DAT_MISO_ADDR,
	 PMIC_RG_SMT_AUD_DAT_MISO_MASK, PMIC_RG_SMT_AUD_DAT_MISO_SHIFT},
	{PMIC_RG_SMT_ANC_DAT_MOSI, PMIC_RG_SMT_ANC_DAT_MOSI_ADDR,
	 PMIC_RG_SMT_ANC_DAT_MOSI_MASK, PMIC_RG_SMT_ANC_DAT_MOSI_SHIFT},
	{PMIC_RG_SMT_VOW_CLK_MISO, PMIC_RG_SMT_VOW_CLK_MISO_ADDR,
	 PMIC_RG_SMT_VOW_CLK_MISO_MASK, PMIC_RG_SMT_VOW_CLK_MISO_SHIFT},
	{PMIC_RG_SMT_ENBB, PMIC_RG_SMT_ENBB_ADDR, PMIC_RG_SMT_ENBB_MASK,
	 PMIC_RG_SMT_ENBB_SHIFT},
	{PMIC_RG_SMT_XOSC_EN, PMIC_RG_SMT_XOSC_EN_ADDR, PMIC_RG_SMT_XOSC_EN_MASK,
	 PMIC_RG_SMT_XOSC_EN_SHIFT},
	{PMIC_RG_OCTL_SRCLKEN_IN0, PMIC_RG_OCTL_SRCLKEN_IN0_ADDR,
	 PMIC_RG_OCTL_SRCLKEN_IN0_MASK, PMIC_RG_OCTL_SRCLKEN_IN0_SHIFT},
	{PMIC_RG_OCTL_SRCLKEN_IN1, PMIC_RG_OCTL_SRCLKEN_IN1_ADDR,
	 PMIC_RG_OCTL_SRCLKEN_IN1_MASK, PMIC_RG_OCTL_SRCLKEN_IN1_SHIFT},
	{PMIC_RG_OCTL_RTC_32K1V8_0, PMIC_RG_OCTL_RTC_32K1V8_0_ADDR,
	 PMIC_RG_OCTL_RTC_32K1V8_0_MASK, PMIC_RG_OCTL_RTC_32K1V8_0_SHIFT},
	{PMIC_RG_OCTL_RTC_32K1V8_1, PMIC_RG_OCTL_RTC_32K1V8_1_ADDR,
	 PMIC_RG_OCTL_RTC_32K1V8_1_MASK, PMIC_RG_OCTL_RTC_32K1V8_1_SHIFT},
	{PMIC_RG_OCTL_SPI_CLK, PMIC_RG_OCTL_SPI_CLK_ADDR, PMIC_RG_OCTL_SPI_CLK_MASK,
	 PMIC_RG_OCTL_SPI_CLK_SHIFT},
	{PMIC_RG_OCTL_SPI_CSN, PMIC_RG_OCTL_SPI_CSN_ADDR, PMIC_RG_OCTL_SPI_CSN_MASK,
	 PMIC_RG_OCTL_SPI_CSN_SHIFT},
	{PMIC_RG_OCTL_SPI_MOSI, PMIC_RG_OCTL_SPI_MOSI_ADDR,
	 PMIC_RG_OCTL_SPI_MOSI_MASK, PMIC_RG_OCTL_SPI_MOSI_SHIFT},
	{PMIC_RG_OCTL_SPI_MISO, PMIC_RG_OCTL_SPI_MISO_ADDR,
	 PMIC_RG_OCTL_SPI_MISO_MASK, PMIC_RG_OCTL_SPI_MISO_SHIFT},
	{PMIC_RG_OCTL_AUD_DAT_MOSI, PMIC_RG_OCTL_AUD_DAT_MOSI_ADDR,
	 PMIC_RG_OCTL_AUD_DAT_MOSI_MASK, PMIC_RG_OCTL_AUD_DAT_MOSI_SHIFT},
	{PMIC_RG_OCTL_AUD_DAT_MISO, PMIC_RG_OCTL_AUD_DAT_MISO_ADDR,
	 PMIC_RG_OCTL_AUD_DAT_MISO_MASK, PMIC_RG_OCTL_AUD_DAT_MISO_SHIFT},
	{PMIC_RG_OCTL_AUD_CLK, PMIC_RG_OCTL_AUD_CLK_ADDR, PMIC_RG_OCTL_AUD_CLK_MASK,
	 PMIC_RG_OCTL_AUD_CLK_SHIFT},
	{PMIC_RG_OCTL_ANC_DAT_MOSI, PMIC_RG_OCTL_ANC_DAT_MOSI_ADDR,
	 PMIC_RG_OCTL_ANC_DAT_MOSI_MASK, PMIC_RG_OCTL_ANC_DAT_MOSI_SHIFT},
	{PMIC_RG_OCTL_HOMEKEY, PMIC_RG_OCTL_HOMEKEY_ADDR, PMIC_RG_OCTL_HOMEKEY_MASK,
	 PMIC_RG_OCTL_HOMEKEY_SHIFT},
	{PMIC_RG_OCTL_ENBB, PMIC_RG_OCTL_ENBB_ADDR, PMIC_RG_OCTL_ENBB_MASK,
	 PMIC_RG_OCTL_ENBB_SHIFT},
	{PMIC_RG_OCTL_XOSC_EN, PMIC_RG_OCTL_XOSC_EN_ADDR, PMIC_RG_OCTL_XOSC_EN_MASK,
	 PMIC_RG_OCTL_XOSC_EN_SHIFT},
	{PMIC_RG_OCTL_VOW_CLK_MISO, PMIC_RG_OCTL_VOW_CLK_MISO_ADDR,
	 PMIC_RG_OCTL_VOW_CLK_MISO_MASK, PMIC_RG_OCTL_VOW_CLK_MISO_SHIFT},
	{PMIC_TOP_STATUS, PMIC_TOP_STATUS_ADDR, PMIC_TOP_STATUS_MASK,
	 PMIC_TOP_STATUS_SHIFT},
	{PMIC_TOP_STATUS_SET, PMIC_TOP_STATUS_SET_ADDR, PMIC_TOP_STATUS_SET_MASK,
	 PMIC_TOP_STATUS_SET_SHIFT},
	{PMIC_TOP_STATUS_CLR, PMIC_TOP_STATUS_CLR_ADDR, PMIC_TOP_STATUS_CLR_MASK,
	 PMIC_TOP_STATUS_CLR_SHIFT},
	{PMIC_CLK_RSV_CON0_RSV, PMIC_CLK_RSV_CON0_RSV_ADDR,
	 PMIC_CLK_RSV_CON0_RSV_MASK, PMIC_CLK_RSV_CON0_RSV_SHIFT},
	{PMIC_RG_DCXO_PWRKEY_RSTB_SEL, PMIC_RG_DCXO_PWRKEY_RSTB_SEL_ADDR,
	 PMIC_RG_DCXO_PWRKEY_RSTB_SEL_MASK, PMIC_RG_DCXO_PWRKEY_RSTB_SEL_SHIFT},
	{PMIC_CLK_SRCVOLTEN_SW, PMIC_CLK_SRCVOLTEN_SW_ADDR,
	 PMIC_CLK_SRCVOLTEN_SW_MASK, PMIC_CLK_SRCVOLTEN_SW_SHIFT},
	{PMIC_CLK_BUCK_OSC_SEL_SW, PMIC_CLK_BUCK_OSC_SEL_SW_ADDR,
	 PMIC_CLK_BUCK_OSC_SEL_SW_MASK, PMIC_CLK_BUCK_OSC_SEL_SW_SHIFT},
	{PMIC_CLK_VOWEN_SW, PMIC_CLK_VOWEN_SW_ADDR, PMIC_CLK_VOWEN_SW_MASK,
	 PMIC_CLK_VOWEN_SW_SHIFT},
	{PMIC_CLK_SRCVOLTEN_MODE, PMIC_CLK_SRCVOLTEN_MODE_ADDR,
	 PMIC_CLK_SRCVOLTEN_MODE_MASK, PMIC_CLK_SRCVOLTEN_MODE_SHIFT},
	{PMIC_CLK_BUCK_OSC_SEL_MODE, PMIC_CLK_BUCK_OSC_SEL_MODE_ADDR,
	 PMIC_CLK_BUCK_OSC_SEL_MODE_MASK, PMIC_CLK_BUCK_OSC_SEL_MODE_SHIFT},
	{PMIC_CLK_VOWEN_MODE, PMIC_CLK_VOWEN_MODE_ADDR, PMIC_CLK_VOWEN_MODE_MASK,
	 PMIC_CLK_VOWEN_MODE_SHIFT},
	{PMIC_RG_TOP_CKSEL_CON2_RSV, PMIC_RG_TOP_CKSEL_CON2_RSV_ADDR,
	 PMIC_RG_TOP_CKSEL_CON2_RSV_MASK, PMIC_RG_TOP_CKSEL_CON2_RSV_SHIFT},
	{PMIC_CLK_BUCK_CON0_RSV, PMIC_CLK_BUCK_CON0_RSV_ADDR,
	 PMIC_CLK_BUCK_CON0_RSV_MASK, PMIC_CLK_BUCK_CON0_RSV_SHIFT},
	{PMIC_CLK_BUCK_CON0_SET, PMIC_CLK_BUCK_CON0_SET_ADDR,
	 PMIC_CLK_BUCK_CON0_SET_MASK, PMIC_CLK_BUCK_CON0_SET_SHIFT},
	{PMIC_CLK_BUCK_CON0_CLR, PMIC_CLK_BUCK_CON0_CLR_ADDR,
	 PMIC_CLK_BUCK_CON0_CLR_MASK, PMIC_CLK_BUCK_CON0_CLR_SHIFT},
	{PMIC_CLK_BUCK_VCORE_OSC_SEL_SW, PMIC_CLK_BUCK_VCORE_OSC_SEL_SW_ADDR,
	 PMIC_CLK_BUCK_VCORE_OSC_SEL_SW_MASK, PMIC_CLK_BUCK_VCORE_OSC_SEL_SW_SHIFT},
	{PMIC_CLK_BUCK_VCORE2_OSC_SEL_SW, PMIC_CLK_BUCK_VCORE2_OSC_SEL_SW_ADDR,
	 PMIC_CLK_BUCK_VCORE2_OSC_SEL_SW_MASK, PMIC_CLK_BUCK_VCORE2_OSC_SEL_SW_SHIFT},
	{PMIC_CLK_BUCK_VPROC_OSC_SEL_SW, PMIC_CLK_BUCK_VPROC_OSC_SEL_SW_ADDR,
	 PMIC_CLK_BUCK_VPROC_OSC_SEL_SW_MASK, PMIC_CLK_BUCK_VPROC_OSC_SEL_SW_SHIFT},
	{PMIC_CLK_BUCK_VPA_OSC_SEL_SW, PMIC_CLK_BUCK_VPA_OSC_SEL_SW_ADDR,
	 PMIC_CLK_BUCK_VPA_OSC_SEL_SW_MASK, PMIC_CLK_BUCK_VPA_OSC_SEL_SW_SHIFT},
	{PMIC_CLK_BUCK_VS1_OSC_SEL_SW, PMIC_CLK_BUCK_VS1_OSC_SEL_SW_ADDR,
	 PMIC_CLK_BUCK_VS1_OSC_SEL_SW_MASK, PMIC_CLK_BUCK_VS1_OSC_SEL_SW_SHIFT},
	{PMIC_CLK_LDO_VSRAM_PROC_OSC_SEL_SW, PMIC_CLK_LDO_VSRAM_PROC_OSC_SEL_SW_ADDR,
	 PMIC_CLK_LDO_VSRAM_PROC_OSC_SEL_SW_MASK,
	 PMIC_CLK_LDO_VSRAM_PROC_OSC_SEL_SW_SHIFT},
	{PMIC_CLK_BUCK_VCORE_OSC_SEL_MODE, PMIC_CLK_BUCK_VCORE_OSC_SEL_MODE_ADDR,
	 PMIC_CLK_BUCK_VCORE_OSC_SEL_MODE_MASK,
	 PMIC_CLK_BUCK_VCORE_OSC_SEL_MODE_SHIFT},
	{PMIC_CLK_BUCK_VCORE2_OSC_SEL_MODE, PMIC_CLK_BUCK_VCORE2_OSC_SEL_MODE_ADDR,
	 PMIC_CLK_BUCK_VCORE2_OSC_SEL_MODE_MASK,
	 PMIC_CLK_BUCK_VCORE2_OSC_SEL_MODE_SHIFT},
	{PMIC_CLK_BUCK_VPROC_OSC_SEL_MODE, PMIC_CLK_BUCK_VPROC_OSC_SEL_MODE_ADDR,
	 PMIC_CLK_BUCK_VPROC_OSC_SEL_MODE_MASK,
	 PMIC_CLK_BUCK_VPROC_OSC_SEL_MODE_SHIFT},
	{PMIC_CLK_BUCK_VPA_OSC_SEL_MODE, PMIC_CLK_BUCK_VPA_OSC_SEL_MODE_ADDR,
	 PMIC_CLK_BUCK_VPA_OSC_SEL_MODE_MASK, PMIC_CLK_BUCK_VPA_OSC_SEL_MODE_SHIFT},
	{PMIC_CLK_BUCK_VS1_OSC_SEL_MODE, PMIC_CLK_BUCK_VS1_OSC_SEL_MODE_ADDR,
	 PMIC_CLK_BUCK_VS1_OSC_SEL_MODE_MASK, PMIC_CLK_BUCK_VS1_OSC_SEL_MODE_SHIFT},
	{PMIC_CLK_LDO_VSRAM_PROC_OSC_SEL_MODE, PMIC_CLK_LDO_VSRAM_PROC_OSC_SEL_MODE_ADDR,
	 PMIC_CLK_LDO_VSRAM_PROC_OSC_SEL_MODE_MASK,
	 PMIC_CLK_LDO_VSRAM_PROC_OSC_SEL_MODE_SHIFT},
	{PMIC_CLK_BUCK_CON1_RSV, PMIC_CLK_BUCK_CON1_RSV_ADDR,
	 PMIC_CLK_BUCK_CON1_RSV_MASK, PMIC_CLK_BUCK_CON1_RSV_SHIFT},
	{PMIC_CLK_BUCK_CON1_SET, PMIC_CLK_BUCK_CON1_SET_ADDR,
	 PMIC_CLK_BUCK_CON1_SET_MASK, PMIC_CLK_BUCK_CON1_SET_SHIFT},
	{PMIC_CLK_BUCK_CON1_CLR, PMIC_CLK_BUCK_CON1_CLR_ADDR,
	 PMIC_CLK_BUCK_CON1_CLR_MASK, PMIC_CLK_BUCK_CON1_CLR_SHIFT},
	{PMIC_RG_CLKSQ_EN_AUD, PMIC_RG_CLKSQ_EN_AUD_ADDR, PMIC_RG_CLKSQ_EN_AUD_MASK,
	 PMIC_RG_CLKSQ_EN_AUD_SHIFT},
	{PMIC_RG_CLKSQ_EN_FQR, PMIC_RG_CLKSQ_EN_FQR_ADDR, PMIC_RG_CLKSQ_EN_FQR_MASK,
	 PMIC_RG_CLKSQ_EN_FQR_SHIFT},
	{PMIC_RG_CLKSQ_EN_AUX_AP, PMIC_RG_CLKSQ_EN_AUX_AP_ADDR,
	 PMIC_RG_CLKSQ_EN_AUX_AP_MASK, PMIC_RG_CLKSQ_EN_AUX_AP_SHIFT},
	{PMIC_RG_CLKSQ_EN_AUX_MD, PMIC_RG_CLKSQ_EN_AUX_MD_ADDR,
	 PMIC_RG_CLKSQ_EN_AUX_MD_MASK, PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT},
	{PMIC_RG_CLKSQ_EN_AUX_GPS, PMIC_RG_CLKSQ_EN_AUX_GPS_ADDR,
	 PMIC_RG_CLKSQ_EN_AUX_GPS_MASK, PMIC_RG_CLKSQ_EN_AUX_GPS_SHIFT},
	{PMIC_RG_CLKSQ_EN_AUX_RSV, PMIC_RG_CLKSQ_EN_AUX_RSV_ADDR,
	 PMIC_RG_CLKSQ_EN_AUX_RSV_MASK, PMIC_RG_CLKSQ_EN_AUX_RSV_SHIFT},
	{PMIC_RG_CLKSQ_EN_AUX_AP_MODE, PMIC_RG_CLKSQ_EN_AUX_AP_MODE_ADDR,
	 PMIC_RG_CLKSQ_EN_AUX_AP_MODE_MASK, PMIC_RG_CLKSQ_EN_AUX_AP_MODE_SHIFT},
	{PMIC_RG_CLKSQ_EN_AUX_MD_MODE, PMIC_RG_CLKSQ_EN_AUX_MD_MODE_ADDR,
	 PMIC_RG_CLKSQ_EN_AUX_MD_MODE_MASK, PMIC_RG_CLKSQ_EN_AUX_MD_MODE_SHIFT},
	{PMIC_RG_CLKSQ_IN_SEL_VA18, PMIC_RG_CLKSQ_IN_SEL_VA18_ADDR,
	 PMIC_RG_CLKSQ_IN_SEL_VA18_MASK, PMIC_RG_CLKSQ_IN_SEL_VA18_SHIFT},
	{PMIC_RG_CLKSQ_IN_SEL_VA18_SWCTRL, PMIC_RG_CLKSQ_IN_SEL_VA18_SWCTRL_ADDR,
	 PMIC_RG_CLKSQ_IN_SEL_VA18_SWCTRL_MASK,
	 PMIC_RG_CLKSQ_IN_SEL_VA18_SWCTRL_SHIFT},
	{PMIC_TOP_CLKSQ_RSV, PMIC_TOP_CLKSQ_RSV_ADDR, PMIC_TOP_CLKSQ_RSV_MASK,
	 PMIC_TOP_CLKSQ_RSV_SHIFT},
	{PMIC_DA_CLKSQ_EN_VA28, PMIC_DA_CLKSQ_EN_VA28_ADDR,
	 PMIC_DA_CLKSQ_EN_VA28_MASK, PMIC_DA_CLKSQ_EN_VA28_SHIFT},
	{PMIC_TOP_CLKSQ_SET, PMIC_TOP_CLKSQ_SET_ADDR, PMIC_TOP_CLKSQ_SET_MASK,
	 PMIC_TOP_CLKSQ_SET_SHIFT},
	{PMIC_TOP_CLKSQ_CLR, PMIC_TOP_CLKSQ_CLR_ADDR, PMIC_TOP_CLKSQ_CLR_MASK,
	 PMIC_TOP_CLKSQ_CLR_SHIFT},
	{PMIC_RG_CLKSQ_RTC_EN, PMIC_RG_CLKSQ_RTC_EN_ADDR, PMIC_RG_CLKSQ_RTC_EN_MASK,
	 PMIC_RG_CLKSQ_RTC_EN_SHIFT},
	{PMIC_RG_CLKSQ_RTC_EN_HW_MODE, PMIC_RG_CLKSQ_RTC_EN_HW_MODE_ADDR,
	 PMIC_RG_CLKSQ_RTC_EN_HW_MODE_MASK, PMIC_RG_CLKSQ_RTC_EN_HW_MODE_SHIFT},
	{PMIC_TOP_CLKSQ_RTC_RSV0, PMIC_TOP_CLKSQ_RTC_RSV0_ADDR,
	 PMIC_TOP_CLKSQ_RTC_RSV0_MASK, PMIC_TOP_CLKSQ_RTC_RSV0_SHIFT},
	{PMIC_RG_ENBB_SEL, PMIC_RG_ENBB_SEL_ADDR, PMIC_RG_ENBB_SEL_MASK,
	 PMIC_RG_ENBB_SEL_SHIFT},
	{PMIC_RG_XOSC_EN_SEL, PMIC_RG_XOSC_EN_SEL_ADDR, PMIC_RG_XOSC_EN_SEL_MASK,
	 PMIC_RG_XOSC_EN_SEL_SHIFT},
	{PMIC_TOP_CLKSQ_RTC_RSV1, PMIC_TOP_CLKSQ_RTC_RSV1_ADDR,
	 PMIC_TOP_CLKSQ_RTC_RSV1_MASK, PMIC_TOP_CLKSQ_RTC_RSV1_SHIFT},
	{PMIC_DA_CLKSQ_EN_VDIG18, PMIC_DA_CLKSQ_EN_VDIG18_ADDR,
	 PMIC_DA_CLKSQ_EN_VDIG18_MASK, PMIC_DA_CLKSQ_EN_VDIG18_SHIFT},
	{PMIC_TOP_CLKSQ_RTC_SET, PMIC_TOP_CLKSQ_RTC_SET_ADDR,
	 PMIC_TOP_CLKSQ_RTC_SET_MASK, PMIC_TOP_CLKSQ_RTC_SET_SHIFT},
	{PMIC_TOP_CLKSQ_RTC_CLR, PMIC_TOP_CLKSQ_RTC_CLR_ADDR,
	 PMIC_TOP_CLKSQ_RTC_CLR_MASK, PMIC_TOP_CLKSQ_RTC_CLR_SHIFT},
	{PMIC_OSC_75K_TRIM, PMIC_OSC_75K_TRIM_ADDR, PMIC_OSC_75K_TRIM_MASK,
	 PMIC_OSC_75K_TRIM_SHIFT},
	{PMIC_RG_OSC_75K_TRIM_EN, PMIC_RG_OSC_75K_TRIM_EN_ADDR,
	 PMIC_RG_OSC_75K_TRIM_EN_MASK, PMIC_RG_OSC_75K_TRIM_EN_SHIFT},
	{PMIC_RG_OSC_75K_TRIM_RATE, PMIC_RG_OSC_75K_TRIM_RATE_ADDR,
	 PMIC_RG_OSC_75K_TRIM_RATE_MASK, PMIC_RG_OSC_75K_TRIM_RATE_SHIFT},
	{PMIC_DA_OSC_75K_TRIM, PMIC_DA_OSC_75K_TRIM_ADDR, PMIC_DA_OSC_75K_TRIM_MASK,
	 PMIC_DA_OSC_75K_TRIM_SHIFT},
	{PMIC_CLK_PMU75K_CK_TST_DIS, PMIC_CLK_PMU75K_CK_TST_DIS_ADDR,
	 PMIC_CLK_PMU75K_CK_TST_DIS_MASK, PMIC_CLK_PMU75K_CK_TST_DIS_SHIFT},
	{PMIC_CLK_SMPS_CK_TST_DIS, PMIC_CLK_SMPS_CK_TST_DIS_ADDR,
	 PMIC_CLK_SMPS_CK_TST_DIS_MASK, PMIC_CLK_SMPS_CK_TST_DIS_SHIFT},
	{PMIC_CLK_AUD26M_CK_TST_DIS, PMIC_CLK_AUD26M_CK_TST_DIS_ADDR,
	 PMIC_CLK_AUD26M_CK_TST_DIS_MASK, PMIC_CLK_AUD26M_CK_TST_DIS_SHIFT},
	{PMIC_CLK_VOW12M_CK_TST_DIS, PMIC_CLK_VOW12M_CK_TST_DIS_ADDR,
	 PMIC_CLK_VOW12M_CK_TST_DIS_MASK, PMIC_CLK_VOW12M_CK_TST_DIS_SHIFT},
	{PMIC_CLK_RTC32K_CK_TST_DIS, PMIC_CLK_RTC32K_CK_TST_DIS_ADDR,
	 PMIC_CLK_RTC32K_CK_TST_DIS_MASK, PMIC_CLK_RTC32K_CK_TST_DIS_SHIFT},
	{PMIC_CLK_RTC26M_CK_TST_DIS, PMIC_CLK_RTC26M_CK_TST_DIS_ADDR,
	 PMIC_CLK_RTC26M_CK_TST_DIS_MASK, PMIC_CLK_RTC26M_CK_TST_DIS_SHIFT},
	{PMIC_CLK_FG_CK_TST_DIS, PMIC_CLK_FG_CK_TST_DIS_ADDR,
	 PMIC_CLK_FG_CK_TST_DIS_MASK, PMIC_CLK_FG_CK_TST_DIS_SHIFT},
	{PMIC_CLK_SPK_CK_TST_DIS, PMIC_CLK_SPK_CK_TST_DIS_ADDR,
	 PMIC_CLK_SPK_CK_TST_DIS_MASK, PMIC_CLK_SPK_CK_TST_DIS_SHIFT},
	{PMIC_CLK_CKROOTTST_CON0_RSV, PMIC_CLK_CKROOTTST_CON0_RSV_ADDR,
	 PMIC_CLK_CKROOTTST_CON0_RSV_MASK, PMIC_CLK_CKROOTTST_CON0_RSV_SHIFT},
	{PMIC_CLK_BUCK_ANA_AUTO_OFF_DIS, PMIC_CLK_BUCK_ANA_AUTO_OFF_DIS_ADDR,
	 PMIC_CLK_BUCK_ANA_AUTO_OFF_DIS_MASK, PMIC_CLK_BUCK_ANA_AUTO_OFF_DIS_SHIFT},
	{PMIC_CLK_PMU75K_CK_TSTSEL, PMIC_CLK_PMU75K_CK_TSTSEL_ADDR,
	 PMIC_CLK_PMU75K_CK_TSTSEL_MASK, PMIC_CLK_PMU75K_CK_TSTSEL_SHIFT},
	{PMIC_CLK_SMPS_CK_TSTSEL, PMIC_CLK_SMPS_CK_TSTSEL_ADDR,
	 PMIC_CLK_SMPS_CK_TSTSEL_MASK, PMIC_CLK_SMPS_CK_TSTSEL_SHIFT},
	{PMIC_CLK_AUD26M_CK_TSTSEL, PMIC_CLK_AUD26M_CK_TSTSEL_ADDR,
	 PMIC_CLK_AUD26M_CK_TSTSEL_MASK, PMIC_CLK_AUD26M_CK_TSTSEL_SHIFT},
	{PMIC_CLK_VOW12M_CK_TSTSEL, PMIC_CLK_VOW12M_CK_TSTSEL_ADDR,
	 PMIC_CLK_VOW12M_CK_TSTSEL_MASK, PMIC_CLK_VOW12M_CK_TSTSEL_SHIFT},
	{PMIC_CLK_RTC32K_CK_TSTSEL, PMIC_CLK_RTC32K_CK_TSTSEL_ADDR,
	 PMIC_CLK_RTC32K_CK_TSTSEL_MASK, PMIC_CLK_RTC32K_CK_TSTSEL_SHIFT},
	{PMIC_CLK_RTC26M_CK_TSTSEL, PMIC_CLK_RTC26M_CK_TSTSEL_ADDR,
	 PMIC_CLK_RTC26M_CK_TSTSEL_MASK, PMIC_CLK_RTC26M_CK_TSTSEL_SHIFT},
	{PMIC_CLK_FG_CK_TSTSEL, PMIC_CLK_FG_CK_TSTSEL_ADDR,
	 PMIC_CLK_FG_CK_TSTSEL_MASK, PMIC_CLK_FG_CK_TSTSEL_SHIFT},
	{PMIC_CLK_SPK_CK_TSTSEL, PMIC_CLK_SPK_CK_TSTSEL_ADDR,
	 PMIC_CLK_SPK_CK_TSTSEL_MASK, PMIC_CLK_SPK_CK_TSTSEL_SHIFT},
	{PMIC_CLK_CKROOTTST_CON1_RSV, PMIC_CLK_CKROOTTST_CON1_RSV_ADDR,
	 PMIC_CLK_CKROOTTST_CON1_RSV_MASK, PMIC_CLK_CKROOTTST_CON1_RSV_SHIFT},
	{PMIC_CLK_RTC32K_1V8_0_O_PDN, PMIC_CLK_RTC32K_1V8_0_O_PDN_ADDR,
	 PMIC_CLK_RTC32K_1V8_0_O_PDN_MASK, PMIC_CLK_RTC32K_1V8_0_O_PDN_SHIFT},
	{PMIC_CLK_RTC32K_1V8_1_O_PDN, PMIC_CLK_RTC32K_1V8_1_O_PDN_ADDR,
	 PMIC_CLK_RTC32K_1V8_1_O_PDN_MASK, PMIC_CLK_RTC32K_1V8_1_O_PDN_SHIFT},
	{PMIC_CLK_RTC_2SEC_OFF_DET_PDN, PMIC_CLK_RTC_2SEC_OFF_DET_PDN_ADDR,
	 PMIC_CLK_RTC_2SEC_OFF_DET_PDN_MASK, PMIC_CLK_RTC_2SEC_OFF_DET_PDN_SHIFT},
	{PMIC_CLK_PDN_CON0_RSV, PMIC_CLK_PDN_CON0_RSV_ADDR,
	 PMIC_CLK_PDN_CON0_RSV_MASK, PMIC_CLK_PDN_CON0_RSV_SHIFT},
	{PMIC_CLK_PDN_CON0_SET, PMIC_CLK_PDN_CON0_SET_ADDR,
	 PMIC_CLK_PDN_CON0_SET_MASK, PMIC_CLK_PDN_CON0_SET_SHIFT},
	{PMIC_CLK_PDN_CON0_CLR, PMIC_CLK_PDN_CON0_CLR_ADDR,
	 PMIC_CLK_PDN_CON0_CLR_MASK, PMIC_CLK_PDN_CON0_CLR_SHIFT},
	{PMIC_CLK_ZCD13M_CK_PDN, PMIC_CLK_ZCD13M_CK_PDN_ADDR,
	 PMIC_CLK_ZCD13M_CK_PDN_MASK, PMIC_CLK_ZCD13M_CK_PDN_SHIFT},
	{PMIC_CLK_SMPS_CK_DIV_PDN, PMIC_CLK_SMPS_CK_DIV_PDN_ADDR,
	 PMIC_CLK_SMPS_CK_DIV_PDN_MASK, PMIC_CLK_SMPS_CK_DIV_PDN_SHIFT},
	{PMIC_CLK_BUCK_ANA_CK_PDN, PMIC_CLK_BUCK_ANA_CK_PDN_ADDR,
	 PMIC_CLK_BUCK_ANA_CK_PDN_MASK, PMIC_CLK_BUCK_ANA_CK_PDN_SHIFT},
	{PMIC_CLK_PDN_CON1_RSV, PMIC_CLK_PDN_CON1_RSV_ADDR,
	 PMIC_CLK_PDN_CON1_RSV_MASK, PMIC_CLK_PDN_CON1_RSV_SHIFT},
	{PMIC_CLK_PDN_CON1_SET, PMIC_CLK_PDN_CON1_SET_ADDR,
	 PMIC_CLK_PDN_CON1_SET_MASK, PMIC_CLK_PDN_CON1_SET_SHIFT},
	{PMIC_CLK_PDN_CON1_CLR, PMIC_CLK_PDN_CON1_CLR_ADDR,
	 PMIC_CLK_PDN_CON1_CLR_MASK, PMIC_CLK_PDN_CON1_CLR_SHIFT},
	{PMIC_CLK_OSC_SEL_HW_SRC_SEL, PMIC_CLK_OSC_SEL_HW_SRC_SEL_ADDR,
	 PMIC_CLK_OSC_SEL_HW_SRC_SEL_MASK, PMIC_CLK_OSC_SEL_HW_SRC_SEL_SHIFT},
	{PMIC_CLK_SRCLKEN_SRC_SEL, PMIC_CLK_SRCLKEN_SRC_SEL_ADDR,
	 PMIC_CLK_SRCLKEN_SRC_SEL_MASK, PMIC_CLK_SRCLKEN_SRC_SEL_SHIFT},
	{PMIC_CLK_SEL_CON0_RSV, PMIC_CLK_SEL_CON0_RSV_ADDR,
	 PMIC_CLK_SEL_CON0_RSV_MASK, PMIC_CLK_SEL_CON0_RSV_SHIFT},
	{PMIC_CLK_SEL_CON0_SET, PMIC_CLK_SEL_CON0_SET_ADDR,
	 PMIC_CLK_SEL_CON0_SET_MASK, PMIC_CLK_SEL_CON0_SET_SHIFT},
	{PMIC_CLK_SEL_CON0_CLR, PMIC_CLK_SEL_CON0_CLR_ADDR,
	 PMIC_CLK_SEL_CON0_CLR_MASK, PMIC_CLK_SEL_CON0_CLR_SHIFT},
	{PMIC_CLK_AUXADC_CK_CKSEL_HWEN, PMIC_CLK_AUXADC_CK_CKSEL_HWEN_ADDR,
	 PMIC_CLK_AUXADC_CK_CKSEL_HWEN_MASK, PMIC_CLK_AUXADC_CK_CKSEL_HWEN_SHIFT},
	{PMIC_CLK_AUXADC_CK_CKSEL, PMIC_CLK_AUXADC_CK_CKSEL_ADDR,
	 PMIC_CLK_AUXADC_CK_CKSEL_MASK, PMIC_CLK_AUXADC_CK_CKSEL_SHIFT},
	{PMIC_CLK_75K_32K_SEL, PMIC_CLK_75K_32K_SEL_ADDR, PMIC_CLK_75K_32K_SEL_MASK,
	 PMIC_CLK_75K_32K_SEL_SHIFT},
	{PMIC_CLK_SEL_CON1_RSV, PMIC_CLK_SEL_CON1_RSV_ADDR,
	 PMIC_CLK_SEL_CON1_RSV_MASK, PMIC_CLK_SEL_CON1_RSV_SHIFT},
	{PMIC_CLK_SEL_CON1_SET, PMIC_CLK_SEL_CON1_SET_ADDR,
	 PMIC_CLK_SEL_CON1_SET_MASK, PMIC_CLK_SEL_CON1_SET_SHIFT},
	{PMIC_CLK_SEL_CON1_CLR, PMIC_CLK_SEL_CON1_CLR_ADDR,
	 PMIC_CLK_SEL_CON1_CLR_MASK, PMIC_CLK_SEL_CON1_CLR_SHIFT},
	{PMIC_CLK_G_SMPS_PD_CK_PDN, PMIC_CLK_G_SMPS_PD_CK_PDN_ADDR,
	 PMIC_CLK_G_SMPS_PD_CK_PDN_MASK, PMIC_CLK_G_SMPS_PD_CK_PDN_SHIFT},
	{PMIC_CLK_G_SMPS_AUD_CK_PDN, PMIC_CLK_G_SMPS_AUD_CK_PDN_ADDR,
	 PMIC_CLK_G_SMPS_AUD_CK_PDN_MASK, PMIC_CLK_G_SMPS_AUD_CK_PDN_SHIFT},
	{PMIC_CLK_G_SMPS_TEST_CK_PDN, PMIC_CLK_G_SMPS_TEST_CK_PDN_ADDR,
	 PMIC_CLK_G_SMPS_TEST_CK_PDN_MASK, PMIC_CLK_G_SMPS_TEST_CK_PDN_SHIFT},
	{PMIC_CLK_ACCDET_CK_PDN, PMIC_CLK_ACCDET_CK_PDN_ADDR,
	 PMIC_CLK_ACCDET_CK_PDN_MASK, PMIC_CLK_ACCDET_CK_PDN_SHIFT},
	{PMIC_CLK_AUDIF_CK_PDN, PMIC_CLK_AUDIF_CK_PDN_ADDR,
	 PMIC_CLK_AUDIF_CK_PDN_MASK, PMIC_CLK_AUDIF_CK_PDN_SHIFT},
	{PMIC_CLK_AUD_CK_PDN, PMIC_CLK_AUD_CK_PDN_ADDR, PMIC_CLK_AUD_CK_PDN_MASK,
	 PMIC_CLK_AUD_CK_PDN_SHIFT},
	{PMIC_CLK_AUDNCP_CK_PDN, PMIC_CLK_AUDNCP_CK_PDN_ADDR,
	 PMIC_CLK_AUDNCP_CK_PDN_MASK, PMIC_CLK_AUDNCP_CK_PDN_SHIFT},
	{PMIC_CLK_AUXADC_1M_CK_PDN, PMIC_CLK_AUXADC_1M_CK_PDN_ADDR,
	 PMIC_CLK_AUXADC_1M_CK_PDN_MASK, PMIC_CLK_AUXADC_1M_CK_PDN_SHIFT},
	{PMIC_CLK_AUXADC_SMPS_CK_PDN, PMIC_CLK_AUXADC_SMPS_CK_PDN_ADDR,
	 PMIC_CLK_AUXADC_SMPS_CK_PDN_MASK, PMIC_CLK_AUXADC_SMPS_CK_PDN_SHIFT},
	{PMIC_CLK_AUXADC_RNG_CK_PDN, PMIC_CLK_AUXADC_RNG_CK_PDN_ADDR,
	 PMIC_CLK_AUXADC_RNG_CK_PDN_MASK, PMIC_CLK_AUXADC_RNG_CK_PDN_SHIFT},
	{PMIC_CLK_AUXADC_26M_CK_PDN, PMIC_CLK_AUXADC_26M_CK_PDN_ADDR,
	 PMIC_CLK_AUXADC_26M_CK_PDN_MASK, PMIC_CLK_AUXADC_26M_CK_PDN_SHIFT},
	{PMIC_CLK_AUXADC_CK_PDN, PMIC_CLK_AUXADC_CK_PDN_ADDR,
	 PMIC_CLK_AUXADC_CK_PDN_MASK, PMIC_CLK_AUXADC_CK_PDN_SHIFT},
	{PMIC_CLK_DRV_ISINK0_CK_PDN, PMIC_CLK_DRV_ISINK0_CK_PDN_ADDR,
	 PMIC_CLK_DRV_ISINK0_CK_PDN_MASK, PMIC_CLK_DRV_ISINK0_CK_PDN_SHIFT},
	{PMIC_CLK_DRV_ISINK1_CK_PDN, PMIC_CLK_DRV_ISINK1_CK_PDN_ADDR,
	 PMIC_CLK_DRV_ISINK1_CK_PDN_MASK, PMIC_CLK_DRV_ISINK1_CK_PDN_SHIFT},
	{PMIC_CLK_DRV_ISINK2_CK_PDN, PMIC_CLK_DRV_ISINK2_CK_PDN_ADDR,
	 PMIC_CLK_DRV_ISINK2_CK_PDN_MASK, PMIC_CLK_DRV_ISINK2_CK_PDN_SHIFT},
	{PMIC_CLK_DRV_ISINK3_CK_PDN, PMIC_CLK_DRV_ISINK3_CK_PDN_ADDR,
	 PMIC_CLK_DRV_ISINK3_CK_PDN_MASK, PMIC_CLK_DRV_ISINK3_CK_PDN_SHIFT},
	{PMIC_CLK_CKPDN_CON0_SET, PMIC_CLK_CKPDN_CON0_SET_ADDR,
	 PMIC_CLK_CKPDN_CON0_SET_MASK, PMIC_CLK_CKPDN_CON0_SET_SHIFT},
	{PMIC_CLK_CKPDN_CON0_CLR, PMIC_CLK_CKPDN_CON0_CLR_ADDR,
	 PMIC_CLK_CKPDN_CON0_CLR_MASK, PMIC_CLK_CKPDN_CON0_CLR_SHIFT},
	{PMIC_CLK_DRV_CHRIND_CK_PDN, PMIC_CLK_DRV_CHRIND_CK_PDN_ADDR,
	 PMIC_CLK_DRV_CHRIND_CK_PDN_MASK, PMIC_CLK_DRV_CHRIND_CK_PDN_SHIFT},
	{PMIC_CLK_DRV_32K_CK_PDN, PMIC_CLK_DRV_32K_CK_PDN_ADDR,
	 PMIC_CLK_DRV_32K_CK_PDN_MASK, PMIC_CLK_DRV_32K_CK_PDN_SHIFT},
	{PMIC_CLK_BUCK_1M_CK_PDN, PMIC_CLK_BUCK_1M_CK_PDN_ADDR,
	 PMIC_CLK_BUCK_1M_CK_PDN_MASK, PMIC_CLK_BUCK_1M_CK_PDN_SHIFT},
	{PMIC_CLK_BUCK_32K_CK_PDN, PMIC_CLK_BUCK_32K_CK_PDN_ADDR,
	 PMIC_CLK_BUCK_32K_CK_PDN_MASK, PMIC_CLK_BUCK_32K_CK_PDN_SHIFT},
	{PMIC_CLK_BUCK_9M_CK_PDN, PMIC_CLK_BUCK_9M_CK_PDN_ADDR,
	 PMIC_CLK_BUCK_9M_CK_PDN_MASK, PMIC_CLK_BUCK_9M_CK_PDN_SHIFT},
	{PMIC_CLK_PWMOC_6M_CK_PDN, PMIC_CLK_PWMOC_6M_CK_PDN_ADDR,
	 PMIC_CLK_PWMOC_6M_CK_PDN_MASK, PMIC_CLK_PWMOC_6M_CK_PDN_SHIFT},
	{PMIC_CLK_BUCK_VPROC_9M_CK_PDN, PMIC_CLK_BUCK_VPROC_9M_CK_PDN_ADDR,
	 PMIC_CLK_BUCK_VPROC_9M_CK_PDN_MASK, PMIC_CLK_BUCK_VPROC_9M_CK_PDN_SHIFT},
	{PMIC_CLK_BUCK_VCORE_9M_CK_PDN, PMIC_CLK_BUCK_VCORE_9M_CK_PDN_ADDR,
	 PMIC_CLK_BUCK_VCORE_9M_CK_PDN_MASK, PMIC_CLK_BUCK_VCORE_9M_CK_PDN_SHIFT},
	{PMIC_CLK_BUCK_VCORE2_9M_CK_PDN, PMIC_CLK_BUCK_VCORE2_9M_CK_PDN_ADDR,
	 PMIC_CLK_BUCK_VCORE2_9M_CK_PDN_MASK, PMIC_CLK_BUCK_VCORE2_9M_CK_PDN_SHIFT},
	{PMIC_CLK_BUCK_VPA_9M_CK_PDN, PMIC_CLK_BUCK_VPA_9M_CK_PDN_ADDR,
	 PMIC_CLK_BUCK_VPA_9M_CK_PDN_MASK, PMIC_CLK_BUCK_VPA_9M_CK_PDN_SHIFT},
	{PMIC_CLK_BUCK_VS1_9M_CK_PDN, PMIC_CLK_BUCK_VS1_9M_CK_PDN_ADDR,
	 PMIC_CLK_BUCK_VS1_9M_CK_PDN_MASK, PMIC_CLK_BUCK_VS1_9M_CK_PDN_SHIFT},
	{PMIC_CLK_FQMTR_CK_PDN, PMIC_CLK_FQMTR_CK_PDN_ADDR,
	 PMIC_CLK_FQMTR_CK_PDN_MASK, PMIC_CLK_FQMTR_CK_PDN_SHIFT},
	{PMIC_CLK_FQMTR_32K_CK_PDN, PMIC_CLK_FQMTR_32K_CK_PDN_ADDR,
	 PMIC_CLK_FQMTR_32K_CK_PDN_MASK, PMIC_CLK_FQMTR_32K_CK_PDN_SHIFT},
	{PMIC_CLK_INTRP_CK_PDN, PMIC_CLK_INTRP_CK_PDN_ADDR,
	 PMIC_CLK_INTRP_CK_PDN_MASK, PMIC_CLK_INTRP_CK_PDN_SHIFT},
	{PMIC_CLK_INTRP_PRE_OC_CK_PDN, PMIC_CLK_INTRP_PRE_OC_CK_PDN_ADDR,
	 PMIC_CLK_INTRP_PRE_OC_CK_PDN_MASK, PMIC_CLK_INTRP_PRE_OC_CK_PDN_SHIFT},
	{PMIC_CLK_STB_1M_CK_PDN, PMIC_CLK_STB_1M_CK_PDN_ADDR,
	 PMIC_CLK_STB_1M_CK_PDN_MASK, PMIC_CLK_STB_1M_CK_PDN_SHIFT},
	{PMIC_CLK_CKPDN_CON1_SET, PMIC_CLK_CKPDN_CON1_SET_ADDR,
	 PMIC_CLK_CKPDN_CON1_SET_MASK, PMIC_CLK_CKPDN_CON1_SET_SHIFT},
	{PMIC_CLK_CKPDN_CON1_CLR, PMIC_CLK_CKPDN_CON1_CLR_ADDR,
	 PMIC_CLK_CKPDN_CON1_CLR_MASK, PMIC_CLK_CKPDN_CON1_CLR_SHIFT},
	{PMIC_CLK_LDO_CALI_75K_CK_PDN, PMIC_CLK_LDO_CALI_75K_CK_PDN_ADDR,
	 PMIC_CLK_LDO_CALI_75K_CK_PDN_MASK, PMIC_CLK_LDO_CALI_75K_CK_PDN_SHIFT},
	{PMIC_CLK_LDO_VSRAM_PROC_9M_CK_PDN, PMIC_CLK_LDO_VSRAM_PROC_9M_CK_PDN_ADDR,
	 PMIC_CLK_LDO_VSRAM_PROC_9M_CK_PDN_MASK,
	 PMIC_CLK_LDO_VSRAM_PROC_9M_CK_PDN_SHIFT},
	{PMIC_CLK_RTC_26M_CK_PDN, PMIC_CLK_RTC_26M_CK_PDN_ADDR,
	 PMIC_CLK_RTC_26M_CK_PDN_MASK, PMIC_CLK_RTC_26M_CK_PDN_SHIFT},
	{PMIC_CLK_RTC_32K_CK_PDN, PMIC_CLK_RTC_32K_CK_PDN_ADDR,
	 PMIC_CLK_RTC_32K_CK_PDN_MASK, PMIC_CLK_RTC_32K_CK_PDN_SHIFT},
	{PMIC_CLK_RTC_MCLK_PDN, PMIC_CLK_RTC_MCLK_PDN_ADDR,
	 PMIC_CLK_RTC_MCLK_PDN_MASK, PMIC_CLK_RTC_MCLK_PDN_SHIFT},
	{PMIC_CLK_RTC_75K_CK_PDN, PMIC_CLK_RTC_75K_CK_PDN_ADDR,
	 PMIC_CLK_RTC_75K_CK_PDN_MASK, PMIC_CLK_RTC_75K_CK_PDN_SHIFT},
	{PMIC_CLK_RTCDET_CK_PDN, PMIC_CLK_RTCDET_CK_PDN_ADDR,
	 PMIC_CLK_RTCDET_CK_PDN_MASK, PMIC_CLK_RTCDET_CK_PDN_SHIFT},
	{PMIC_CLK_RTC_EOSC32_CK_PDN, PMIC_CLK_RTC_EOSC32_CK_PDN_ADDR,
	 PMIC_CLK_RTC_EOSC32_CK_PDN_MASK, PMIC_CLK_RTC_EOSC32_CK_PDN_SHIFT},
	{PMIC_CLK_EOSC_CALI_TEST_CK_PDN, PMIC_CLK_EOSC_CALI_TEST_CK_PDN_ADDR,
	 PMIC_CLK_EOSC_CALI_TEST_CK_PDN_MASK, PMIC_CLK_EOSC_CALI_TEST_CK_PDN_SHIFT},
	{PMIC_CLK_FGADC_ANA_CK_PDN, PMIC_CLK_FGADC_ANA_CK_PDN_ADDR,
	 PMIC_CLK_FGADC_ANA_CK_PDN_MASK, PMIC_CLK_FGADC_ANA_CK_PDN_SHIFT},
	{PMIC_CLK_FGADC_DIG_CK_PDN, PMIC_CLK_FGADC_DIG_CK_PDN_ADDR,
	 PMIC_CLK_FGADC_DIG_CK_PDN_MASK, PMIC_CLK_FGADC_DIG_CK_PDN_SHIFT},
	{PMIC_CLK_FGADC_FT_CK_PDN, PMIC_CLK_FGADC_FT_CK_PDN_ADDR,
	 PMIC_CLK_FGADC_FT_CK_PDN_MASK, PMIC_CLK_FGADC_FT_CK_PDN_SHIFT},
	{PMIC_CLK_TRIM_75K_CK_PDN, PMIC_CLK_TRIM_75K_CK_PDN_ADDR,
	 PMIC_CLK_TRIM_75K_CK_PDN_MASK, PMIC_CLK_TRIM_75K_CK_PDN_SHIFT},
	{PMIC_CLK_EFUSE_CK_PDN, PMIC_CLK_EFUSE_CK_PDN_ADDR,
	 PMIC_CLK_EFUSE_CK_PDN_MASK, PMIC_CLK_EFUSE_CK_PDN_SHIFT},
	{PMIC_CLK_STRUP_75K_CK_PDN, PMIC_CLK_STRUP_75K_CK_PDN_ADDR,
	 PMIC_CLK_STRUP_75K_CK_PDN_MASK, PMIC_CLK_STRUP_75K_CK_PDN_SHIFT},
	{PMIC_CLK_STRUP_32K_CK_PDN, PMIC_CLK_STRUP_32K_CK_PDN_ADDR,
	 PMIC_CLK_STRUP_32K_CK_PDN_MASK, PMIC_CLK_STRUP_32K_CK_PDN_SHIFT},
	{PMIC_CLK_CKPDN_CON2_SET, PMIC_CLK_CKPDN_CON2_SET_ADDR,
	 PMIC_CLK_CKPDN_CON2_SET_MASK, PMIC_CLK_CKPDN_CON2_SET_SHIFT},
	{PMIC_CLK_CKPDN_CON2_CLR, PMIC_CLK_CKPDN_CON2_CLR_ADDR,
	 PMIC_CLK_CKPDN_CON2_CLR_MASK, PMIC_CLK_CKPDN_CON2_CLR_SHIFT},
	{PMIC_CLK_PCHR_32K_CK_PDN, PMIC_CLK_PCHR_32K_CK_PDN_ADDR,
	 PMIC_CLK_PCHR_32K_CK_PDN_MASK, PMIC_CLK_PCHR_32K_CK_PDN_SHIFT},
	{PMIC_CLK_PCHR_TEST_CK_PDN, PMIC_CLK_PCHR_TEST_CK_PDN_ADDR,
	 PMIC_CLK_PCHR_TEST_CK_PDN_MASK, PMIC_CLK_PCHR_TEST_CK_PDN_SHIFT},
	{PMIC_CLK_SPI_CK_PDN, PMIC_CLK_SPI_CK_PDN_ADDR, PMIC_CLK_SPI_CK_PDN_MASK,
	 PMIC_CLK_SPI_CK_PDN_SHIFT},
	{PMIC_CLK_BGR_TEST_CK_PDN, PMIC_CLK_BGR_TEST_CK_PDN_ADDR,
	 PMIC_CLK_BGR_TEST_CK_PDN_MASK, PMIC_CLK_BGR_TEST_CK_PDN_SHIFT},
	{PMIC_CLK_TYPE_C_CC_CK_PDN, PMIC_CLK_TYPE_C_CC_CK_PDN_ADDR,
	 PMIC_CLK_TYPE_C_CC_CK_PDN_MASK, PMIC_CLK_TYPE_C_CC_CK_PDN_SHIFT},
	{PMIC_CLK_TYPE_C_CSR_CK_PDN, PMIC_CLK_TYPE_C_CSR_CK_PDN_ADDR,
	 PMIC_CLK_TYPE_C_CSR_CK_PDN_MASK, PMIC_CLK_TYPE_C_CSR_CK_PDN_SHIFT},
	{PMIC_CLK_SPK_CK_PDN, PMIC_CLK_SPK_CK_PDN_ADDR, PMIC_CLK_SPK_CK_PDN_MASK,
	 PMIC_CLK_SPK_CK_PDN_SHIFT},
	{PMIC_CLK_SPK_PWM_CK_PDN, PMIC_CLK_SPK_PWM_CK_PDN_ADDR,
	 PMIC_CLK_SPK_PWM_CK_PDN_MASK, PMIC_CLK_SPK_PWM_CK_PDN_SHIFT},
	{PMIC_CLK_RSV_PDN, PMIC_CLK_RSV_PDN_ADDR, PMIC_CLK_RSV_PDN_MASK,
	 PMIC_CLK_RSV_PDN_SHIFT},
	{PMIC_CLK_CKPDN_CON3_SET, PMIC_CLK_CKPDN_CON3_SET_ADDR,
	 PMIC_CLK_CKPDN_CON3_SET_MASK, PMIC_CLK_CKPDN_CON3_SET_SHIFT},
	{PMIC_CLK_CKPDN_CON3_CLR, PMIC_CLK_CKPDN_CON3_CLR_ADDR,
	 PMIC_CLK_CKPDN_CON3_CLR_MASK, PMIC_CLK_CKPDN_CON3_CLR_SHIFT},
	{PMIC_CLK_G_SMPS_PD_CK_PDN_HWEN, PMIC_CLK_G_SMPS_PD_CK_PDN_HWEN_ADDR,
	 PMIC_CLK_G_SMPS_PD_CK_PDN_HWEN_MASK, PMIC_CLK_G_SMPS_PD_CK_PDN_HWEN_SHIFT},
	{PMIC_CLK_G_SMPS_AUD_CK_PDN_HWEN, PMIC_CLK_G_SMPS_AUD_CK_PDN_HWEN_ADDR,
	 PMIC_CLK_G_SMPS_AUD_CK_PDN_HWEN_MASK, PMIC_CLK_G_SMPS_AUD_CK_PDN_HWEN_SHIFT},
	{PMIC_CLK_AUXADC_SMPS_CK_PDN_HWEN, PMIC_CLK_AUXADC_SMPS_CK_PDN_HWEN_ADDR,
	 PMIC_CLK_AUXADC_SMPS_CK_PDN_HWEN_MASK,
	 PMIC_CLK_AUXADC_SMPS_CK_PDN_HWEN_SHIFT},
	{PMIC_CLK_AUXADC_26M_CK_PDN_HWEN, PMIC_CLK_AUXADC_26M_CK_PDN_HWEN_ADDR,
	 PMIC_CLK_AUXADC_26M_CK_PDN_HWEN_MASK, PMIC_CLK_AUXADC_26M_CK_PDN_HWEN_SHIFT},
	{PMIC_CLK_AUXADC_CK_PDN_HWEN, PMIC_CLK_AUXADC_CK_PDN_HWEN_ADDR,
	 PMIC_CLK_AUXADC_CK_PDN_HWEN_MASK, PMIC_CLK_AUXADC_CK_PDN_HWEN_SHIFT},
	{PMIC_CLK_BUCK_1M_CK_PDN_HWEN, PMIC_CLK_BUCK_1M_CK_PDN_HWEN_ADDR,
	 PMIC_CLK_BUCK_1M_CK_PDN_HWEN_MASK, PMIC_CLK_BUCK_1M_CK_PDN_HWEN_SHIFT},
	{PMIC_CLK_BUCK_VPROC_9M_CK_PDN_HWEN, PMIC_CLK_BUCK_VPROC_9M_CK_PDN_HWEN_ADDR,
	 PMIC_CLK_BUCK_VPROC_9M_CK_PDN_HWEN_MASK,
	 PMIC_CLK_BUCK_VPROC_9M_CK_PDN_HWEN_SHIFT},
	{PMIC_CLK_BUCK_VCORE_9M_CK_PDN_HWEN, PMIC_CLK_BUCK_VCORE_9M_CK_PDN_HWEN_ADDR,
	 PMIC_CLK_BUCK_VCORE_9M_CK_PDN_HWEN_MASK,
	 PMIC_CLK_BUCK_VCORE_9M_CK_PDN_HWEN_SHIFT},
	{PMIC_CLK_BUCK_VCORE2_9M_CK_PDN_HWEN, PMIC_CLK_BUCK_VCORE2_9M_CK_PDN_HWEN_ADDR,
	 PMIC_CLK_BUCK_VCORE2_9M_CK_PDN_HWEN_MASK,
	 PMIC_CLK_BUCK_VCORE2_9M_CK_PDN_HWEN_SHIFT},
	{PMIC_CLK_BUCK_VPA_9M_CK_PDN_HWEN, PMIC_CLK_BUCK_VPA_9M_CK_PDN_HWEN_ADDR,
	 PMIC_CLK_BUCK_VPA_9M_CK_PDN_HWEN_MASK,
	 PMIC_CLK_BUCK_VPA_9M_CK_PDN_HWEN_SHIFT},
	{PMIC_CLK_BUCK_VS1_9M_CK_PDN_HWEN, PMIC_CLK_BUCK_VS1_9M_CK_PDN_HWEN_ADDR,
	 PMIC_CLK_BUCK_VS1_9M_CK_PDN_HWEN_MASK,
	 PMIC_CLK_BUCK_VS1_9M_CK_PDN_HWEN_SHIFT},
	{PMIC_CLK_STB_1M_CK_PDN_HWEN, PMIC_CLK_STB_1M_CK_PDN_HWEN_ADDR,
	 PMIC_CLK_STB_1M_CK_PDN_HWEN_MASK, PMIC_CLK_STB_1M_CK_PDN_HWEN_SHIFT},
	{PMIC_CLK_LDO_VSRAM_PROC_9M_CK_PDN_HWEN, PMIC_CLK_LDO_VSRAM_PROC_9M_CK_PDN_HWEN_ADDR,
	 PMIC_CLK_LDO_VSRAM_PROC_9M_CK_PDN_HWEN_MASK,
	 PMIC_CLK_LDO_VSRAM_PROC_9M_CK_PDN_HWEN_SHIFT},
	{PMIC_CLK_RTC_26M_CK_PDN_HWEN, PMIC_CLK_RTC_26M_CK_PDN_HWEN_ADDR,
	 PMIC_CLK_RTC_26M_CK_PDN_HWEN_MASK, PMIC_CLK_RTC_26M_CK_PDN_HWEN_SHIFT},
	{PMIC_CLK_RSV_PDN_HWEN, PMIC_CLK_RSV_PDN_HWEN_ADDR,
	 PMIC_CLK_RSV_PDN_HWEN_MASK, PMIC_CLK_RSV_PDN_HWEN_SHIFT},
	{PMIC_CLK_CKPDN_HWEN_CON0_SET, PMIC_CLK_CKPDN_HWEN_CON0_SET_ADDR,
	 PMIC_CLK_CKPDN_HWEN_CON0_SET_MASK, PMIC_CLK_CKPDN_HWEN_CON0_SET_SHIFT},
	{PMIC_CLK_CKPDN_HWEN_CON0_CLR, PMIC_CLK_CKPDN_HWEN_CON0_CLR_ADDR,
	 PMIC_CLK_CKPDN_HWEN_CON0_CLR_MASK, PMIC_CLK_CKPDN_HWEN_CON0_CLR_SHIFT},
	{PMIC_CLK_AUDIF_CK_CKSEL, PMIC_CLK_AUDIF_CK_CKSEL_ADDR,
	 PMIC_CLK_AUDIF_CK_CKSEL_MASK, PMIC_CLK_AUDIF_CK_CKSEL_SHIFT},
	{PMIC_CLK_AUD_CK_CKSEL, PMIC_CLK_AUD_CK_CKSEL_ADDR,
	 PMIC_CLK_AUD_CK_CKSEL_MASK, PMIC_CLK_AUD_CK_CKSEL_SHIFT},
	{PMIC_CLK_FQMTR_CK_CKSEL, PMIC_CLK_FQMTR_CK_CKSEL_ADDR,
	 PMIC_CLK_FQMTR_CK_CKSEL_MASK, PMIC_CLK_FQMTR_CK_CKSEL_SHIFT},
	{PMIC_CLK_FGADC_ANA_CK_CKSEL, PMIC_CLK_FGADC_ANA_CK_CKSEL_ADDR,
	 PMIC_CLK_FGADC_ANA_CK_CKSEL_MASK, PMIC_CLK_FGADC_ANA_CK_CKSEL_SHIFT},
	{PMIC_CLK_PCHR_TEST_CK_CKSEL, PMIC_CLK_PCHR_TEST_CK_CKSEL_ADDR,
	 PMIC_CLK_PCHR_TEST_CK_CKSEL_MASK, PMIC_CLK_PCHR_TEST_CK_CKSEL_SHIFT},
	{PMIC_CLK_BGR_TEST_CK_CKSEL, PMIC_CLK_BGR_TEST_CK_CKSEL_ADDR,
	 PMIC_CLK_BGR_TEST_CK_CKSEL_MASK, PMIC_CLK_BGR_TEST_CK_CKSEL_SHIFT},
	{PMIC_CLK_EFUSE_CK_PDN_HWEN, PMIC_CLK_EFUSE_CK_PDN_HWEN_ADDR,
	 PMIC_CLK_EFUSE_CK_PDN_HWEN_MASK, PMIC_CLK_EFUSE_CK_PDN_HWEN_SHIFT},
	{PMIC_CLK_RSV_CKSEL, PMIC_CLK_RSV_CKSEL_ADDR, PMIC_CLK_RSV_CKSEL_MASK,
	 PMIC_CLK_RSV_CKSEL_SHIFT},
	{PMIC_CLK_CKSEL_CON0_SET, PMIC_CLK_CKSEL_CON0_SET_ADDR,
	 PMIC_CLK_CKSEL_CON0_SET_MASK, PMIC_CLK_CKSEL_CON0_SET_SHIFT},
	{PMIC_CLK_CKSEL_CON0_CLR, PMIC_CLK_CKSEL_CON0_CLR_ADDR,
	 PMIC_CLK_CKSEL_CON0_CLR_MASK, PMIC_CLK_CKSEL_CON0_CLR_SHIFT},
	{PMIC_CLK_AUXADC_SMPS_CK_DIVSEL, PMIC_CLK_AUXADC_SMPS_CK_DIVSEL_ADDR,
	 PMIC_CLK_AUXADC_SMPS_CK_DIVSEL_MASK, PMIC_CLK_AUXADC_SMPS_CK_DIVSEL_SHIFT},
	{PMIC_CLK_AUXADC_26M_CK_DIVSEL, PMIC_CLK_AUXADC_26M_CK_DIVSEL_ADDR,
	 PMIC_CLK_AUXADC_26M_CK_DIVSEL_MASK, PMIC_CLK_AUXADC_26M_CK_DIVSEL_SHIFT},
	{PMIC_CLK_BUCK_9M_CK_DIVSEL, PMIC_CLK_BUCK_9M_CK_DIVSEL_ADDR,
	 PMIC_CLK_BUCK_9M_CK_DIVSEL_MASK, PMIC_CLK_BUCK_9M_CK_DIVSEL_SHIFT},
	{PMIC_CLK_REG_CK_DIVSEL, PMIC_CLK_REG_CK_DIVSEL_ADDR,
	 PMIC_CLK_REG_CK_DIVSEL_MASK, PMIC_CLK_REG_CK_DIVSEL_SHIFT},
	{PMIC_CLK_SPK_CK_DIVSEL, PMIC_CLK_SPK_CK_DIVSEL_ADDR,
	 PMIC_CLK_SPK_CK_DIVSEL_MASK, PMIC_CLK_SPK_CK_DIVSEL_SHIFT},
	{PMIC_CLK_SPK_PWM_CK_DIVSEL, PMIC_CLK_SPK_PWM_CK_DIVSEL_ADDR,
	 PMIC_CLK_SPK_PWM_CK_DIVSEL_MASK, PMIC_CLK_SPK_PWM_CK_DIVSEL_SHIFT},
	{PMIC_CLK_RSV_DIVSEL, PMIC_CLK_RSV_DIVSEL_ADDR, PMIC_CLK_RSV_DIVSEL_MASK,
	 PMIC_CLK_RSV_DIVSEL_SHIFT},
	{PMIC_CLK_CKDIVSEL_CON0_SET, PMIC_CLK_CKDIVSEL_CON0_SET_ADDR,
	 PMIC_CLK_CKDIVSEL_CON0_SET_MASK, PMIC_CLK_CKDIVSEL_CON0_SET_SHIFT},
	{PMIC_CLK_CKDIVSEL_CON0_CLR, PMIC_CLK_CKDIVSEL_CON0_CLR_ADDR,
	 PMIC_CLK_CKDIVSEL_CON0_CLR_MASK, PMIC_CLK_CKDIVSEL_CON0_CLR_SHIFT},
	{PMIC_CLK_AUDIF_CK_TSTSEL, PMIC_CLK_AUDIF_CK_TSTSEL_ADDR,
	 PMIC_CLK_AUDIF_CK_TSTSEL_MASK, PMIC_CLK_AUDIF_CK_TSTSEL_SHIFT},
	{PMIC_CLK_AUD_CK_TSTSEL, PMIC_CLK_AUD_CK_TSTSEL_ADDR,
	 PMIC_CLK_AUD_CK_TSTSEL_MASK, PMIC_CLK_AUD_CK_TSTSEL_SHIFT},
	{PMIC_CLK_AUXADC_SMPS_CK_TSTSEL, PMIC_CLK_AUXADC_SMPS_CK_TSTSEL_ADDR,
	 PMIC_CLK_AUXADC_SMPS_CK_TSTSEL_MASK, PMIC_CLK_AUXADC_SMPS_CK_TSTSEL_SHIFT},
	{PMIC_CLK_AUXADC_26M_CK_TSTSEL, PMIC_CLK_AUXADC_26M_CK_TSTSEL_ADDR,
	 PMIC_CLK_AUXADC_26M_CK_TSTSEL_MASK, PMIC_CLK_AUXADC_26M_CK_TSTSEL_SHIFT},
	{PMIC_CLK_AUXADC_CK_TSTSEL, PMIC_CLK_AUXADC_CK_TSTSEL_ADDR,
	 PMIC_CLK_AUXADC_CK_TSTSEL_MASK, PMIC_CLK_AUXADC_CK_TSTSEL_SHIFT},
	{PMIC_CLK_DRV_CHRIND_CK_TSTSEL, PMIC_CLK_DRV_CHRIND_CK_TSTSEL_ADDR,
	 PMIC_CLK_DRV_CHRIND_CK_TSTSEL_MASK, PMIC_CLK_DRV_CHRIND_CK_TSTSEL_SHIFT},
	{PMIC_CLK_FQMTR_CK_TSTSEL, PMIC_CLK_FQMTR_CK_TSTSEL_ADDR,
	 PMIC_CLK_FQMTR_CK_TSTSEL_MASK, PMIC_CLK_FQMTR_CK_TSTSEL_SHIFT},
	{PMIC_CLK_RTCDET_CK_TSTSEL, PMIC_CLK_RTCDET_CK_TSTSEL_ADDR,
	 PMIC_CLK_RTCDET_CK_TSTSEL_MASK, PMIC_CLK_RTCDET_CK_TSTSEL_SHIFT},
	{PMIC_CLK_RTC_EOSC32_CK_TSTSEL, PMIC_CLK_RTC_EOSC32_CK_TSTSEL_ADDR,
	 PMIC_CLK_RTC_EOSC32_CK_TSTSEL_MASK, PMIC_CLK_RTC_EOSC32_CK_TSTSEL_SHIFT},
	{PMIC_CLK_EOSC_CALI_TEST_CK_TSTSEL, PMIC_CLK_EOSC_CALI_TEST_CK_TSTSEL_ADDR,
	 PMIC_CLK_EOSC_CALI_TEST_CK_TSTSEL_MASK,
	 PMIC_CLK_EOSC_CALI_TEST_CK_TSTSEL_SHIFT},
	{PMIC_CLK_FGADC_ANA_CK_TSTSEL, PMIC_CLK_FGADC_ANA_CK_TSTSEL_ADDR,
	 PMIC_CLK_FGADC_ANA_CK_TSTSEL_MASK, PMIC_CLK_FGADC_ANA_CK_TSTSEL_SHIFT},
	{PMIC_CLK_PCHR_TEST_CK_TSTSEL, PMIC_CLK_PCHR_TEST_CK_TSTSEL_ADDR,
	 PMIC_CLK_PCHR_TEST_CK_TSTSEL_MASK, PMIC_CLK_PCHR_TEST_CK_TSTSEL_SHIFT},
	{PMIC_CLK_BGR_TEST_CK_TSTSEL, PMIC_CLK_BGR_TEST_CK_TSTSEL_ADDR,
	 PMIC_CLK_BGR_TEST_CK_TSTSEL_MASK, PMIC_CLK_BGR_TEST_CK_TSTSEL_SHIFT},
	{PMIC_CLK_RSV_TSTSEL, PMIC_CLK_RSV_TSTSEL_ADDR, PMIC_CLK_RSV_TSTSEL_MASK,
	 PMIC_CLK_RSV_TSTSEL_SHIFT},
	{PMIC_RG_EFUSE_MAN_RST, PMIC_RG_EFUSE_MAN_RST_ADDR,
	 PMIC_RG_EFUSE_MAN_RST_MASK, PMIC_RG_EFUSE_MAN_RST_SHIFT},
	{PMIC_RG_AUXADC_RST, PMIC_RG_AUXADC_RST_ADDR, PMIC_RG_AUXADC_RST_MASK,
	 PMIC_RG_AUXADC_RST_SHIFT},
	{PMIC_RG_AUXADC_REG_RST, PMIC_RG_AUXADC_REG_RST_ADDR,
	 PMIC_RG_AUXADC_REG_RST_MASK, PMIC_RG_AUXADC_REG_RST_SHIFT},
	{PMIC_RG_AUDIO_RST, PMIC_RG_AUDIO_RST_ADDR, PMIC_RG_AUDIO_RST_MASK,
	 PMIC_RG_AUDIO_RST_SHIFT},
	{PMIC_RG_ACCDET_RST, PMIC_RG_ACCDET_RST_ADDR, PMIC_RG_ACCDET_RST_MASK,
	 PMIC_RG_ACCDET_RST_SHIFT},
	{PMIC_RG_BIF_RST, PMIC_RG_BIF_RST_ADDR, PMIC_RG_BIF_RST_MASK,
	 PMIC_RG_BIF_RST_SHIFT},
	{PMIC_RG_DRIVER_RST, PMIC_RG_DRIVER_RST_ADDR, PMIC_RG_DRIVER_RST_MASK,
	 PMIC_RG_DRIVER_RST_SHIFT},
	{PMIC_RG_FGADC_RST, PMIC_RG_FGADC_RST_ADDR, PMIC_RG_FGADC_RST_MASK,
	 PMIC_RG_FGADC_RST_SHIFT},
	{PMIC_RG_FQMTR_RST, PMIC_RG_FQMTR_RST_ADDR, PMIC_RG_FQMTR_RST_MASK,
	 PMIC_RG_FQMTR_RST_SHIFT},
	{PMIC_RG_RTC_RST, PMIC_RG_RTC_RST_ADDR, PMIC_RG_RTC_RST_MASK,
	 PMIC_RG_RTC_RST_SHIFT},
	{PMIC_RG_TYPE_C_CC_RST, PMIC_RG_TYPE_C_CC_RST_ADDR,
	 PMIC_RG_TYPE_C_CC_RST_MASK, PMIC_RG_TYPE_C_CC_RST_SHIFT},
	{PMIC_RG_CHRWDT_RST, PMIC_RG_CHRWDT_RST_ADDR, PMIC_RG_CHRWDT_RST_MASK,
	 PMIC_RG_CHRWDT_RST_SHIFT},
	{PMIC_RG_ZCD_RST, PMIC_RG_ZCD_RST_ADDR, PMIC_RG_ZCD_RST_MASK,
	 PMIC_RG_ZCD_RST_SHIFT},
	{PMIC_RG_AUDNCP_RST, PMIC_RG_AUDNCP_RST_ADDR, PMIC_RG_AUDNCP_RST_MASK,
	 PMIC_RG_AUDNCP_RST_SHIFT},
	{PMIC_RG_CLK_TRIM_RST, PMIC_RG_CLK_TRIM_RST_ADDR, PMIC_RG_CLK_TRIM_RST_MASK,
	 PMIC_RG_CLK_TRIM_RST_SHIFT},
	{PMIC_RG_BUCK_SRCLKEN_RST, PMIC_RG_BUCK_SRCLKEN_RST_ADDR,
	 PMIC_RG_BUCK_SRCLKEN_RST_MASK, PMIC_RG_BUCK_SRCLKEN_RST_SHIFT},
	{PMIC_TOP_RST_CON0_SET, PMIC_TOP_RST_CON0_SET_ADDR,
	 PMIC_TOP_RST_CON0_SET_MASK, PMIC_TOP_RST_CON0_SET_SHIFT},
	{PMIC_TOP_RST_CON0_CLR, PMIC_TOP_RST_CON0_CLR_ADDR,
	 PMIC_TOP_RST_CON0_CLR_MASK, PMIC_TOP_RST_CON0_CLR_SHIFT},
	{PMIC_RG_STRUP_LONG_PRESS_RST, PMIC_RG_STRUP_LONG_PRESS_RST_ADDR,
	 PMIC_RG_STRUP_LONG_PRESS_RST_MASK, PMIC_RG_STRUP_LONG_PRESS_RST_SHIFT},
	{PMIC_RG_BUCK_PROT_PMPP_RST, PMIC_RG_BUCK_PROT_PMPP_RST_ADDR,
	 PMIC_RG_BUCK_PROT_PMPP_RST_MASK, PMIC_RG_BUCK_PROT_PMPP_RST_SHIFT},
	{PMIC_RG_SPK_RST, PMIC_RG_SPK_RST_ADDR, PMIC_RG_SPK_RST_MASK,
	 PMIC_RG_SPK_RST_SHIFT},
	{PMIC_TOP_RST_CON1_RSV, PMIC_TOP_RST_CON1_RSV_ADDR,
	 PMIC_TOP_RST_CON1_RSV_MASK, PMIC_TOP_RST_CON1_RSV_SHIFT},
	{PMIC_TOP_RST_CON1_SET, PMIC_TOP_RST_CON1_SET_ADDR,
	 PMIC_TOP_RST_CON1_SET_MASK, PMIC_TOP_RST_CON1_SET_SHIFT},
	{PMIC_TOP_RST_CON1_CLR, PMIC_TOP_RST_CON1_CLR_ADDR,
	 PMIC_TOP_RST_CON1_CLR_MASK, PMIC_TOP_RST_CON1_CLR_SHIFT},
	{PMIC_RG_CHR_LDO_DET_MODE, PMIC_RG_CHR_LDO_DET_MODE_ADDR,
	 PMIC_RG_CHR_LDO_DET_MODE_MASK, PMIC_RG_CHR_LDO_DET_MODE_SHIFT},
	{PMIC_RG_CHR_LDO_DET_SW, PMIC_RG_CHR_LDO_DET_SW_ADDR,
	 PMIC_RG_CHR_LDO_DET_SW_MASK, PMIC_RG_CHR_LDO_DET_SW_SHIFT},
	{PMIC_RG_CHRWDT_FLAG_MODE, PMIC_RG_CHRWDT_FLAG_MODE_ADDR,
	 PMIC_RG_CHRWDT_FLAG_MODE_MASK, PMIC_RG_CHRWDT_FLAG_MODE_SHIFT},
	{PMIC_RG_CHRWDT_FLAG_SW, PMIC_RG_CHRWDT_FLAG_SW_ADDR,
	 PMIC_RG_CHRWDT_FLAG_SW_MASK, PMIC_RG_CHRWDT_FLAG_SW_SHIFT},
	{PMIC_TOP_RST_CON2_RSV, PMIC_TOP_RST_CON2_RSV_ADDR,
	 PMIC_TOP_RST_CON2_RSV_MASK, PMIC_TOP_RST_CON2_RSV_SHIFT},
	{PMIC_RG_WDTRSTB_EN, PMIC_RG_WDTRSTB_EN_ADDR, PMIC_RG_WDTRSTB_EN_MASK,
	 PMIC_RG_WDTRSTB_EN_SHIFT},
	{PMIC_RG_WDTRSTB_MODE, PMIC_RG_WDTRSTB_MODE_ADDR, PMIC_RG_WDTRSTB_MODE_MASK,
	 PMIC_RG_WDTRSTB_MODE_SHIFT},
	{PMIC_WDTRSTB_STATUS, PMIC_WDTRSTB_STATUS_ADDR, PMIC_WDTRSTB_STATUS_MASK,
	 PMIC_WDTRSTB_STATUS_SHIFT},
	{PMIC_WDTRSTB_STATUS_CLR, PMIC_WDTRSTB_STATUS_CLR_ADDR,
	 PMIC_WDTRSTB_STATUS_CLR_MASK, PMIC_WDTRSTB_STATUS_CLR_SHIFT},
	{PMIC_RG_WDTRSTB_FB_EN, PMIC_RG_WDTRSTB_FB_EN_ADDR,
	 PMIC_RG_WDTRSTB_FB_EN_MASK, PMIC_RG_WDTRSTB_FB_EN_SHIFT},
	{PMIC_RG_WDTRSTB_DEB, PMIC_RG_WDTRSTB_DEB_ADDR, PMIC_RG_WDTRSTB_DEB_MASK,
	 PMIC_RG_WDTRSTB_DEB_SHIFT},
	{PMIC_RG_HOMEKEY_RST_EN, PMIC_RG_HOMEKEY_RST_EN_ADDR,
	 PMIC_RG_HOMEKEY_RST_EN_MASK, PMIC_RG_HOMEKEY_RST_EN_SHIFT},
	{PMIC_RG_PWRKEY_RST_EN, PMIC_RG_PWRKEY_RST_EN_ADDR,
	 PMIC_RG_PWRKEY_RST_EN_MASK, PMIC_RG_PWRKEY_RST_EN_SHIFT},
	{PMIC_RG_PWRRST_TMR_DIS, PMIC_RG_PWRRST_TMR_DIS_ADDR,
	 PMIC_RG_PWRRST_TMR_DIS_MASK, PMIC_RG_PWRRST_TMR_DIS_SHIFT},
	{PMIC_RG_PWRKEY_RST_TD, PMIC_RG_PWRKEY_RST_TD_ADDR,
	 PMIC_RG_PWRKEY_RST_TD_MASK, PMIC_RG_PWRKEY_RST_TD_SHIFT},
	{PMIC_TOP_RST_MISC_RSV, PMIC_TOP_RST_MISC_RSV_ADDR,
	 PMIC_TOP_RST_MISC_RSV_MASK, PMIC_TOP_RST_MISC_RSV_SHIFT},
	{PMIC_TOP_RST_MISC_SET, PMIC_TOP_RST_MISC_SET_ADDR,
	 PMIC_TOP_RST_MISC_SET_MASK, PMIC_TOP_RST_MISC_SET_SHIFT},
	{PMIC_TOP_RST_MISC_CLR, PMIC_TOP_RST_MISC_CLR_ADDR,
	 PMIC_TOP_RST_MISC_CLR_MASK, PMIC_TOP_RST_MISC_CLR_SHIFT},
	{PMIC_VPWRIN_RSTB_STATUS, PMIC_VPWRIN_RSTB_STATUS_ADDR,
	 PMIC_VPWRIN_RSTB_STATUS_MASK, PMIC_VPWRIN_RSTB_STATUS_SHIFT},
	{PMIC_DDLO_RSTB_STATUS, PMIC_DDLO_RSTB_STATUS_ADDR,
	 PMIC_DDLO_RSTB_STATUS_MASK, PMIC_DDLO_RSTB_STATUS_SHIFT},
	{PMIC_UVLO_RSTB_STATUS, PMIC_UVLO_RSTB_STATUS_ADDR,
	 PMIC_UVLO_RSTB_STATUS_MASK, PMIC_UVLO_RSTB_STATUS_SHIFT},
	{PMIC_RTC_DDLO_RSTB_STATUS, PMIC_RTC_DDLO_RSTB_STATUS_ADDR,
	 PMIC_RTC_DDLO_RSTB_STATUS_MASK, PMIC_RTC_DDLO_RSTB_STATUS_SHIFT},
	{PMIC_CHRWDT_REG_RSTB_STATUS, PMIC_CHRWDT_REG_RSTB_STATUS_ADDR,
	 PMIC_CHRWDT_REG_RSTB_STATUS_MASK, PMIC_CHRWDT_REG_RSTB_STATUS_SHIFT},
	{PMIC_CHRDET_REG_RSTB_STATUS, PMIC_CHRDET_REG_RSTB_STATUS_ADDR,
	 PMIC_CHRDET_REG_RSTB_STATUS_MASK, PMIC_CHRDET_REG_RSTB_STATUS_SHIFT},
	{PMIC_TOP_RST_STATUS_RSV, PMIC_TOP_RST_STATUS_RSV_ADDR,
	 PMIC_TOP_RST_STATUS_RSV_MASK, PMIC_TOP_RST_STATUS_RSV_SHIFT},
	{PMIC_TOP_RST_STATUS_SET, PMIC_TOP_RST_STATUS_SET_ADDR,
	 PMIC_TOP_RST_STATUS_SET_MASK, PMIC_TOP_RST_STATUS_SET_SHIFT},
	{PMIC_TOP_RST_STATUS_CLR, PMIC_TOP_RST_STATUS_CLR_ADDR,
	 PMIC_TOP_RST_STATUS_CLR_MASK, PMIC_TOP_RST_STATUS_CLR_SHIFT},
	{PMIC_TOP_RST_RSV_CON0, PMIC_TOP_RST_RSV_CON0_ADDR,
	 PMIC_TOP_RST_RSV_CON0_MASK, PMIC_TOP_RST_RSV_CON0_SHIFT},
	{PMIC_TOP_RST_RSV_CON1, PMIC_TOP_RST_RSV_CON1_ADDR,
	 PMIC_TOP_RST_RSV_CON1_MASK, PMIC_TOP_RST_RSV_CON1_SHIFT},
	{PMIC_RG_INT_EN_PWRKEY, PMIC_RG_INT_EN_PWRKEY_ADDR,
	 PMIC_RG_INT_EN_PWRKEY_MASK, PMIC_RG_INT_EN_PWRKEY_SHIFT},
	{PMIC_RG_INT_EN_HOMEKEY, PMIC_RG_INT_EN_HOMEKEY_ADDR,
	 PMIC_RG_INT_EN_HOMEKEY_MASK, PMIC_RG_INT_EN_HOMEKEY_SHIFT},
	{PMIC_RG_INT_EN_PWRKEY_R, PMIC_RG_INT_EN_PWRKEY_R_ADDR,
	 PMIC_RG_INT_EN_PWRKEY_R_MASK, PMIC_RG_INT_EN_PWRKEY_R_SHIFT},
	{PMIC_RG_INT_EN_HOMEKEY_R, PMIC_RG_INT_EN_HOMEKEY_R_ADDR,
	 PMIC_RG_INT_EN_HOMEKEY_R_MASK, PMIC_RG_INT_EN_HOMEKEY_R_SHIFT},
	{PMIC_RG_INT_EN_THR_H, PMIC_RG_INT_EN_THR_H_ADDR, PMIC_RG_INT_EN_THR_H_MASK,
	 PMIC_RG_INT_EN_THR_H_SHIFT},
	{PMIC_RG_INT_EN_THR_L, PMIC_RG_INT_EN_THR_L_ADDR, PMIC_RG_INT_EN_THR_L_MASK,
	 PMIC_RG_INT_EN_THR_L_SHIFT},
	{PMIC_RG_INT_EN_BAT_H, PMIC_RG_INT_EN_BAT_H_ADDR, PMIC_RG_INT_EN_BAT_H_MASK,
	 PMIC_RG_INT_EN_BAT_H_SHIFT},
	{PMIC_RG_INT_EN_BAT_L, PMIC_RG_INT_EN_BAT_L_ADDR, PMIC_RG_INT_EN_BAT_L_MASK,
	 PMIC_RG_INT_EN_BAT_L_SHIFT},
	{PMIC_RG_INT_EN_RTC, PMIC_RG_INT_EN_RTC_ADDR, PMIC_RG_INT_EN_RTC_MASK,
	 PMIC_RG_INT_EN_RTC_SHIFT},
	{PMIC_RG_INT_EN_AUDIO, PMIC_RG_INT_EN_AUDIO_ADDR, PMIC_RG_INT_EN_AUDIO_MASK,
	 PMIC_RG_INT_EN_AUDIO_SHIFT},
	{PMIC_RG_INT_EN_ACCDET, PMIC_RG_INT_EN_ACCDET_ADDR,
	 PMIC_RG_INT_EN_ACCDET_MASK, PMIC_RG_INT_EN_ACCDET_SHIFT},
	{PMIC_RG_INT_EN_ACCDET_EINT, PMIC_RG_INT_EN_ACCDET_EINT_ADDR,
	 PMIC_RG_INT_EN_ACCDET_EINT_MASK, PMIC_RG_INT_EN_ACCDET_EINT_SHIFT},
	{PMIC_RG_INT_EN_ACCDET_NEGV, PMIC_RG_INT_EN_ACCDET_NEGV_ADDR,
	 PMIC_RG_INT_EN_ACCDET_NEGV_MASK, PMIC_RG_INT_EN_ACCDET_NEGV_SHIFT},
	{PMIC_RG_INT_EN_NI_LBAT_INT, PMIC_RG_INT_EN_NI_LBAT_INT_ADDR,
	 PMIC_RG_INT_EN_NI_LBAT_INT_MASK, PMIC_RG_INT_EN_NI_LBAT_INT_SHIFT},
	{PMIC_INT_CON0_SET, PMIC_INT_CON0_SET_ADDR, PMIC_INT_CON0_SET_MASK,
	 PMIC_INT_CON0_SET_SHIFT},
	{PMIC_INT_CON0_CLR, PMIC_INT_CON0_CLR_ADDR, PMIC_INT_CON0_CLR_MASK,
	 PMIC_INT_CON0_CLR_SHIFT},
	{PMIC_RG_INT_EN_VCORE_OC, PMIC_RG_INT_EN_VCORE_OC_ADDR,
	 PMIC_RG_INT_EN_VCORE_OC_MASK, PMIC_RG_INT_EN_VCORE_OC_SHIFT},
	{PMIC_RG_INT_EN_VPROC_OC, PMIC_RG_INT_EN_VPROC_OC_ADDR,
	 PMIC_RG_INT_EN_VPROC_OC_MASK, PMIC_RG_INT_EN_VPROC_OC_SHIFT},
	{PMIC_RG_INT_EN_VS1_OC, PMIC_RG_INT_EN_VS1_OC_ADDR,
	 PMIC_RG_INT_EN_VS1_OC_MASK, PMIC_RG_INT_EN_VS1_OC_SHIFT},
	{PMIC_RG_INT_EN_VPA_OC, PMIC_RG_INT_EN_VPA_OC_ADDR,
	 PMIC_RG_INT_EN_VPA_OC_MASK, PMIC_RG_INT_EN_VPA_OC_SHIFT},
	{PMIC_RG_INT_EN_SPKL_D, PMIC_RG_INT_EN_SPKL_D_ADDR,
	 PMIC_RG_INT_EN_SPKL_D_MASK, PMIC_RG_INT_EN_SPKL_D_SHIFT},
	{PMIC_RG_INT_EN_SPKL_AB, PMIC_RG_INT_EN_SPKL_AB_ADDR,
	 PMIC_RG_INT_EN_SPKL_AB_MASK, PMIC_RG_INT_EN_SPKL_AB_SHIFT},
	{PMIC_RG_INT_EN_LDO_OC, PMIC_RG_INT_EN_LDO_OC_ADDR,
	 PMIC_RG_INT_EN_LDO_OC_MASK, PMIC_RG_INT_EN_LDO_OC_SHIFT},
	{PMIC_INT_CON1_SET, PMIC_INT_CON1_SET_ADDR, PMIC_INT_CON1_SET_MASK,
	 PMIC_INT_CON1_SET_SHIFT},
	{PMIC_INT_CON1_CLR, PMIC_INT_CON1_CLR_ADDR, PMIC_INT_CON1_CLR_MASK,
	 PMIC_INT_CON1_CLR_SHIFT},
	{PMIC_RG_INT_EN_TYPE_C_L_MIN, PMIC_RG_INT_EN_TYPE_C_L_MIN_ADDR,
	 PMIC_RG_INT_EN_TYPE_C_L_MIN_MASK, PMIC_RG_INT_EN_TYPE_C_L_MIN_SHIFT},
	{PMIC_RG_INT_EN_TYPE_C_L_MAX, PMIC_RG_INT_EN_TYPE_C_L_MAX_ADDR,
	 PMIC_RG_INT_EN_TYPE_C_L_MAX_MASK, PMIC_RG_INT_EN_TYPE_C_L_MAX_SHIFT},
	{PMIC_RG_INT_EN_TYPE_C_H_MIN, PMIC_RG_INT_EN_TYPE_C_H_MIN_ADDR,
	 PMIC_RG_INT_EN_TYPE_C_H_MIN_MASK, PMIC_RG_INT_EN_TYPE_C_H_MIN_SHIFT},
	{PMIC_RG_INT_EN_TYPE_C_H_MAX, PMIC_RG_INT_EN_TYPE_C_H_MAX_ADDR,
	 PMIC_RG_INT_EN_TYPE_C_H_MAX_MASK, PMIC_RG_INT_EN_TYPE_C_H_MAX_SHIFT},
	{PMIC_RG_INT_EN_AUXADC_IMP, PMIC_RG_INT_EN_AUXADC_IMP_ADDR,
	 PMIC_RG_INT_EN_AUXADC_IMP_MASK, PMIC_RG_INT_EN_AUXADC_IMP_SHIFT},
	{PMIC_RG_INT_EN_NAG_C_DLTV, PMIC_RG_INT_EN_NAG_C_DLTV_ADDR,
	 PMIC_RG_INT_EN_NAG_C_DLTV_MASK, PMIC_RG_INT_EN_NAG_C_DLTV_SHIFT},
	{PMIC_RG_INT_EN_TYPE_C_CC_IRQ, PMIC_RG_INT_EN_TYPE_C_CC_IRQ_ADDR,
	 PMIC_RG_INT_EN_TYPE_C_CC_IRQ_MASK, PMIC_RG_INT_EN_TYPE_C_CC_IRQ_SHIFT},
	{PMIC_RG_INT_EN_CHRDET_EDGE, PMIC_RG_INT_EN_CHRDET_EDGE_ADDR,
	 PMIC_RG_INT_EN_CHRDET_EDGE_MASK, PMIC_RG_INT_EN_CHRDET_EDGE_SHIFT},
	{PMIC_RG_INT_EN_OV, PMIC_RG_INT_EN_OV_ADDR, PMIC_RG_INT_EN_OV_MASK,
	 PMIC_RG_INT_EN_OV_SHIFT},
	{PMIC_RG_INT_EN_BVALID_DET, PMIC_RG_INT_EN_BVALID_DET_ADDR,
	 PMIC_RG_INT_EN_BVALID_DET_MASK, PMIC_RG_INT_EN_BVALID_DET_SHIFT},
	{PMIC_RG_INT_EN_RGS_BATON_HV, PMIC_RG_INT_EN_RGS_BATON_HV_ADDR,
	 PMIC_RG_INT_EN_RGS_BATON_HV_MASK, PMIC_RG_INT_EN_RGS_BATON_HV_SHIFT},
	{PMIC_RG_INT_EN_VBATON_UNDET, PMIC_RG_INT_EN_VBATON_UNDET_ADDR,
	 PMIC_RG_INT_EN_VBATON_UNDET_MASK, PMIC_RG_INT_EN_VBATON_UNDET_SHIFT},
	{PMIC_RG_INT_EN_WATCHDOG, PMIC_RG_INT_EN_WATCHDOG_ADDR,
	 PMIC_RG_INT_EN_WATCHDOG_MASK, PMIC_RG_INT_EN_WATCHDOG_SHIFT},
	{PMIC_RG_INT_EN_PCHR_CM_VDEC, PMIC_RG_INT_EN_PCHR_CM_VDEC_ADDR,
	 PMIC_RG_INT_EN_PCHR_CM_VDEC_MASK, PMIC_RG_INT_EN_PCHR_CM_VDEC_SHIFT},
	{PMIC_RG_INT_EN_CHRDET, PMIC_RG_INT_EN_CHRDET_ADDR,
	 PMIC_RG_INT_EN_CHRDET_MASK, PMIC_RG_INT_EN_CHRDET_SHIFT},
	{PMIC_RG_INT_EN_PCHR_CM_VINC, PMIC_RG_INT_EN_PCHR_CM_VINC_ADDR,
	 PMIC_RG_INT_EN_PCHR_CM_VINC_MASK, PMIC_RG_INT_EN_PCHR_CM_VINC_SHIFT},
	{PMIC_INT_CON2_SET, PMIC_INT_CON2_SET_ADDR, PMIC_INT_CON2_SET_MASK,
	 PMIC_INT_CON2_SET_SHIFT},
	{PMIC_INT_CON2_CLR, PMIC_INT_CON2_CLR_ADDR, PMIC_INT_CON2_CLR_MASK,
	 PMIC_INT_CON2_CLR_SHIFT},
	{PMIC_RG_INT_EN_FG_BAT_H, PMIC_RG_INT_EN_FG_BAT_H_ADDR,
	 PMIC_RG_INT_EN_FG_BAT_H_MASK, PMIC_RG_INT_EN_FG_BAT_H_SHIFT},
	{PMIC_RG_INT_EN_FG_BAT_L, PMIC_RG_INT_EN_FG_BAT_L_ADDR,
	 PMIC_RG_INT_EN_FG_BAT_L_MASK, PMIC_RG_INT_EN_FG_BAT_L_SHIFT},
	{PMIC_RG_INT_EN_FG_CUR_H, PMIC_RG_INT_EN_FG_CUR_H_ADDR,
	 PMIC_RG_INT_EN_FG_CUR_H_MASK, PMIC_RG_INT_EN_FG_CUR_H_SHIFT},
	{PMIC_RG_INT_EN_FG_CUR_L, PMIC_RG_INT_EN_FG_CUR_L_ADDR,
	 PMIC_RG_INT_EN_FG_CUR_L_MASK, PMIC_RG_INT_EN_FG_CUR_L_SHIFT},
	{PMIC_RG_INT_EN_FG_ZCV, PMIC_RG_INT_EN_FG_ZCV_ADDR,
	 PMIC_RG_INT_EN_FG_ZCV_MASK, PMIC_RG_INT_EN_FG_ZCV_SHIFT},
	{PMIC_INT_CON3_SET, PMIC_INT_CON3_SET_ADDR, PMIC_INT_CON3_SET_MASK,
	 PMIC_INT_CON3_SET_SHIFT},
	{PMIC_INT_CON3_CLR, PMIC_INT_CON3_CLR_ADDR, PMIC_INT_CON3_CLR_MASK,
	 PMIC_INT_CON3_CLR_SHIFT},
	{PMIC_POLARITY, PMIC_POLARITY_ADDR, PMIC_POLARITY_MASK,
	 PMIC_POLARITY_SHIFT},
	{PMIC_RG_HOMEKEY_INT_SEL, PMIC_RG_HOMEKEY_INT_SEL_ADDR,
	 PMIC_RG_HOMEKEY_INT_SEL_MASK, PMIC_RG_HOMEKEY_INT_SEL_SHIFT},
	{PMIC_RG_PWRKEY_INT_SEL, PMIC_RG_PWRKEY_INT_SEL_ADDR,
	 PMIC_RG_PWRKEY_INT_SEL_MASK, PMIC_RG_PWRKEY_INT_SEL_SHIFT},
	{PMIC_RG_CHRDET_INT_SEL, PMIC_RG_CHRDET_INT_SEL_ADDR,
	 PMIC_RG_CHRDET_INT_SEL_MASK, PMIC_RG_CHRDET_INT_SEL_SHIFT},
	{PMIC_RG_PCHR_CM_VINC_POLARITY_RSV, PMIC_RG_PCHR_CM_VINC_POLARITY_RSV_ADDR,
	 PMIC_RG_PCHR_CM_VINC_POLARITY_RSV_MASK,
	 PMIC_RG_PCHR_CM_VINC_POLARITY_RSV_SHIFT},
	{PMIC_RG_PCHR_CM_VDEC_POLARITY_RSV, PMIC_RG_PCHR_CM_VDEC_POLARITY_RSV_ADDR,
	 PMIC_RG_PCHR_CM_VDEC_POLARITY_RSV_MASK,
	 PMIC_RG_PCHR_CM_VDEC_POLARITY_RSV_SHIFT},
	{PMIC_INT_MISC_CON_SET, PMIC_INT_MISC_CON_SET_ADDR,
	 PMIC_INT_MISC_CON_SET_MASK, PMIC_INT_MISC_CON_SET_SHIFT},
	{PMIC_INT_MISC_CON_CLR, PMIC_INT_MISC_CON_CLR_ADDR,
	 PMIC_INT_MISC_CON_CLR_MASK, PMIC_INT_MISC_CON_CLR_SHIFT},
	{PMIC_RG_INT_STATUS_PWRKEY, PMIC_RG_INT_STATUS_PWRKEY_ADDR,
	 PMIC_RG_INT_STATUS_PWRKEY_MASK, PMIC_RG_INT_STATUS_PWRKEY_SHIFT},
	{PMIC_RG_INT_STATUS_HOMEKEY, PMIC_RG_INT_STATUS_HOMEKEY_ADDR,
	 PMIC_RG_INT_STATUS_HOMEKEY_MASK, PMIC_RG_INT_STATUS_HOMEKEY_SHIFT},
	{PMIC_RG_INT_STATUS_PWRKEY_R, PMIC_RG_INT_STATUS_PWRKEY_R_ADDR,
	 PMIC_RG_INT_STATUS_PWRKEY_R_MASK, PMIC_RG_INT_STATUS_PWRKEY_R_SHIFT},
	{PMIC_RG_INT_STATUS_HOMEKEY_R, PMIC_RG_INT_STATUS_HOMEKEY_R_ADDR,
	 PMIC_RG_INT_STATUS_HOMEKEY_R_MASK, PMIC_RG_INT_STATUS_HOMEKEY_R_SHIFT},
	{PMIC_RG_INT_STATUS_THR_H, PMIC_RG_INT_STATUS_THR_H_ADDR,
	 PMIC_RG_INT_STATUS_THR_H_MASK, PMIC_RG_INT_STATUS_THR_H_SHIFT},
	{PMIC_RG_INT_STATUS_THR_L, PMIC_RG_INT_STATUS_THR_L_ADDR,
	 PMIC_RG_INT_STATUS_THR_L_MASK, PMIC_RG_INT_STATUS_THR_L_SHIFT},
	{PMIC_RG_INT_STATUS_BAT_H, PMIC_RG_INT_STATUS_BAT_H_ADDR,
	 PMIC_RG_INT_STATUS_BAT_H_MASK, PMIC_RG_INT_STATUS_BAT_H_SHIFT},
	{PMIC_RG_INT_STATUS_BAT_L, PMIC_RG_INT_STATUS_BAT_L_ADDR,
	 PMIC_RG_INT_STATUS_BAT_L_MASK, PMIC_RG_INT_STATUS_BAT_L_SHIFT},
	{PMIC_RG_INT_STATUS_RTC, PMIC_RG_INT_STATUS_RTC_ADDR,
	 PMIC_RG_INT_STATUS_RTC_MASK, PMIC_RG_INT_STATUS_RTC_SHIFT},
	{PMIC_RG_INT_STATUS_AUDIO, PMIC_RG_INT_STATUS_AUDIO_ADDR,
	 PMIC_RG_INT_STATUS_AUDIO_MASK, PMIC_RG_INT_STATUS_AUDIO_SHIFT},
	{PMIC_RG_INT_STATUS_ACCDET, PMIC_RG_INT_STATUS_ACCDET_ADDR,
	 PMIC_RG_INT_STATUS_ACCDET_MASK, PMIC_RG_INT_STATUS_ACCDET_SHIFT},
	{PMIC_RG_INT_STATUS_ACCDET_EINT, PMIC_RG_INT_STATUS_ACCDET_EINT_ADDR,
	 PMIC_RG_INT_STATUS_ACCDET_EINT_MASK, PMIC_RG_INT_STATUS_ACCDET_EINT_SHIFT},
	{PMIC_RG_INT_STATUS_ACCDET_NEGV, PMIC_RG_INT_STATUS_ACCDET_NEGV_ADDR,
	 PMIC_RG_INT_STATUS_ACCDET_NEGV_MASK, PMIC_RG_INT_STATUS_ACCDET_NEGV_SHIFT},
	{PMIC_RG_INT_STATUS_NI_LBAT_INT, PMIC_RG_INT_STATUS_NI_LBAT_INT_ADDR,
	 PMIC_RG_INT_STATUS_NI_LBAT_INT_MASK, PMIC_RG_INT_STATUS_NI_LBAT_INT_SHIFT},
	{PMIC_RG_INT_STATUS_VCORE_OC, PMIC_RG_INT_STATUS_VCORE_OC_ADDR,
	 PMIC_RG_INT_STATUS_VCORE_OC_MASK, PMIC_RG_INT_STATUS_VCORE_OC_SHIFT},
	{PMIC_RG_INT_STATUS_VPROC_OC, PMIC_RG_INT_STATUS_VPROC_OC_ADDR,
	 PMIC_RG_INT_STATUS_VPROC_OC_MASK, PMIC_RG_INT_STATUS_VPROC_OC_SHIFT},
	{PMIC_RG_INT_STATUS_VS1_OC, PMIC_RG_INT_STATUS_VS1_OC_ADDR,
	 PMIC_RG_INT_STATUS_VS1_OC_MASK, PMIC_RG_INT_STATUS_VS1_OC_SHIFT},
	{PMIC_RG_INT_STATUS_VPA_OC, PMIC_RG_INT_STATUS_VPA_OC_ADDR,
	 PMIC_RG_INT_STATUS_VPA_OC_MASK, PMIC_RG_INT_STATUS_VPA_OC_SHIFT},
	{PMIC_RG_INT_STATUS_SPKL_D, PMIC_RG_INT_STATUS_SPKL_D_ADDR,
	 PMIC_RG_INT_STATUS_SPKL_D_MASK, PMIC_RG_INT_STATUS_SPKL_D_SHIFT},
	{PMIC_RG_INT_STATUS_SPKL_AB, PMIC_RG_INT_STATUS_SPKL_AB_ADDR,
	 PMIC_RG_INT_STATUS_SPKL_AB_MASK, PMIC_RG_INT_STATUS_SPKL_AB_SHIFT},
	{PMIC_RG_INT_STATUS_LDO_OC, PMIC_RG_INT_STATUS_LDO_OC_ADDR,
	 PMIC_RG_INT_STATUS_LDO_OC_MASK, PMIC_RG_INT_STATUS_LDO_OC_SHIFT},
	{PMIC_RG_INT_STATUS_TYPE_C_L_MIN, PMIC_RG_INT_STATUS_TYPE_C_L_MIN_ADDR,
	 PMIC_RG_INT_STATUS_TYPE_C_L_MIN_MASK, PMIC_RG_INT_STATUS_TYPE_C_L_MIN_SHIFT},
	{PMIC_RG_INT_STATUS_TYPE_C_L_MAX, PMIC_RG_INT_STATUS_TYPE_C_L_MAX_ADDR,
	 PMIC_RG_INT_STATUS_TYPE_C_L_MAX_MASK, PMIC_RG_INT_STATUS_TYPE_C_L_MAX_SHIFT},
	{PMIC_RG_INT_STATUS_TYPE_C_H_MIN, PMIC_RG_INT_STATUS_TYPE_C_H_MIN_ADDR,
	 PMIC_RG_INT_STATUS_TYPE_C_H_MIN_MASK, PMIC_RG_INT_STATUS_TYPE_C_H_MIN_SHIFT},
	{PMIC_RG_INT_STATUS_TYPE_C_H_MAX, PMIC_RG_INT_STATUS_TYPE_C_H_MAX_ADDR,
	 PMIC_RG_INT_STATUS_TYPE_C_H_MAX_MASK, PMIC_RG_INT_STATUS_TYPE_C_H_MAX_SHIFT},
	{PMIC_RG_INT_STATUS_AUXADC_IMP, PMIC_RG_INT_STATUS_AUXADC_IMP_ADDR,
	 PMIC_RG_INT_STATUS_AUXADC_IMP_MASK, PMIC_RG_INT_STATUS_AUXADC_IMP_SHIFT},
	{PMIC_RG_INT_STATUS_NAG_C_DLTV, PMIC_RG_INT_STATUS_NAG_C_DLTV_ADDR,
	 PMIC_RG_INT_STATUS_NAG_C_DLTV_MASK, PMIC_RG_INT_STATUS_NAG_C_DLTV_SHIFT},
	{PMIC_RG_INT_STATUS_TYPE_C_CC_IRQ, PMIC_RG_INT_STATUS_TYPE_C_CC_IRQ_ADDR,
	 PMIC_RG_INT_STATUS_TYPE_C_CC_IRQ_MASK,
	 PMIC_RG_INT_STATUS_TYPE_C_CC_IRQ_SHIFT},
	{PMIC_RG_INT_STATUS_CHRDET_EDGE, PMIC_RG_INT_STATUS_CHRDET_EDGE_ADDR,
	 PMIC_RG_INT_STATUS_CHRDET_EDGE_MASK, PMIC_RG_INT_STATUS_CHRDET_EDGE_SHIFT},
	{PMIC_RG_INT_STATUS_OV, PMIC_RG_INT_STATUS_OV_ADDR,
	 PMIC_RG_INT_STATUS_OV_MASK, PMIC_RG_INT_STATUS_OV_SHIFT},
	{PMIC_RG_INT_STATUS_BVALID_DET, PMIC_RG_INT_STATUS_BVALID_DET_ADDR,
	 PMIC_RG_INT_STATUS_BVALID_DET_MASK, PMIC_RG_INT_STATUS_BVALID_DET_SHIFT},
	{PMIC_RG_INT_STATUS_RGS_BATON_HV, PMIC_RG_INT_STATUS_RGS_BATON_HV_ADDR,
	 PMIC_RG_INT_STATUS_RGS_BATON_HV_MASK, PMIC_RG_INT_STATUS_RGS_BATON_HV_SHIFT},
	{PMIC_RG_INT_STATUS_VBATON_UNDET, PMIC_RG_INT_STATUS_VBATON_UNDET_ADDR,
	 PMIC_RG_INT_STATUS_VBATON_UNDET_MASK, PMIC_RG_INT_STATUS_VBATON_UNDET_SHIFT},
	{PMIC_RG_INT_STATUS_WATCHDOG, PMIC_RG_INT_STATUS_WATCHDOG_ADDR,
	 PMIC_RG_INT_STATUS_WATCHDOG_MASK, PMIC_RG_INT_STATUS_WATCHDOG_SHIFT},
	{PMIC_RG_INT_STATUS_PCHR_CM_VDEC, PMIC_RG_INT_STATUS_PCHR_CM_VDEC_ADDR,
	 PMIC_RG_INT_STATUS_PCHR_CM_VDEC_MASK, PMIC_RG_INT_STATUS_PCHR_CM_VDEC_SHIFT},
	{PMIC_RG_INT_STATUS_CHRDET, PMIC_RG_INT_STATUS_CHRDET_ADDR,
	 PMIC_RG_INT_STATUS_CHRDET_MASK, PMIC_RG_INT_STATUS_CHRDET_SHIFT},
	{PMIC_RG_INT_STATUS_PCHR_CM_VINC, PMIC_RG_INT_STATUS_PCHR_CM_VINC_ADDR,
	 PMIC_RG_INT_STATUS_PCHR_CM_VINC_MASK, PMIC_RG_INT_STATUS_PCHR_CM_VINC_SHIFT},
	{PMIC_RG_INT_STATUS_FG_BAT_H, PMIC_RG_INT_STATUS_FG_BAT_H_ADDR,
	 PMIC_RG_INT_STATUS_FG_BAT_H_MASK, PMIC_RG_INT_STATUS_FG_BAT_H_SHIFT},
	{PMIC_RG_INT_STATUS_FG_BAT_L, PMIC_RG_INT_STATUS_FG_BAT_L_ADDR,
	 PMIC_RG_INT_STATUS_FG_BAT_L_MASK, PMIC_RG_INT_STATUS_FG_BAT_L_SHIFT},
	{PMIC_RG_INT_STATUS_FG_CUR_H, PMIC_RG_INT_STATUS_FG_CUR_H_ADDR,
	 PMIC_RG_INT_STATUS_FG_CUR_H_MASK, PMIC_RG_INT_STATUS_FG_CUR_H_SHIFT},
	{PMIC_RG_INT_STATUS_FG_CUR_L, PMIC_RG_INT_STATUS_FG_CUR_L_ADDR,
	 PMIC_RG_INT_STATUS_FG_CUR_L_MASK, PMIC_RG_INT_STATUS_FG_CUR_L_SHIFT},
	{PMIC_RG_INT_STATUS_FG_ZCV, PMIC_RG_INT_STATUS_FG_ZCV_ADDR,
	 PMIC_RG_INT_STATUS_FG_ZCV_MASK, PMIC_RG_INT_STATUS_FG_ZCV_SHIFT},
	{PMIC_OC_GEAR_LDO, PMIC_OC_GEAR_LDO_ADDR, PMIC_OC_GEAR_LDO_MASK,
	 PMIC_OC_GEAR_LDO_SHIFT},
	{PMIC_SPK_EN_L, PMIC_SPK_EN_L_ADDR, PMIC_SPK_EN_L_MASK,
	 PMIC_SPK_EN_L_SHIFT},
	{PMIC_SPKMODE_L, PMIC_SPKMODE_L_ADDR, PMIC_SPKMODE_L_MASK,
	 PMIC_SPKMODE_L_SHIFT},
	{PMIC_SPK_TRIM_EN_L, PMIC_SPK_TRIM_EN_L_ADDR, PMIC_SPK_TRIM_EN_L_MASK,
	 PMIC_SPK_TRIM_EN_L_SHIFT},
	{PMIC_SPK_OC_SHDN_DL, PMIC_SPK_OC_SHDN_DL_ADDR, PMIC_SPK_OC_SHDN_DL_MASK,
	 PMIC_SPK_OC_SHDN_DL_SHIFT},
	{PMIC_SPK_THER_SHDN_L_EN, PMIC_SPK_THER_SHDN_L_EN_ADDR,
	 PMIC_SPK_THER_SHDN_L_EN_MASK, PMIC_SPK_THER_SHDN_L_EN_SHIFT},
	{PMIC_SPK_OUT_STAGE_SEL, PMIC_SPK_OUT_STAGE_SEL_ADDR,
	 PMIC_SPK_OUT_STAGE_SEL_MASK, PMIC_SPK_OUT_STAGE_SEL_SHIFT},
	{PMIC_RG_SPK_GAINL, PMIC_RG_SPK_GAINL_ADDR, PMIC_RG_SPK_GAINL_MASK,
	 PMIC_RG_SPK_GAINL_SHIFT},
	{PMIC_DA_SPK_OFFSET_L, PMIC_DA_SPK_OFFSET_L_ADDR, PMIC_DA_SPK_OFFSET_L_MASK,
	 PMIC_DA_SPK_OFFSET_L_SHIFT},
	{PMIC_DA_SPK_LEAD_DGLH_L, PMIC_DA_SPK_LEAD_DGLH_L_ADDR,
	 PMIC_DA_SPK_LEAD_DGLH_L_MASK, PMIC_DA_SPK_LEAD_DGLH_L_SHIFT},
	{PMIC_AD_NI_SPK_LEAD_L, PMIC_AD_NI_SPK_LEAD_L_ADDR,
	 PMIC_AD_NI_SPK_LEAD_L_MASK, PMIC_AD_NI_SPK_LEAD_L_SHIFT},
	{PMIC_SPK_OFFSET_L_OV, PMIC_SPK_OFFSET_L_OV_ADDR, PMIC_SPK_OFFSET_L_OV_MASK,
	 PMIC_SPK_OFFSET_L_OV_SHIFT},
	{PMIC_SPK_OFFSET_L_SW, PMIC_SPK_OFFSET_L_SW_ADDR, PMIC_SPK_OFFSET_L_SW_MASK,
	 PMIC_SPK_OFFSET_L_SW_SHIFT},
	{PMIC_SPK_LEAD_L_SW, PMIC_SPK_LEAD_L_SW_ADDR, PMIC_SPK_LEAD_L_SW_MASK,
	 PMIC_SPK_LEAD_L_SW_SHIFT},
	{PMIC_SPK_OFFSET_L_MODE, PMIC_SPK_OFFSET_L_MODE_ADDR,
	 PMIC_SPK_OFFSET_L_MODE_MASK, PMIC_SPK_OFFSET_L_MODE_SHIFT},
	{PMIC_SPK_TRIM_DONE_L, PMIC_SPK_TRIM_DONE_L_ADDR, PMIC_SPK_TRIM_DONE_L_MASK,
	 PMIC_SPK_TRIM_DONE_L_SHIFT},
	{PMIC_RG_SPK_INTG_RST_L, PMIC_RG_SPK_INTG_RST_L_ADDR,
	 PMIC_RG_SPK_INTG_RST_L_MASK, PMIC_RG_SPK_INTG_RST_L_SHIFT},
	{PMIC_RG_SPK_FORCE_EN_L, PMIC_RG_SPK_FORCE_EN_L_ADDR,
	 PMIC_RG_SPK_FORCE_EN_L_MASK, PMIC_RG_SPK_FORCE_EN_L_SHIFT},
	{PMIC_RG_SPK_SLEW_L, PMIC_RG_SPK_SLEW_L_ADDR, PMIC_RG_SPK_SLEW_L_MASK,
	 PMIC_RG_SPK_SLEW_L_SHIFT},
	{PMIC_RG_SPKAB_OBIAS_L, PMIC_RG_SPKAB_OBIAS_L_ADDR,
	 PMIC_RG_SPKAB_OBIAS_L_MASK, PMIC_RG_SPKAB_OBIAS_L_SHIFT},
	{PMIC_RG_SPKRCV_EN_L, PMIC_RG_SPKRCV_EN_L_ADDR, PMIC_RG_SPKRCV_EN_L_MASK,
	 PMIC_RG_SPKRCV_EN_L_SHIFT},
	{PMIC_RG_SPK_DRC_EN_L, PMIC_RG_SPK_DRC_EN_L_ADDR, PMIC_RG_SPK_DRC_EN_L_MASK,
	 PMIC_RG_SPK_DRC_EN_L_SHIFT},
	{PMIC_RG_SPK_TEST_EN_L, PMIC_RG_SPK_TEST_EN_L_ADDR,
	 PMIC_RG_SPK_TEST_EN_L_MASK, PMIC_RG_SPK_TEST_EN_L_SHIFT},
	{PMIC_RG_SPKAB_OC_EN_L, PMIC_RG_SPKAB_OC_EN_L_ADDR,
	 PMIC_RG_SPKAB_OC_EN_L_MASK, PMIC_RG_SPKAB_OC_EN_L_SHIFT},
	{PMIC_RG_SPK_OC_EN_L, PMIC_RG_SPK_OC_EN_L_ADDR, PMIC_RG_SPK_OC_EN_L_MASK,
	 PMIC_RG_SPK_OC_EN_L_SHIFT},
	{PMIC_SPK_EN_R, PMIC_SPK_EN_R_ADDR, PMIC_SPK_EN_R_MASK,
	 PMIC_SPK_EN_R_SHIFT},
	{PMIC_SPKMODE_R, PMIC_SPKMODE_R_ADDR, PMIC_SPKMODE_R_MASK,
	 PMIC_SPKMODE_R_SHIFT},
	{PMIC_SPK_TRIM_EN_R, PMIC_SPK_TRIM_EN_R_ADDR, PMIC_SPK_TRIM_EN_R_MASK,
	 PMIC_SPK_TRIM_EN_R_SHIFT},
	{PMIC_SPK_OC_SHDN_DR, PMIC_SPK_OC_SHDN_DR_ADDR, PMIC_SPK_OC_SHDN_DR_MASK,
	 PMIC_SPK_OC_SHDN_DR_SHIFT},
	{PMIC_SPK_THER_SHDN_R_EN, PMIC_SPK_THER_SHDN_R_EN_ADDR,
	 PMIC_SPK_THER_SHDN_R_EN_MASK, PMIC_SPK_THER_SHDN_R_EN_SHIFT},
	{PMIC_RG_SPK_GAINR, PMIC_RG_SPK_GAINR_ADDR, PMIC_RG_SPK_GAINR_MASK,
	 PMIC_RG_SPK_GAINR_SHIFT},
	{PMIC_DA_SPK_OFFSET_R, PMIC_DA_SPK_OFFSET_R_ADDR, PMIC_DA_SPK_OFFSET_R_MASK,
	 PMIC_DA_SPK_OFFSET_R_SHIFT},
	{PMIC_DA_SPK_LEAD_DGLH_R, PMIC_DA_SPK_LEAD_DGLH_R_ADDR,
	 PMIC_DA_SPK_LEAD_DGLH_R_MASK, PMIC_DA_SPK_LEAD_DGLH_R_SHIFT},
	{PMIC_NI_SPK_LEAD_R, PMIC_NI_SPK_LEAD_R_ADDR, PMIC_NI_SPK_LEAD_R_MASK,
	 PMIC_NI_SPK_LEAD_R_SHIFT},
	{PMIC_SPK_OFFSET_R_OV, PMIC_SPK_OFFSET_R_OV_ADDR, PMIC_SPK_OFFSET_R_OV_MASK,
	 PMIC_SPK_OFFSET_R_OV_SHIFT},
	{PMIC_SPK_OFFSET_R_SW, PMIC_SPK_OFFSET_R_SW_ADDR, PMIC_SPK_OFFSET_R_SW_MASK,
	 PMIC_SPK_OFFSET_R_SW_SHIFT},
	{PMIC_SPK_LEAD_R_SW, PMIC_SPK_LEAD_R_SW_ADDR, PMIC_SPK_LEAD_R_SW_MASK,
	 PMIC_SPK_LEAD_R_SW_SHIFT},
	{PMIC_SPK_OFFSET_R_MODE, PMIC_SPK_OFFSET_R_MODE_ADDR,
	 PMIC_SPK_OFFSET_R_MODE_MASK, PMIC_SPK_OFFSET_R_MODE_SHIFT},
	{PMIC_SPK_TRIM_DONE_R, PMIC_SPK_TRIM_DONE_R_ADDR, PMIC_SPK_TRIM_DONE_R_MASK,
	 PMIC_SPK_TRIM_DONE_R_SHIFT},
	{PMIC_RG_SPK_INTG_RST_R, PMIC_RG_SPK_INTG_RST_R_ADDR,
	 PMIC_RG_SPK_INTG_RST_R_MASK, PMIC_RG_SPK_INTG_RST_R_SHIFT},
	{PMIC_RG_SPK_FORCE_EN_R, PMIC_RG_SPK_FORCE_EN_R_ADDR,
	 PMIC_RG_SPK_FORCE_EN_R_MASK, PMIC_RG_SPK_FORCE_EN_R_SHIFT},
	{PMIC_RG_SPK_SLEW_R, PMIC_RG_SPK_SLEW_R_ADDR, PMIC_RG_SPK_SLEW_R_MASK,
	 PMIC_RG_SPK_SLEW_R_SHIFT},
	{PMIC_RG_SPKAB_OBIAS_R, PMIC_RG_SPKAB_OBIAS_R_ADDR,
	 PMIC_RG_SPKAB_OBIAS_R_MASK, PMIC_RG_SPKAB_OBIAS_R_SHIFT},
	{PMIC_RG_SPKRCV_EN_R, PMIC_RG_SPKRCV_EN_R_ADDR, PMIC_RG_SPKRCV_EN_R_MASK,
	 PMIC_RG_SPKRCV_EN_R_SHIFT},
	{PMIC_RG_SPK_DRC_EN_R, PMIC_RG_SPK_DRC_EN_R_ADDR, PMIC_RG_SPK_DRC_EN_R_MASK,
	 PMIC_RG_SPK_DRC_EN_R_SHIFT},
	{PMIC_RG_SPK_TEST_EN_R, PMIC_RG_SPK_TEST_EN_R_ADDR,
	 PMIC_RG_SPK_TEST_EN_R_MASK, PMIC_RG_SPK_TEST_EN_R_SHIFT},
	{PMIC_RG_SPKAB_OC_EN_R, PMIC_RG_SPKAB_OC_EN_R_ADDR,
	 PMIC_RG_SPKAB_OC_EN_R_MASK, PMIC_RG_SPKAB_OC_EN_R_SHIFT},
	{PMIC_RG_SPK_OC_EN_R, PMIC_RG_SPK_OC_EN_R_ADDR, PMIC_RG_SPK_OC_EN_R_MASK,
	 PMIC_RG_SPK_OC_EN_R_SHIFT},
	{PMIC_RG_SPKPGA_GAINR, PMIC_RG_SPKPGA_GAINR_ADDR, PMIC_RG_SPKPGA_GAINR_MASK,
	 PMIC_RG_SPKPGA_GAINR_SHIFT},
	{PMIC_SPK_TRIM_WND, PMIC_SPK_TRIM_WND_ADDR, PMIC_SPK_TRIM_WND_MASK,
	 PMIC_SPK_TRIM_WND_SHIFT},
	{PMIC_SPK_TRIM_THD, PMIC_SPK_TRIM_THD_ADDR, PMIC_SPK_TRIM_THD_MASK,
	 PMIC_SPK_TRIM_THD_SHIFT},
	{PMIC_SPK_OC_WND, PMIC_SPK_OC_WND_ADDR, PMIC_SPK_OC_WND_MASK,
	 PMIC_SPK_OC_WND_SHIFT},
	{PMIC_SPK_OC_THD, PMIC_SPK_OC_THD_ADDR, PMIC_SPK_OC_THD_MASK,
	 PMIC_SPK_OC_THD_SHIFT},
	{PMIC_SPK_D_OC_R_DEG, PMIC_SPK_D_OC_R_DEG_ADDR, PMIC_SPK_D_OC_R_DEG_MASK,
	 PMIC_SPK_D_OC_R_DEG_SHIFT},
	{PMIC_SPK_AB_OC_R_DEG, PMIC_SPK_AB_OC_R_DEG_ADDR, PMIC_SPK_AB_OC_R_DEG_MASK,
	 PMIC_SPK_AB_OC_R_DEG_SHIFT},
	{PMIC_SPK_D_OC_L_DEG, PMIC_SPK_D_OC_L_DEG_ADDR, PMIC_SPK_D_OC_L_DEG_MASK,
	 PMIC_SPK_D_OC_L_DEG_SHIFT},
	{PMIC_SPK_AB_OC_L_DEG, PMIC_SPK_AB_OC_L_DEG_ADDR, PMIC_SPK_AB_OC_L_DEG_MASK,
	 PMIC_SPK_AB_OC_L_DEG_SHIFT},
	{PMIC_SPK_TD1, PMIC_SPK_TD1_ADDR, PMIC_SPK_TD1_MASK,
	 PMIC_SPK_TD1_SHIFT},
	{PMIC_SPK_TD2, PMIC_SPK_TD2_ADDR, PMIC_SPK_TD2_MASK,
	 PMIC_SPK_TD2_SHIFT},
	{PMIC_SPK_TD3, PMIC_SPK_TD3_ADDR, PMIC_SPK_TD3_MASK,
	 PMIC_SPK_TD3_SHIFT},
	{PMIC_SPK_TRIM_DIV, PMIC_SPK_TRIM_DIV_ADDR, PMIC_SPK_TRIM_DIV_MASK,
	 PMIC_SPK_TRIM_DIV_SHIFT},
	{PMIC_RG_BTL_SET, PMIC_RG_BTL_SET_ADDR, PMIC_RG_BTL_SET_MASK,
	 PMIC_RG_BTL_SET_SHIFT},
	{PMIC_RG_SPK_IBIAS_SEL, PMIC_RG_SPK_IBIAS_SEL_ADDR,
	 PMIC_RG_SPK_IBIAS_SEL_MASK, PMIC_RG_SPK_IBIAS_SEL_SHIFT},
	{PMIC_RG_SPK_CCODE, PMIC_RG_SPK_CCODE_ADDR, PMIC_RG_SPK_CCODE_MASK,
	 PMIC_RG_SPK_CCODE_SHIFT},
	{PMIC_RG_SPK_EN_VIEW_VCM, PMIC_RG_SPK_EN_VIEW_VCM_ADDR,
	 PMIC_RG_SPK_EN_VIEW_VCM_MASK, PMIC_RG_SPK_EN_VIEW_VCM_SHIFT},
	{PMIC_RG_SPK_EN_VIEW_CLK, PMIC_RG_SPK_EN_VIEW_CLK_ADDR,
	 PMIC_RG_SPK_EN_VIEW_CLK_MASK, PMIC_RG_SPK_EN_VIEW_CLK_SHIFT},
	{PMIC_RG_SPK_VCM_SEL, PMIC_RG_SPK_VCM_SEL_ADDR, PMIC_RG_SPK_VCM_SEL_MASK,
	 PMIC_RG_SPK_VCM_SEL_SHIFT},
	{PMIC_RG_SPK_VCM_IBSEL, PMIC_RG_SPK_VCM_IBSEL_ADDR,
	 PMIC_RG_SPK_VCM_IBSEL_MASK, PMIC_RG_SPK_VCM_IBSEL_SHIFT},
	{PMIC_RG_SPK_FBRC_EN, PMIC_RG_SPK_FBRC_EN_ADDR, PMIC_RG_SPK_FBRC_EN_MASK,
	 PMIC_RG_SPK_FBRC_EN_SHIFT},
	{PMIC_RG_SPKAB_OVDRV, PMIC_RG_SPKAB_OVDRV_ADDR, PMIC_RG_SPKAB_OVDRV_MASK,
	 PMIC_RG_SPKAB_OVDRV_SHIFT},
	{PMIC_RG_SPK_OCTH_D, PMIC_RG_SPK_OCTH_D_ADDR, PMIC_RG_SPK_OCTH_D_MASK,
	 PMIC_RG_SPK_OCTH_D_SHIFT},
	{PMIC_RG_SPKPGA_GAINL, PMIC_RG_SPKPGA_GAINL_ADDR, PMIC_RG_SPKPGA_GAINL_MASK,
	 PMIC_RG_SPKPGA_GAINL_SHIFT},
	{PMIC_SPK_RSV0, PMIC_SPK_RSV0_ADDR, PMIC_SPK_RSV0_MASK,
	 PMIC_SPK_RSV0_SHIFT},
	{PMIC_SPK_VCM_FAST_EN, PMIC_SPK_VCM_FAST_EN_ADDR, PMIC_SPK_VCM_FAST_EN_MASK,
	 PMIC_SPK_VCM_FAST_EN_SHIFT},
	{PMIC_SPK_TEST_MODE0, PMIC_SPK_TEST_MODE0_ADDR, PMIC_SPK_TEST_MODE0_MASK,
	 PMIC_SPK_TEST_MODE0_SHIFT},
	{PMIC_SPK_TEST_MODE1, PMIC_SPK_TEST_MODE1_ADDR, PMIC_SPK_TEST_MODE1_MASK,
	 PMIC_SPK_TEST_MODE1_SHIFT},
	{PMIC_SPK_TD_WAIT, PMIC_SPK_TD_WAIT_ADDR, PMIC_SPK_TD_WAIT_MASK,
	 PMIC_SPK_TD_WAIT_SHIFT},
	{PMIC_SPK_TD_DONE, PMIC_SPK_TD_DONE_ADDR, PMIC_SPK_TD_DONE_MASK,
	 PMIC_SPK_TD_DONE_SHIFT},
	{PMIC_SPK_EN_MODE, PMIC_SPK_EN_MODE_ADDR, PMIC_SPK_EN_MODE_MASK,
	 PMIC_SPK_EN_MODE_SHIFT},
	{PMIC_SPK_VCM_FAST_SW, PMIC_SPK_VCM_FAST_SW_ADDR, PMIC_SPK_VCM_FAST_SW_MASK,
	 PMIC_SPK_VCM_FAST_SW_SHIFT},
	{PMIC_SPK_RST_R_SW, PMIC_SPK_RST_R_SW_ADDR, PMIC_SPK_RST_R_SW_MASK,
	 PMIC_SPK_RST_R_SW_SHIFT},
	{PMIC_SPK_RST_L_SW, PMIC_SPK_RST_L_SW_ADDR, PMIC_SPK_RST_L_SW_MASK,
	 PMIC_SPK_RST_L_SW_SHIFT},
	{PMIC_SPKMODE_R_SW, PMIC_SPKMODE_R_SW_ADDR, PMIC_SPKMODE_R_SW_MASK,
	 PMIC_SPKMODE_R_SW_SHIFT},
	{PMIC_SPKMODE_L_SW, PMIC_SPKMODE_L_SW_ADDR, PMIC_SPKMODE_L_SW_MASK,
	 PMIC_SPKMODE_L_SW_SHIFT},
	{PMIC_SPK_DEPOP_EN_R_SW, PMIC_SPK_DEPOP_EN_R_SW_ADDR,
	 PMIC_SPK_DEPOP_EN_R_SW_MASK, PMIC_SPK_DEPOP_EN_R_SW_SHIFT},
	{PMIC_SPK_DEPOP_EN_L_SW, PMIC_SPK_DEPOP_EN_L_SW_ADDR,
	 PMIC_SPK_DEPOP_EN_L_SW_MASK, PMIC_SPK_DEPOP_EN_L_SW_SHIFT},
	{PMIC_SPK_EN_R_SW, PMIC_SPK_EN_R_SW_ADDR, PMIC_SPK_EN_R_SW_MASK,
	 PMIC_SPK_EN_R_SW_SHIFT},
	{PMIC_SPK_EN_L_SW, PMIC_SPK_EN_L_SW_ADDR, PMIC_SPK_EN_L_SW_MASK,
	 PMIC_SPK_EN_L_SW_SHIFT},
	{PMIC_SPK_OUTSTG_EN_R_SW, PMIC_SPK_OUTSTG_EN_R_SW_ADDR,
	 PMIC_SPK_OUTSTG_EN_R_SW_MASK, PMIC_SPK_OUTSTG_EN_R_SW_SHIFT},
	{PMIC_SPK_OUTSTG_EN_L_SW, PMIC_SPK_OUTSTG_EN_L_SW_ADDR,
	 PMIC_SPK_OUTSTG_EN_L_SW_MASK, PMIC_SPK_OUTSTG_EN_L_SW_SHIFT},
	{PMIC_SPK_TRIM_EN_R_SW, PMIC_SPK_TRIM_EN_R_SW_ADDR,
	 PMIC_SPK_TRIM_EN_R_SW_MASK, PMIC_SPK_TRIM_EN_R_SW_SHIFT},
	{PMIC_SPK_TRIM_EN_L_SW, PMIC_SPK_TRIM_EN_L_SW_ADDR,
	 PMIC_SPK_TRIM_EN_L_SW_MASK, PMIC_SPK_TRIM_EN_L_SW_SHIFT},
	{PMIC_SPK_TRIM_STOP_R_SW, PMIC_SPK_TRIM_STOP_R_SW_ADDR,
	 PMIC_SPK_TRIM_STOP_R_SW_MASK, PMIC_SPK_TRIM_STOP_R_SW_SHIFT},
	{PMIC_SPK_TRIM_STOP_L_SW, PMIC_SPK_TRIM_STOP_L_SW_ADDR,
	 PMIC_SPK_TRIM_STOP_L_SW_MASK, PMIC_SPK_TRIM_STOP_L_SW_SHIFT},
	{PMIC_RG_SPK_ISENSE_TEST_EN, PMIC_RG_SPK_ISENSE_TEST_EN_ADDR,
	 PMIC_RG_SPK_ISENSE_TEST_EN_MASK, PMIC_RG_SPK_ISENSE_TEST_EN_SHIFT},
	{PMIC_RG_SPK_ISENSE_REFSEL, PMIC_RG_SPK_ISENSE_REFSEL_ADDR,
	 PMIC_RG_SPK_ISENSE_REFSEL_MASK, PMIC_RG_SPK_ISENSE_REFSEL_SHIFT},
	{PMIC_RG_SPK_ISENSE_GAINSEL, PMIC_RG_SPK_ISENSE_GAINSEL_ADDR,
	 PMIC_RG_SPK_ISENSE_GAINSEL_MASK, PMIC_RG_SPK_ISENSE_GAINSEL_SHIFT},
	{PMIC_RG_SPK_ISENSE_PDRESET, PMIC_RG_SPK_ISENSE_PDRESET_ADDR,
	 PMIC_RG_SPK_ISENSE_PDRESET_MASK, PMIC_RG_SPK_ISENSE_PDRESET_SHIFT},
	{PMIC_RG_SPK_ISENSE_EN, PMIC_RG_SPK_ISENSE_EN_ADDR,
	 PMIC_RG_SPK_ISENSE_EN_MASK, PMIC_RG_SPK_ISENSE_EN_SHIFT},
	{PMIC_RG_SPK_RSV1, PMIC_RG_SPK_RSV1_ADDR, PMIC_RG_SPK_RSV1_MASK,
	 PMIC_RG_SPK_RSV1_SHIFT},
	{PMIC_RG_SPK_RSV0, PMIC_RG_SPK_RSV0_ADDR, PMIC_RG_SPK_RSV0_MASK,
	 PMIC_RG_SPK_RSV0_SHIFT},
	{PMIC_RG_SPK_ABD_VOLSEN_GAIN, PMIC_RG_SPK_ABD_VOLSEN_GAIN_ADDR,
	 PMIC_RG_SPK_ABD_VOLSEN_GAIN_MASK, PMIC_RG_SPK_ABD_VOLSEN_GAIN_SHIFT},
	{PMIC_RG_SPK_ABD_VOLSEN_EN, PMIC_RG_SPK_ABD_VOLSEN_EN_ADDR,
	 PMIC_RG_SPK_ABD_VOLSEN_EN_MASK, PMIC_RG_SPK_ABD_VOLSEN_EN_SHIFT},
	{PMIC_RG_SPK_ABD_CURSEN_SEL, PMIC_RG_SPK_ABD_CURSEN_SEL_ADDR,
	 PMIC_RG_SPK_ABD_CURSEN_SEL_MASK, PMIC_RG_SPK_ABD_CURSEN_SEL_SHIFT},
	{PMIC_RG_SPK_RSV2, PMIC_RG_SPK_RSV2_ADDR, PMIC_RG_SPK_RSV2_MASK,
	 PMIC_RG_SPK_RSV2_SHIFT},
	{PMIC_RG_SPK_TRIM2, PMIC_RG_SPK_TRIM2_ADDR, PMIC_RG_SPK_TRIM2_MASK,
	 PMIC_RG_SPK_TRIM2_SHIFT},
	{PMIC_RG_SPK_TRIM1, PMIC_RG_SPK_TRIM1_ADDR, PMIC_RG_SPK_TRIM1_MASK,
	 PMIC_RG_SPK_TRIM1_SHIFT},
	{PMIC_RG_SPK_D_CURSEN_RSETSEL, PMIC_RG_SPK_D_CURSEN_RSETSEL_ADDR,
	 PMIC_RG_SPK_D_CURSEN_RSETSEL_MASK, PMIC_RG_SPK_D_CURSEN_RSETSEL_SHIFT},
	{PMIC_RG_SPK_D_CURSEN_GAIN, PMIC_RG_SPK_D_CURSEN_GAIN_ADDR,
	 PMIC_RG_SPK_D_CURSEN_GAIN_MASK, PMIC_RG_SPK_D_CURSEN_GAIN_SHIFT},
	{PMIC_RG_SPK_D_CURSEN_EN, PMIC_RG_SPK_D_CURSEN_EN_ADDR,
	 PMIC_RG_SPK_D_CURSEN_EN_MASK, PMIC_RG_SPK_D_CURSEN_EN_SHIFT},
	{PMIC_RG_SPK_AB_CURSEN_RSETSEL, PMIC_RG_SPK_AB_CURSEN_RSETSEL_ADDR,
	 PMIC_RG_SPK_AB_CURSEN_RSETSEL_MASK, PMIC_RG_SPK_AB_CURSEN_RSETSEL_SHIFT},
	{PMIC_RG_SPK_AB_CURSEN_GAIN, PMIC_RG_SPK_AB_CURSEN_GAIN_ADDR,
	 PMIC_RG_SPK_AB_CURSEN_GAIN_MASK, PMIC_RG_SPK_AB_CURSEN_GAIN_SHIFT},
	{PMIC_RG_SPK_AB_CURSEN_EN, PMIC_RG_SPK_AB_CURSEN_EN_ADDR,
	 PMIC_RG_SPK_AB_CURSEN_EN_MASK, PMIC_RG_SPK_AB_CURSEN_EN_SHIFT},
	{PMIC_RG_SPKPGA_GAIN, PMIC_RG_SPKPGA_GAIN_ADDR, PMIC_RG_SPKPGA_GAIN_MASK,
	 PMIC_RG_SPKPGA_GAIN_SHIFT},
	{PMIC_RG_SPK_RSV, PMIC_RG_SPK_RSV_ADDR, PMIC_RG_SPK_RSV_MASK,
	 PMIC_RG_SPK_RSV_SHIFT},
	{PMIC_RG_ISENSE_PD_RESET, PMIC_RG_ISENSE_PD_RESET_ADDR,
	 PMIC_RG_ISENSE_PD_RESET_MASK, PMIC_RG_ISENSE_PD_RESET_SHIFT},
	{PMIC_RG_AUDIVLPWRUP_VAUDP12, PMIC_RG_AUDIVLPWRUP_VAUDP12_ADDR,
	 PMIC_RG_AUDIVLPWRUP_VAUDP12_MASK, PMIC_RG_AUDIVLPWRUP_VAUDP12_SHIFT},
	{PMIC_RG_AUDIVLSTARTUP_VAUDP12, PMIC_RG_AUDIVLSTARTUP_VAUDP12_ADDR,
	 PMIC_RG_AUDIVLSTARTUP_VAUDP12_MASK, PMIC_RG_AUDIVLSTARTUP_VAUDP12_SHIFT},
	{PMIC_RG_AUDIVLMUXSEL_VAUDP12, PMIC_RG_AUDIVLMUXSEL_VAUDP12_ADDR,
	 PMIC_RG_AUDIVLMUXSEL_VAUDP12_MASK, PMIC_RG_AUDIVLMUXSEL_VAUDP12_SHIFT},
	{PMIC_RG_AUDIVLMUTE_VAUDP12, PMIC_RG_AUDIVLMUTE_VAUDP12_ADDR,
	 PMIC_RG_AUDIVLMUTE_VAUDP12_MASK, PMIC_RG_AUDIVLMUTE_VAUDP12_SHIFT},
	{PMIC_FQMTR_TCKSEL, PMIC_FQMTR_TCKSEL_ADDR, PMIC_FQMTR_TCKSEL_MASK,
	 PMIC_FQMTR_TCKSEL_SHIFT},
	{PMIC_FQMTR_BUSY, PMIC_FQMTR_BUSY_ADDR, PMIC_FQMTR_BUSY_MASK,
	 PMIC_FQMTR_BUSY_SHIFT},
	{PMIC_FQMTR_DCXO26M_EN, PMIC_FQMTR_DCXO26M_EN_ADDR,
	 PMIC_FQMTR_DCXO26M_EN_MASK, PMIC_FQMTR_DCXO26M_EN_SHIFT},
	{PMIC_FQMTR_EN, PMIC_FQMTR_EN_ADDR, PMIC_FQMTR_EN_MASK,
	 PMIC_FQMTR_EN_SHIFT},
	{PMIC_FQMTR_WINSET, PMIC_FQMTR_WINSET_ADDR, PMIC_FQMTR_WINSET_MASK,
	 PMIC_FQMTR_WINSET_SHIFT},
	{PMIC_FQMTR_DATA, PMIC_FQMTR_DATA_ADDR, PMIC_FQMTR_DATA_MASK,
	 PMIC_FQMTR_DATA_SHIFT},
	{PMIC_RG_TRIM_EN, PMIC_RG_TRIM_EN_ADDR, PMIC_RG_TRIM_EN_MASK,
	 PMIC_RG_TRIM_EN_SHIFT},
	{PMIC_RG_TRIM_SEL, PMIC_RG_TRIM_SEL_ADDR, PMIC_RG_TRIM_SEL_MASK,
	 PMIC_RG_TRIM_SEL_SHIFT},
	{PMIC_RG_ISINKS_RSV, PMIC_RG_ISINKS_RSV_ADDR, PMIC_RG_ISINKS_RSV_MASK,
	 PMIC_RG_ISINKS_RSV_SHIFT},
	{PMIC_RG_ISINK0_DOUBLE_EN, PMIC_RG_ISINK0_DOUBLE_EN_ADDR,
	 PMIC_RG_ISINK0_DOUBLE_EN_MASK, PMIC_RG_ISINK0_DOUBLE_EN_SHIFT},
	{PMIC_RG_ISINK1_DOUBLE_EN, PMIC_RG_ISINK1_DOUBLE_EN_ADDR,
	 PMIC_RG_ISINK1_DOUBLE_EN_MASK, PMIC_RG_ISINK1_DOUBLE_EN_SHIFT},
	{PMIC_RG_ISINK2_DOUBLE_EN, PMIC_RG_ISINK2_DOUBLE_EN_ADDR,
	 PMIC_RG_ISINK2_DOUBLE_EN_MASK, PMIC_RG_ISINK2_DOUBLE_EN_SHIFT},
	{PMIC_RG_ISINK3_DOUBLE_EN, PMIC_RG_ISINK3_DOUBLE_EN_ADDR,
	 PMIC_RG_ISINK3_DOUBLE_EN_MASK, PMIC_RG_ISINK3_DOUBLE_EN_SHIFT},
	{PMIC_ISINK_DIM0_FSEL, PMIC_ISINK_DIM0_FSEL_ADDR, PMIC_ISINK_DIM0_FSEL_MASK,
	 PMIC_ISINK_DIM0_FSEL_SHIFT},
	{PMIC_ISINK0_RSV1, PMIC_ISINK0_RSV1_ADDR, PMIC_ISINK0_RSV1_MASK,
	 PMIC_ISINK0_RSV1_SHIFT},
	{PMIC_ISINK0_RSV0, PMIC_ISINK0_RSV0_ADDR, PMIC_ISINK0_RSV0_MASK,
	 PMIC_ISINK0_RSV0_SHIFT},
	{PMIC_ISINK_DIM0_DUTY, PMIC_ISINK_DIM0_DUTY_ADDR, PMIC_ISINK_DIM0_DUTY_MASK,
	 PMIC_ISINK_DIM0_DUTY_SHIFT},
	{PMIC_ISINK_CH0_STEP, PMIC_ISINK_CH0_STEP_ADDR, PMIC_ISINK_CH0_STEP_MASK,
	 PMIC_ISINK_CH0_STEP_SHIFT},
	{PMIC_ISINK_BREATH0_TF2_SEL, PMIC_ISINK_BREATH0_TF2_SEL_ADDR,
	 PMIC_ISINK_BREATH0_TF2_SEL_MASK, PMIC_ISINK_BREATH0_TF2_SEL_SHIFT},
	{PMIC_ISINK_BREATH0_TF1_SEL, PMIC_ISINK_BREATH0_TF1_SEL_ADDR,
	 PMIC_ISINK_BREATH0_TF1_SEL_MASK, PMIC_ISINK_BREATH0_TF1_SEL_SHIFT},
	{PMIC_ISINK_BREATH0_TR2_SEL, PMIC_ISINK_BREATH0_TR2_SEL_ADDR,
	 PMIC_ISINK_BREATH0_TR2_SEL_MASK, PMIC_ISINK_BREATH0_TR2_SEL_SHIFT},
	{PMIC_ISINK_BREATH0_TR1_SEL, PMIC_ISINK_BREATH0_TR1_SEL_ADDR,
	 PMIC_ISINK_BREATH0_TR1_SEL_MASK, PMIC_ISINK_BREATH0_TR1_SEL_SHIFT},
	{PMIC_ISINK_BREATH0_TOFF_SEL, PMIC_ISINK_BREATH0_TOFF_SEL_ADDR,
	 PMIC_ISINK_BREATH0_TOFF_SEL_MASK, PMIC_ISINK_BREATH0_TOFF_SEL_SHIFT},
	{PMIC_ISINK_BREATH0_TON_SEL, PMIC_ISINK_BREATH0_TON_SEL_ADDR,
	 PMIC_ISINK_BREATH0_TON_SEL_MASK, PMIC_ISINK_BREATH0_TON_SEL_SHIFT},
	{PMIC_ISINK_DIM1_FSEL, PMIC_ISINK_DIM1_FSEL_ADDR, PMIC_ISINK_DIM1_FSEL_MASK,
	 PMIC_ISINK_DIM1_FSEL_SHIFT},
	{PMIC_ISINK1_RSV1, PMIC_ISINK1_RSV1_ADDR, PMIC_ISINK1_RSV1_MASK,
	 PMIC_ISINK1_RSV1_SHIFT},
	{PMIC_ISINK1_RSV0, PMIC_ISINK1_RSV0_ADDR, PMIC_ISINK1_RSV0_MASK,
	 PMIC_ISINK1_RSV0_SHIFT},
	{PMIC_ISINK_DIM1_DUTY, PMIC_ISINK_DIM1_DUTY_ADDR, PMIC_ISINK_DIM1_DUTY_MASK,
	 PMIC_ISINK_DIM1_DUTY_SHIFT},
	{PMIC_ISINK_CH1_STEP, PMIC_ISINK_CH1_STEP_ADDR, PMIC_ISINK_CH1_STEP_MASK,
	 PMIC_ISINK_CH1_STEP_SHIFT},
	{PMIC_ISINK_BREATH1_TF2_SEL, PMIC_ISINK_BREATH1_TF2_SEL_ADDR,
	 PMIC_ISINK_BREATH1_TF2_SEL_MASK, PMIC_ISINK_BREATH1_TF2_SEL_SHIFT},
	{PMIC_ISINK_BREATH1_TF1_SEL, PMIC_ISINK_BREATH1_TF1_SEL_ADDR,
	 PMIC_ISINK_BREATH1_TF1_SEL_MASK, PMIC_ISINK_BREATH1_TF1_SEL_SHIFT},
	{PMIC_ISINK_BREATH1_TR2_SEL, PMIC_ISINK_BREATH1_TR2_SEL_ADDR,
	 PMIC_ISINK_BREATH1_TR2_SEL_MASK, PMIC_ISINK_BREATH1_TR2_SEL_SHIFT},
	{PMIC_ISINK_BREATH1_TR1_SEL, PMIC_ISINK_BREATH1_TR1_SEL_ADDR,
	 PMIC_ISINK_BREATH1_TR1_SEL_MASK, PMIC_ISINK_BREATH1_TR1_SEL_SHIFT},
	{PMIC_ISINK_BREATH1_TOFF_SEL, PMIC_ISINK_BREATH1_TOFF_SEL_ADDR,
	 PMIC_ISINK_BREATH1_TOFF_SEL_MASK, PMIC_ISINK_BREATH1_TOFF_SEL_SHIFT},
	{PMIC_ISINK_BREATH1_TON_SEL, PMIC_ISINK_BREATH1_TON_SEL_ADDR,
	 PMIC_ISINK_BREATH1_TON_SEL_MASK, PMIC_ISINK_BREATH1_TON_SEL_SHIFT},
	{PMIC_AD_NI_ISINK3_STATUS, PMIC_AD_NI_ISINK3_STATUS_ADDR,
	 PMIC_AD_NI_ISINK3_STATUS_MASK, PMIC_AD_NI_ISINK3_STATUS_SHIFT},
	{PMIC_AD_NI_ISINK2_STATUS, PMIC_AD_NI_ISINK2_STATUS_ADDR,
	 PMIC_AD_NI_ISINK2_STATUS_MASK, PMIC_AD_NI_ISINK2_STATUS_SHIFT},
	{PMIC_AD_NI_ISINK1_STATUS, PMIC_AD_NI_ISINK1_STATUS_ADDR,
	 PMIC_AD_NI_ISINK1_STATUS_MASK, PMIC_AD_NI_ISINK1_STATUS_SHIFT},
	{PMIC_AD_NI_ISINK0_STATUS, PMIC_AD_NI_ISINK0_STATUS_ADDR,
	 PMIC_AD_NI_ISINK0_STATUS_MASK, PMIC_AD_NI_ISINK0_STATUS_SHIFT},
	{PMIC_ISINK_PHASE0_DLY_EN, PMIC_ISINK_PHASE0_DLY_EN_ADDR,
	 PMIC_ISINK_PHASE0_DLY_EN_MASK, PMIC_ISINK_PHASE0_DLY_EN_SHIFT},
	{PMIC_ISINK_PHASE1_DLY_EN, PMIC_ISINK_PHASE1_DLY_EN_ADDR,
	 PMIC_ISINK_PHASE1_DLY_EN_MASK, PMIC_ISINK_PHASE1_DLY_EN_SHIFT},
	{PMIC_ISINK_PHASE_DLY_TC, PMIC_ISINK_PHASE_DLY_TC_ADDR,
	 PMIC_ISINK_PHASE_DLY_TC_MASK, PMIC_ISINK_PHASE_DLY_TC_SHIFT},
	{PMIC_ISINK_CHOP0_SW, PMIC_ISINK_CHOP0_SW_ADDR, PMIC_ISINK_CHOP0_SW_MASK,
	 PMIC_ISINK_CHOP0_SW_SHIFT},
	{PMIC_ISINK_CHOP1_SW, PMIC_ISINK_CHOP1_SW_ADDR, PMIC_ISINK_CHOP1_SW_MASK,
	 PMIC_ISINK_CHOP1_SW_SHIFT},
	{PMIC_ISINK_SFSTR1_EN, PMIC_ISINK_SFSTR1_EN_ADDR, PMIC_ISINK_SFSTR1_EN_MASK,
	 PMIC_ISINK_SFSTR1_EN_SHIFT},
	{PMIC_ISINK_SFSTR1_TC, PMIC_ISINK_SFSTR1_TC_ADDR, PMIC_ISINK_SFSTR1_TC_MASK,
	 PMIC_ISINK_SFSTR1_TC_SHIFT},
	{PMIC_ISINK_SFSTR0_EN, PMIC_ISINK_SFSTR0_EN_ADDR, PMIC_ISINK_SFSTR0_EN_MASK,
	 PMIC_ISINK_SFSTR0_EN_SHIFT},
	{PMIC_ISINK_SFSTR0_TC, PMIC_ISINK_SFSTR0_TC_ADDR, PMIC_ISINK_SFSTR0_TC_MASK,
	 PMIC_ISINK_SFSTR0_TC_SHIFT},
	{PMIC_ISINK_CH0_EN, PMIC_ISINK_CH0_EN_ADDR, PMIC_ISINK_CH0_EN_MASK,
	 PMIC_ISINK_CH0_EN_SHIFT},
	{PMIC_ISINK_CH1_EN, PMIC_ISINK_CH1_EN_ADDR, PMIC_ISINK_CH1_EN_MASK,
	 PMIC_ISINK_CH1_EN_SHIFT},
	{PMIC_ISINK_CHOP0_EN, PMIC_ISINK_CHOP0_EN_ADDR, PMIC_ISINK_CHOP0_EN_MASK,
	 PMIC_ISINK_CHOP0_EN_SHIFT},
	{PMIC_ISINK_CHOP1_EN, PMIC_ISINK_CHOP1_EN_ADDR, PMIC_ISINK_CHOP1_EN_MASK,
	 PMIC_ISINK_CHOP1_EN_SHIFT},
	{PMIC_ISINK_CH0_BIAS_EN, PMIC_ISINK_CH0_BIAS_EN_ADDR,
	 PMIC_ISINK_CH0_BIAS_EN_MASK, PMIC_ISINK_CH0_BIAS_EN_SHIFT},
	{PMIC_ISINK_CH1_BIAS_EN, PMIC_ISINK_CH1_BIAS_EN_ADDR,
	 PMIC_ISINK_CH1_BIAS_EN_MASK, PMIC_ISINK_CH1_BIAS_EN_SHIFT},
	{PMIC_ISINK_RSV, PMIC_ISINK_RSV_ADDR, PMIC_ISINK_RSV_MASK,
	 PMIC_ISINK_RSV_SHIFT},
	{PMIC_ISINK_CH1_MODE, PMIC_ISINK_CH1_MODE_ADDR, PMIC_ISINK_CH1_MODE_MASK,
	 PMIC_ISINK_CH1_MODE_SHIFT},
	{PMIC_ISINK_CH0_MODE, PMIC_ISINK_CH0_MODE_ADDR, PMIC_ISINK_CH0_MODE_MASK,
	 PMIC_ISINK_CH0_MODE_SHIFT},
	{PMIC_DA_QI_ISINKS_CH3_STEP, PMIC_DA_QI_ISINKS_CH3_STEP_ADDR,
	 PMIC_DA_QI_ISINKS_CH3_STEP_MASK, PMIC_DA_QI_ISINKS_CH3_STEP_SHIFT},
	{PMIC_DA_QI_ISINKS_CH2_STEP, PMIC_DA_QI_ISINKS_CH2_STEP_ADDR,
	 PMIC_DA_QI_ISINKS_CH2_STEP_MASK, PMIC_DA_QI_ISINKS_CH2_STEP_SHIFT},
	{PMIC_DA_QI_ISINKS_CH1_STEP, PMIC_DA_QI_ISINKS_CH1_STEP_ADDR,
	 PMIC_DA_QI_ISINKS_CH1_STEP_MASK, PMIC_DA_QI_ISINKS_CH1_STEP_SHIFT},
	{PMIC_DA_QI_ISINKS_CH0_STEP, PMIC_DA_QI_ISINKS_CH0_STEP_ADDR,
	 PMIC_DA_QI_ISINKS_CH0_STEP_MASK, PMIC_DA_QI_ISINKS_CH0_STEP_SHIFT},
	{PMIC_ISINK2_RSV1, PMIC_ISINK2_RSV1_ADDR, PMIC_ISINK2_RSV1_MASK,
	 PMIC_ISINK2_RSV1_SHIFT},
	{PMIC_ISINK2_RSV0, PMIC_ISINK2_RSV0_ADDR, PMIC_ISINK2_RSV0_MASK,
	 PMIC_ISINK2_RSV0_SHIFT},
	{PMIC_ISINK_CH2_STEP, PMIC_ISINK_CH2_STEP_ADDR, PMIC_ISINK_CH2_STEP_MASK,
	 PMIC_ISINK_CH2_STEP_SHIFT},
	{PMIC_ISINK3_RSV1, PMIC_ISINK3_RSV1_ADDR, PMIC_ISINK3_RSV1_MASK,
	 PMIC_ISINK3_RSV1_SHIFT},
	{PMIC_ISINK3_RSV0, PMIC_ISINK3_RSV0_ADDR, PMIC_ISINK3_RSV0_MASK,
	 PMIC_ISINK3_RSV0_SHIFT},
	{PMIC_ISINK_CH3_STEP, PMIC_ISINK_CH3_STEP_ADDR, PMIC_ISINK_CH3_STEP_MASK,
	 PMIC_ISINK_CH3_STEP_SHIFT},
	{PMIC_ISINK_CHOP3_SW, PMIC_ISINK_CHOP3_SW_ADDR, PMIC_ISINK_CHOP3_SW_MASK,
	 PMIC_ISINK_CHOP3_SW_SHIFT},
	{PMIC_ISINK_CHOP2_SW, PMIC_ISINK_CHOP2_SW_ADDR, PMIC_ISINK_CHOP2_SW_MASK,
	 PMIC_ISINK_CHOP2_SW_SHIFT},
	{PMIC_ISINK_CH3_EN, PMIC_ISINK_CH3_EN_ADDR, PMIC_ISINK_CH3_EN_MASK,
	 PMIC_ISINK_CH3_EN_SHIFT},
	{PMIC_ISINK_CH2_EN, PMIC_ISINK_CH2_EN_ADDR, PMIC_ISINK_CH2_EN_MASK,
	 PMIC_ISINK_CH2_EN_SHIFT},
	{PMIC_ISINK_CHOP3_EN, PMIC_ISINK_CHOP3_EN_ADDR, PMIC_ISINK_CHOP3_EN_MASK,
	 PMIC_ISINK_CHOP3_EN_SHIFT},
	{PMIC_ISINK_CHOP2_EN, PMIC_ISINK_CHOP2_EN_ADDR, PMIC_ISINK_CHOP2_EN_MASK,
	 PMIC_ISINK_CHOP2_EN_SHIFT},
	{PMIC_ISINK_CH3_BIAS_EN, PMIC_ISINK_CH3_BIAS_EN_ADDR,
	 PMIC_ISINK_CH3_BIAS_EN_MASK, PMIC_ISINK_CH3_BIAS_EN_SHIFT},
	{PMIC_ISINK_CH2_BIAS_EN, PMIC_ISINK_CH2_BIAS_EN_ADDR,
	 PMIC_ISINK_CH2_BIAS_EN_MASK, PMIC_ISINK_CH2_BIAS_EN_SHIFT},
	{PMIC_CHRIND_DIM_FSEL, PMIC_CHRIND_DIM_FSEL_ADDR, PMIC_CHRIND_DIM_FSEL_MASK,
	 PMIC_CHRIND_DIM_FSEL_SHIFT},
	{PMIC_CHRIND_RSV1, PMIC_CHRIND_RSV1_ADDR, PMIC_CHRIND_RSV1_MASK,
	 PMIC_CHRIND_RSV1_SHIFT},
	{PMIC_CHRIND_RSV0, PMIC_CHRIND_RSV0_ADDR, PMIC_CHRIND_RSV0_MASK,
	 PMIC_CHRIND_RSV0_SHIFT},
	{PMIC_CHRIND_DIM_DUTY, PMIC_CHRIND_DIM_DUTY_ADDR, PMIC_CHRIND_DIM_DUTY_MASK,
	 PMIC_CHRIND_DIM_DUTY_SHIFT},
	{PMIC_CHRIND_STEP, PMIC_CHRIND_STEP_ADDR, PMIC_CHRIND_STEP_MASK,
	 PMIC_CHRIND_STEP_SHIFT},
	{PMIC_CHRIND_BREATH_TF2_SEL, PMIC_CHRIND_BREATH_TF2_SEL_ADDR,
	 PMIC_CHRIND_BREATH_TF2_SEL_MASK, PMIC_CHRIND_BREATH_TF2_SEL_SHIFT},
	{PMIC_CHRIND_BREATH_TF1_SEL, PMIC_CHRIND_BREATH_TF1_SEL_ADDR,
	 PMIC_CHRIND_BREATH_TF1_SEL_MASK, PMIC_CHRIND_BREATH_TF1_SEL_SHIFT},
	{PMIC_CHRIND_BREATH_TR2_SEL, PMIC_CHRIND_BREATH_TR2_SEL_ADDR,
	 PMIC_CHRIND_BREATH_TR2_SEL_MASK, PMIC_CHRIND_BREATH_TR2_SEL_SHIFT},
	{PMIC_CHRIND_BREATH_TR1_SEL, PMIC_CHRIND_BREATH_TR1_SEL_ADDR,
	 PMIC_CHRIND_BREATH_TR1_SEL_MASK, PMIC_CHRIND_BREATH_TR1_SEL_SHIFT},
	{PMIC_CHRIND_BREATH_TOFF_SEL, PMIC_CHRIND_BREATH_TOFF_SEL_ADDR,
	 PMIC_CHRIND_BREATH_TOFF_SEL_MASK, PMIC_CHRIND_BREATH_TOFF_SEL_SHIFT},
	{PMIC_CHRIND_BREATH_TON_SEL, PMIC_CHRIND_BREATH_TON_SEL_ADDR,
	 PMIC_CHRIND_BREATH_TON_SEL_MASK, PMIC_CHRIND_BREATH_TON_SEL_SHIFT},
	{PMIC_CHRIND_SFSTR_EN, PMIC_CHRIND_SFSTR_EN_ADDR, PMIC_CHRIND_SFSTR_EN_MASK,
	 PMIC_CHRIND_SFSTR_EN_SHIFT},
	{PMIC_CHRIND_SFSTR_TC, PMIC_CHRIND_SFSTR_TC_ADDR, PMIC_CHRIND_SFSTR_TC_MASK,
	 PMIC_CHRIND_SFSTR_TC_SHIFT},
	{PMIC_CHRIND_EN_SEL, PMIC_CHRIND_EN_SEL_ADDR, PMIC_CHRIND_EN_SEL_MASK,
	 PMIC_CHRIND_EN_SEL_SHIFT},
	{PMIC_CHRIND_EN, PMIC_CHRIND_EN_ADDR, PMIC_CHRIND_EN_MASK,
	 PMIC_CHRIND_EN_SHIFT},
	{PMIC_CHRIND_CHOP_EN, PMIC_CHRIND_CHOP_EN_ADDR, PMIC_CHRIND_CHOP_EN_MASK,
	 PMIC_CHRIND_CHOP_EN_SHIFT},
	{PMIC_CHRIND_MODE, PMIC_CHRIND_MODE_ADDR, PMIC_CHRIND_MODE_MASK,
	 PMIC_CHRIND_MODE_SHIFT},
	{PMIC_CHRIND_CHOP_SW, PMIC_CHRIND_CHOP_SW_ADDR, PMIC_CHRIND_CHOP_SW_MASK,
	 PMIC_CHRIND_CHOP_SW_SHIFT},
	{PMIC_CHRIND_BIAS_EN, PMIC_CHRIND_BIAS_EN_ADDR, PMIC_CHRIND_BIAS_EN_MASK,
	 PMIC_CHRIND_BIAS_EN_SHIFT},
	{PMIC_RG_SLP_RW_EN, PMIC_RG_SLP_RW_EN_ADDR, PMIC_RG_SLP_RW_EN_MASK,
	 PMIC_RG_SLP_RW_EN_SHIFT},
	{PMIC_RG_SPI_RSV, PMIC_RG_SPI_RSV_ADDR, PMIC_RG_SPI_RSV_MASK,
	 PMIC_RG_SPI_RSV_SHIFT},
	{PMIC_DEW_DIO_EN, PMIC_DEW_DIO_EN_ADDR, PMIC_DEW_DIO_EN_MASK,
	 PMIC_DEW_DIO_EN_SHIFT},
	{PMIC_DEW_READ_TEST, PMIC_DEW_READ_TEST_ADDR, PMIC_DEW_READ_TEST_MASK,
	 PMIC_DEW_READ_TEST_SHIFT},
	{PMIC_DEW_WRITE_TEST, PMIC_DEW_WRITE_TEST_ADDR, PMIC_DEW_WRITE_TEST_MASK,
	 PMIC_DEW_WRITE_TEST_SHIFT},
	{PMIC_DEW_CRC_SWRST, PMIC_DEW_CRC_SWRST_ADDR, PMIC_DEW_CRC_SWRST_MASK,
	 PMIC_DEW_CRC_SWRST_SHIFT},
	{PMIC_DEW_CRC_EN, PMIC_DEW_CRC_EN_ADDR, PMIC_DEW_CRC_EN_MASK,
	 PMIC_DEW_CRC_EN_SHIFT},
	{PMIC_DEW_CRC_VAL, PMIC_DEW_CRC_VAL_ADDR, PMIC_DEW_CRC_VAL_MASK,
	 PMIC_DEW_CRC_VAL_SHIFT},
	{PMIC_DEW_DBG_MON_SEL, PMIC_DEW_DBG_MON_SEL_ADDR, PMIC_DEW_DBG_MON_SEL_MASK,
	 PMIC_DEW_DBG_MON_SEL_SHIFT},
	{PMIC_DEW_CIPHER_KEY_SEL, PMIC_DEW_CIPHER_KEY_SEL_ADDR,
	 PMIC_DEW_CIPHER_KEY_SEL_MASK, PMIC_DEW_CIPHER_KEY_SEL_SHIFT},
	{PMIC_DEW_CIPHER_IV_SEL, PMIC_DEW_CIPHER_IV_SEL_ADDR,
	 PMIC_DEW_CIPHER_IV_SEL_MASK, PMIC_DEW_CIPHER_IV_SEL_SHIFT},
	{PMIC_DEW_CIPHER_EN, PMIC_DEW_CIPHER_EN_ADDR, PMIC_DEW_CIPHER_EN_MASK,
	 PMIC_DEW_CIPHER_EN_SHIFT},
	{PMIC_DEW_CIPHER_RDY, PMIC_DEW_CIPHER_RDY_ADDR, PMIC_DEW_CIPHER_RDY_MASK,
	 PMIC_DEW_CIPHER_RDY_SHIFT},
	{PMIC_DEW_CIPHER_MODE, PMIC_DEW_CIPHER_MODE_ADDR, PMIC_DEW_CIPHER_MODE_MASK,
	 PMIC_DEW_CIPHER_MODE_SHIFT},
	{PMIC_DEW_CIPHER_SWRST, PMIC_DEW_CIPHER_SWRST_ADDR,
	 PMIC_DEW_CIPHER_SWRST_MASK, PMIC_DEW_CIPHER_SWRST_SHIFT},
	{PMIC_DEW_RDDMY_NO, PMIC_DEW_RDDMY_NO_ADDR, PMIC_DEW_RDDMY_NO_MASK,
	 PMIC_DEW_RDDMY_NO_SHIFT},
	{PMIC_INT_TYPE_CON0, PMIC_INT_TYPE_CON0_ADDR, PMIC_INT_TYPE_CON0_MASK,
	 PMIC_INT_TYPE_CON0_SHIFT},
	{PMIC_INT_TYPE_CON0_SET, PMIC_INT_TYPE_CON0_SET_ADDR,
	 PMIC_INT_TYPE_CON0_SET_MASK, PMIC_INT_TYPE_CON0_SET_SHIFT},
	{PMIC_INT_TYPE_CON0_CLR, PMIC_INT_TYPE_CON0_CLR_ADDR,
	 PMIC_INT_TYPE_CON0_CLR_MASK, PMIC_INT_TYPE_CON0_CLR_SHIFT},
	{PMIC_INT_TYPE_CON1, PMIC_INT_TYPE_CON1_ADDR, PMIC_INT_TYPE_CON1_MASK,
	 PMIC_INT_TYPE_CON1_SHIFT},
	{PMIC_INT_TYPE_CON1_SET, PMIC_INT_TYPE_CON1_SET_ADDR,
	 PMIC_INT_TYPE_CON1_SET_MASK, PMIC_INT_TYPE_CON1_SET_SHIFT},
	{PMIC_INT_TYPE_CON1_CLR, PMIC_INT_TYPE_CON1_CLR_ADDR,
	 PMIC_INT_TYPE_CON1_CLR_MASK, PMIC_INT_TYPE_CON1_CLR_SHIFT},
	{PMIC_INT_TYPE_CON2, PMIC_INT_TYPE_CON2_ADDR, PMIC_INT_TYPE_CON2_MASK,
	 PMIC_INT_TYPE_CON2_SHIFT},
	{PMIC_INT_TYPE_CON2_SET, PMIC_INT_TYPE_CON2_SET_ADDR,
	 PMIC_INT_TYPE_CON2_SET_MASK, PMIC_INT_TYPE_CON2_SET_SHIFT},
	{PMIC_INT_TYPE_CON2_CLR, PMIC_INT_TYPE_CON2_CLR_ADDR,
	 PMIC_INT_TYPE_CON2_CLR_MASK, PMIC_INT_TYPE_CON2_CLR_SHIFT},
	{PMIC_INT_TYPE_CON3, PMIC_INT_TYPE_CON3_ADDR, PMIC_INT_TYPE_CON3_MASK,
	 PMIC_INT_TYPE_CON3_SHIFT},
	{PMIC_INT_TYPE_CON3_SET, PMIC_INT_TYPE_CON3_SET_ADDR,
	 PMIC_INT_TYPE_CON3_SET_MASK, PMIC_INT_TYPE_CON3_SET_SHIFT},
	{PMIC_INT_TYPE_CON3_CLR, PMIC_INT_TYPE_CON3_CLR_ADDR,
	 PMIC_INT_TYPE_CON3_CLR_MASK, PMIC_INT_TYPE_CON3_CLR_SHIFT},
	{PMIC_CPU_INT_STA, PMIC_CPU_INT_STA_ADDR, PMIC_CPU_INT_STA_MASK,
	 PMIC_CPU_INT_STA_SHIFT},
	{PMIC_MD32_INT_STA, PMIC_MD32_INT_STA_ADDR, PMIC_MD32_INT_STA_MASK,
	 PMIC_MD32_INT_STA_SHIFT},
	{PMIC_BUCK_LDO_FT_TESTMODE_EN, PMIC_BUCK_LDO_FT_TESTMODE_EN_ADDR,
	 PMIC_BUCK_LDO_FT_TESTMODE_EN_MASK, PMIC_BUCK_LDO_FT_TESTMODE_EN_SHIFT},
	{PMIC_EFUSE_VOSEL_LIMIT, PMIC_EFUSE_VOSEL_LIMIT_ADDR,
	 PMIC_EFUSE_VOSEL_LIMIT_MASK, PMIC_EFUSE_VOSEL_LIMIT_SHIFT},
	{PMIC_EFUSE_OC_EN_SEL, PMIC_EFUSE_OC_EN_SEL_ADDR, PMIC_EFUSE_OC_EN_SEL_MASK,
	 PMIC_EFUSE_OC_EN_SEL_SHIFT},
	{PMIC_EFUSE_OC_SDN_EN, PMIC_EFUSE_OC_SDN_EN_ADDR, PMIC_EFUSE_OC_SDN_EN_MASK,
	 PMIC_EFUSE_OC_SDN_EN_SHIFT},
	{PMIC_BUCK_FOR_LDO_OSC_SEL, PMIC_BUCK_FOR_LDO_OSC_SEL_ADDR,
	 PMIC_BUCK_FOR_LDO_OSC_SEL_MASK, PMIC_BUCK_FOR_LDO_OSC_SEL_SHIFT},
	{PMIC_BUCK_ALL_CON0_RSV0, PMIC_BUCK_ALL_CON0_RSV0_ADDR,
	 PMIC_BUCK_ALL_CON0_RSV0_MASK, PMIC_BUCK_ALL_CON0_RSV0_SHIFT},
	{PMIC_BUCK_BUCK_RSV, PMIC_BUCK_BUCK_RSV_ADDR, PMIC_BUCK_BUCK_RSV_MASK,
	 PMIC_BUCK_BUCK_RSV_SHIFT},
	{PMIC_BUCK_VCORE_VOSEL_CTRL_PROT, PMIC_BUCK_VCORE_VOSEL_CTRL_PROT_ADDR,
	 PMIC_BUCK_VCORE_VOSEL_CTRL_PROT_MASK, PMIC_BUCK_VCORE_VOSEL_CTRL_PROT_SHIFT},
	{PMIC_BUCK_VCORE_VOSEL_CTRL_PROT_EN, PMIC_BUCK_VCORE_VOSEL_CTRL_PROT_EN_ADDR,
	 PMIC_BUCK_VCORE_VOSEL_CTRL_PROT_EN_MASK,
	 PMIC_BUCK_VCORE_VOSEL_CTRL_PROT_EN_SHIFT},
	{PMIC_BUCK_ALL_CON2_RSV0, PMIC_BUCK_ALL_CON2_RSV0_ADDR,
	 PMIC_BUCK_ALL_CON2_RSV0_MASK, PMIC_BUCK_ALL_CON2_RSV0_SHIFT},
	{PMIC_BUCK_VSLEEP_SRC0, PMIC_BUCK_VSLEEP_SRC0_ADDR,
	 PMIC_BUCK_VSLEEP_SRC0_MASK, PMIC_BUCK_VSLEEP_SRC0_SHIFT},
	{PMIC_BUCK_VSLEEP_SRC1, PMIC_BUCK_VSLEEP_SRC1_ADDR,
	 PMIC_BUCK_VSLEEP_SRC1_MASK, PMIC_BUCK_VSLEEP_SRC1_SHIFT},
	{PMIC_BUCK_R2R_SRC0, PMIC_BUCK_R2R_SRC0_ADDR, PMIC_BUCK_R2R_SRC0_MASK,
	 PMIC_BUCK_R2R_SRC0_SHIFT},
	{PMIC_BUCK_R2R_SRC1, PMIC_BUCK_R2R_SRC1_ADDR, PMIC_BUCK_R2R_SRC1_MASK,
	 PMIC_BUCK_R2R_SRC1_SHIFT},
	{PMIC_BUCK_BUCK_OSC_SEL_SRC0, PMIC_BUCK_BUCK_OSC_SEL_SRC0_ADDR,
	 PMIC_BUCK_BUCK_OSC_SEL_SRC0_MASK, PMIC_BUCK_BUCK_OSC_SEL_SRC0_SHIFT},
	{PMIC_BUCK_SRCLKEN_DLY_SRC1, PMIC_BUCK_SRCLKEN_DLY_SRC1_ADDR,
	 PMIC_BUCK_SRCLKEN_DLY_SRC1_MASK, PMIC_BUCK_SRCLKEN_DLY_SRC1_SHIFT},
	{PMIC_BUCK_VPA_VOSEL_DLC011, PMIC_BUCK_VPA_VOSEL_DLC011_ADDR,
	 PMIC_BUCK_VPA_VOSEL_DLC011_MASK, PMIC_BUCK_VPA_VOSEL_DLC011_SHIFT},
	{PMIC_BUCK_VPA_VOSEL_DLC111, PMIC_BUCK_VPA_VOSEL_DLC111_ADDR,
	 PMIC_BUCK_VPA_VOSEL_DLC111_MASK, PMIC_BUCK_VPA_VOSEL_DLC111_SHIFT},
	{PMIC_BUCK_VPA_DLC_MAP_EN, PMIC_BUCK_VPA_DLC_MAP_EN_ADDR,
	 PMIC_BUCK_VPA_DLC_MAP_EN_MASK, PMIC_BUCK_VPA_DLC_MAP_EN_SHIFT},
	{PMIC_BUCK_VPA_VOSEL_DLC001, PMIC_BUCK_VPA_VOSEL_DLC001_ADDR,
	 PMIC_BUCK_VPA_VOSEL_DLC001_MASK, PMIC_BUCK_VPA_VOSEL_DLC001_SHIFT},
	{PMIC_BUCK_VPA_DLC, PMIC_BUCK_VPA_DLC_ADDR, PMIC_BUCK_VPA_DLC_MASK,
	 PMIC_BUCK_VPA_DLC_SHIFT},
	{PMIC_DA_NI_VPA_DLC, PMIC_DA_NI_VPA_DLC_ADDR, PMIC_DA_NI_VPA_DLC_MASK,
	 PMIC_DA_NI_VPA_DLC_SHIFT},
	{PMIC_BUCK_VSRAM_PROC_TRACK_SLEEP_CTRL, PMIC_BUCK_VSRAM_PROC_TRACK_SLEEP_CTRL_ADDR,
	 PMIC_BUCK_VSRAM_PROC_TRACK_SLEEP_CTRL_MASK,
	 PMIC_BUCK_VSRAM_PROC_TRACK_SLEEP_CTRL_SHIFT},
	{PMIC_BUCK_VSRAM_PROC_TRACK_ON_CTRL, PMIC_BUCK_VSRAM_PROC_TRACK_ON_CTRL_ADDR,
	 PMIC_BUCK_VSRAM_PROC_TRACK_ON_CTRL_MASK,
	 PMIC_BUCK_VSRAM_PROC_TRACK_ON_CTRL_SHIFT},
	{PMIC_BUCK_VPROC_TRACK_ON_CTRL, PMIC_BUCK_VPROC_TRACK_ON_CTRL_ADDR,
	 PMIC_BUCK_VPROC_TRACK_ON_CTRL_MASK, PMIC_BUCK_VPROC_TRACK_ON_CTRL_SHIFT},
	{PMIC_BUCK_VSRAM_PROC_VOSEL_DELTA, PMIC_BUCK_VSRAM_PROC_VOSEL_DELTA_ADDR,
	 PMIC_BUCK_VSRAM_PROC_VOSEL_DELTA_MASK,
	 PMIC_BUCK_VSRAM_PROC_VOSEL_DELTA_SHIFT},
	{PMIC_BUCK_VSRAM_PROC_VOSEL_OFFSET, PMIC_BUCK_VSRAM_PROC_VOSEL_OFFSET_ADDR,
	 PMIC_BUCK_VSRAM_PROC_VOSEL_OFFSET_MASK,
	 PMIC_BUCK_VSRAM_PROC_VOSEL_OFFSET_SHIFT},
	{PMIC_BUCK_VSRAM_PROC_VOSEL_ON_LB, PMIC_BUCK_VSRAM_PROC_VOSEL_ON_LB_ADDR,
	 PMIC_BUCK_VSRAM_PROC_VOSEL_ON_LB_MASK,
	 PMIC_BUCK_VSRAM_PROC_VOSEL_ON_LB_SHIFT},
	{PMIC_BUCK_VSRAM_PROC_VOSEL_ON_HB, PMIC_BUCK_VSRAM_PROC_VOSEL_ON_HB_ADDR,
	 PMIC_BUCK_VSRAM_PROC_VOSEL_ON_HB_MASK,
	 PMIC_BUCK_VSRAM_PROC_VOSEL_ON_HB_SHIFT},
	{PMIC_BUCK_VSRAM_PROC_VOSEL_SLEEP_LB, PMIC_BUCK_VSRAM_PROC_VOSEL_SLEEP_LB_ADDR,
	 PMIC_BUCK_VSRAM_PROC_VOSEL_SLEEP_LB_MASK,
	 PMIC_BUCK_VSRAM_PROC_VOSEL_SLEEP_LB_SHIFT},
	{PMIC_AD_QI_VCORE_OC_STATUS, PMIC_AD_QI_VCORE_OC_STATUS_ADDR,
	 PMIC_AD_QI_VCORE_OC_STATUS_MASK, PMIC_AD_QI_VCORE_OC_STATUS_SHIFT},
	{PMIC_AD_QI_VPROC_OC_STATUS, PMIC_AD_QI_VPROC_OC_STATUS_ADDR,
	 PMIC_AD_QI_VPROC_OC_STATUS_MASK, PMIC_AD_QI_VPROC_OC_STATUS_SHIFT},
	{PMIC_AD_QI_VS1_OC_STATUS, PMIC_AD_QI_VS1_OC_STATUS_ADDR,
	 PMIC_AD_QI_VS1_OC_STATUS_MASK, PMIC_AD_QI_VS1_OC_STATUS_SHIFT},
	{PMIC_AD_QI_VPA_OC_STATUS, PMIC_AD_QI_VPA_OC_STATUS_ADDR,
	 PMIC_AD_QI_VPA_OC_STATUS_MASK, PMIC_AD_QI_VPA_OC_STATUS_SHIFT},
	{PMIC_BUCK_ANA_STATUS, PMIC_BUCK_ANA_STATUS_ADDR, PMIC_BUCK_ANA_STATUS_MASK,
	 PMIC_BUCK_ANA_STATUS_SHIFT},
	{PMIC_AD_QI_VCORE_DIG_MON, PMIC_AD_QI_VCORE_DIG_MON_ADDR,
	 PMIC_AD_QI_VCORE_DIG_MON_MASK, PMIC_AD_QI_VCORE_DIG_MON_SHIFT},
	{PMIC_AD_QI_VPROC_DIG_MON, PMIC_AD_QI_VPROC_DIG_MON_ADDR,
	 PMIC_AD_QI_VPROC_DIG_MON_MASK, PMIC_AD_QI_VPROC_DIG_MON_SHIFT},
	{PMIC_AD_QI_VS1_DIG_MON, PMIC_AD_QI_VS1_DIG_MON_ADDR,
	 PMIC_AD_QI_VS1_DIG_MON_MASK, PMIC_AD_QI_VS1_DIG_MON_SHIFT},
	{PMIC_BUCK_VCORE_OC_STATUS, PMIC_BUCK_VCORE_OC_STATUS_ADDR,
	 PMIC_BUCK_VCORE_OC_STATUS_MASK, PMIC_BUCK_VCORE_OC_STATUS_SHIFT},
	{PMIC_BUCK_VCORE2_OC_STATUS, PMIC_BUCK_VCORE2_OC_STATUS_ADDR,
	 PMIC_BUCK_VCORE2_OC_STATUS_MASK, PMIC_BUCK_VCORE2_OC_STATUS_SHIFT},
	{PMIC_BUCK_VPROC_OC_STATUS, PMIC_BUCK_VPROC_OC_STATUS_ADDR,
	 PMIC_BUCK_VPROC_OC_STATUS_MASK, PMIC_BUCK_VPROC_OC_STATUS_SHIFT},
	{PMIC_BUCK_VS1_OC_STATUS, PMIC_BUCK_VS1_OC_STATUS_ADDR,
	 PMIC_BUCK_VS1_OC_STATUS_MASK, PMIC_BUCK_VS1_OC_STATUS_SHIFT},
	{PMIC_BUCK_VPA_OC_STATUS, PMIC_BUCK_VPA_OC_STATUS_ADDR,
	 PMIC_BUCK_VPA_OC_STATUS_MASK, PMIC_BUCK_VPA_OC_STATUS_SHIFT},
	{PMIC_BUCK_VCORE_OC_INT_EN, PMIC_BUCK_VCORE_OC_INT_EN_ADDR,
	 PMIC_BUCK_VCORE_OC_INT_EN_MASK, PMIC_BUCK_VCORE_OC_INT_EN_SHIFT},
	{PMIC_BUCK_VCORE2_OC_INT_EN, PMIC_BUCK_VCORE2_OC_INT_EN_ADDR,
	 PMIC_BUCK_VCORE2_OC_INT_EN_MASK, PMIC_BUCK_VCORE2_OC_INT_EN_SHIFT},
	{PMIC_BUCK_VPROC_OC_INT_EN, PMIC_BUCK_VPROC_OC_INT_EN_ADDR,
	 PMIC_BUCK_VPROC_OC_INT_EN_MASK, PMIC_BUCK_VPROC_OC_INT_EN_SHIFT},
	{PMIC_BUCK_VS1_OC_INT_EN, PMIC_BUCK_VS1_OC_INT_EN_ADDR,
	 PMIC_BUCK_VS1_OC_INT_EN_MASK, PMIC_BUCK_VS1_OC_INT_EN_SHIFT},
	{PMIC_BUCK_VPA_OC_INT_EN, PMIC_BUCK_VPA_OC_INT_EN_ADDR,
	 PMIC_BUCK_VPA_OC_INT_EN_MASK, PMIC_BUCK_VPA_OC_INT_EN_SHIFT},
	{PMIC_BUCK_VCORE_EN_OC_SDN_SEL, PMIC_BUCK_VCORE_EN_OC_SDN_SEL_ADDR,
	 PMIC_BUCK_VCORE_EN_OC_SDN_SEL_MASK, PMIC_BUCK_VCORE_EN_OC_SDN_SEL_SHIFT},
	{PMIC_BUCK_VCORE2_EN_OC_SDN_SEL, PMIC_BUCK_VCORE2_EN_OC_SDN_SEL_ADDR,
	 PMIC_BUCK_VCORE2_EN_OC_SDN_SEL_MASK, PMIC_BUCK_VCORE2_EN_OC_SDN_SEL_SHIFT},
	{PMIC_BUCK_VPROC_EN_OC_SDN_SEL, PMIC_BUCK_VPROC_EN_OC_SDN_SEL_ADDR,
	 PMIC_BUCK_VPROC_EN_OC_SDN_SEL_MASK, PMIC_BUCK_VPROC_EN_OC_SDN_SEL_SHIFT},
	{PMIC_BUCK_VS1_EN_OC_SDN_SEL, PMIC_BUCK_VS1_EN_OC_SDN_SEL_ADDR,
	 PMIC_BUCK_VS1_EN_OC_SDN_SEL_MASK, PMIC_BUCK_VS1_EN_OC_SDN_SEL_SHIFT},
	{PMIC_BUCK_VPA_EN_OC_SDN_SEL, PMIC_BUCK_VPA_EN_OC_SDN_SEL_ADDR,
	 PMIC_BUCK_VPA_EN_OC_SDN_SEL_MASK, PMIC_BUCK_VPA_EN_OC_SDN_SEL_SHIFT},
	{PMIC_BUCK_VCORE_OC_FLAG_CLR, PMIC_BUCK_VCORE_OC_FLAG_CLR_ADDR,
	 PMIC_BUCK_VCORE_OC_FLAG_CLR_MASK, PMIC_BUCK_VCORE_OC_FLAG_CLR_SHIFT},
	{PMIC_BUCK_VCORE2_OC_FLAG_CLR, PMIC_BUCK_VCORE2_OC_FLAG_CLR_ADDR,
	 PMIC_BUCK_VCORE2_OC_FLAG_CLR_MASK, PMIC_BUCK_VCORE2_OC_FLAG_CLR_SHIFT},
	{PMIC_BUCK_VPROC_OC_FLAG_CLR, PMIC_BUCK_VPROC_OC_FLAG_CLR_ADDR,
	 PMIC_BUCK_VPROC_OC_FLAG_CLR_MASK, PMIC_BUCK_VPROC_OC_FLAG_CLR_SHIFT},
	{PMIC_BUCK_VS1_OC_FLAG_CLR, PMIC_BUCK_VS1_OC_FLAG_CLR_ADDR,
	 PMIC_BUCK_VS1_OC_FLAG_CLR_MASK, PMIC_BUCK_VS1_OC_FLAG_CLR_SHIFT},
	{PMIC_BUCK_VPA_OC_FLAG_CLR, PMIC_BUCK_VPA_OC_FLAG_CLR_ADDR,
	 PMIC_BUCK_VPA_OC_FLAG_CLR_MASK, PMIC_BUCK_VPA_OC_FLAG_CLR_SHIFT},
	{PMIC_BUCK_VCORE_OC_FLAG_CLR_SEL, PMIC_BUCK_VCORE_OC_FLAG_CLR_SEL_ADDR,
	 PMIC_BUCK_VCORE_OC_FLAG_CLR_SEL_MASK, PMIC_BUCK_VCORE_OC_FLAG_CLR_SEL_SHIFT},
	{PMIC_BUCK_VCORE2_OC_FLAG_CLR_SEL, PMIC_BUCK_VCORE2_OC_FLAG_CLR_SEL_ADDR,
	 PMIC_BUCK_VCORE2_OC_FLAG_CLR_SEL_MASK,
	 PMIC_BUCK_VCORE2_OC_FLAG_CLR_SEL_SHIFT},
	{PMIC_BUCK_VPROC_OC_FLAG_CLR_SEL, PMIC_BUCK_VPROC_OC_FLAG_CLR_SEL_ADDR,
	 PMIC_BUCK_VPROC_OC_FLAG_CLR_SEL_MASK, PMIC_BUCK_VPROC_OC_FLAG_CLR_SEL_SHIFT},
	{PMIC_BUCK_VS1_OC_FLAG_CLR_SEL, PMIC_BUCK_VS1_OC_FLAG_CLR_SEL_ADDR,
	 PMIC_BUCK_VS1_OC_FLAG_CLR_SEL_MASK, PMIC_BUCK_VS1_OC_FLAG_CLR_SEL_SHIFT},
	{PMIC_BUCK_VPA_OC_FLAG_CLR_SEL, PMIC_BUCK_VPA_OC_FLAG_CLR_SEL_ADDR,
	 PMIC_BUCK_VPA_OC_FLAG_CLR_SEL_MASK, PMIC_BUCK_VPA_OC_FLAG_CLR_SEL_SHIFT},
	{PMIC_BUCK_VCORE_OC_DEG_EN, PMIC_BUCK_VCORE_OC_DEG_EN_ADDR,
	 PMIC_BUCK_VCORE_OC_DEG_EN_MASK, PMIC_BUCK_VCORE_OC_DEG_EN_SHIFT},
	{PMIC_BUCK_VCORE_OC_WND, PMIC_BUCK_VCORE_OC_WND_ADDR,
	 PMIC_BUCK_VCORE_OC_WND_MASK, PMIC_BUCK_VCORE_OC_WND_SHIFT},
	{PMIC_BUCK_VCORE_OC_THD, PMIC_BUCK_VCORE_OC_THD_ADDR,
	 PMIC_BUCK_VCORE_OC_THD_MASK, PMIC_BUCK_VCORE_OC_THD_SHIFT},
	{PMIC_BUCK_VCORE2_OC_DEG_EN, PMIC_BUCK_VCORE2_OC_DEG_EN_ADDR,
	 PMIC_BUCK_VCORE2_OC_DEG_EN_MASK, PMIC_BUCK_VCORE2_OC_DEG_EN_SHIFT},
	{PMIC_BUCK_VCORE2_OC_WND, PMIC_BUCK_VCORE2_OC_WND_ADDR,
	 PMIC_BUCK_VCORE2_OC_WND_MASK, PMIC_BUCK_VCORE2_OC_WND_SHIFT},
	{PMIC_BUCK_VCORE2_OC_THD, PMIC_BUCK_VCORE2_OC_THD_ADDR,
	 PMIC_BUCK_VCORE2_OC_THD_MASK, PMIC_BUCK_VCORE2_OC_THD_SHIFT},
	{PMIC_BUCK_VPROC_OC_DEG_EN, PMIC_BUCK_VPROC_OC_DEG_EN_ADDR,
	 PMIC_BUCK_VPROC_OC_DEG_EN_MASK, PMIC_BUCK_VPROC_OC_DEG_EN_SHIFT},
	{PMIC_BUCK_VPROC_OC_WND, PMIC_BUCK_VPROC_OC_WND_ADDR,
	 PMIC_BUCK_VPROC_OC_WND_MASK, PMIC_BUCK_VPROC_OC_WND_SHIFT},
	{PMIC_BUCK_VPROC_OC_THD, PMIC_BUCK_VPROC_OC_THD_ADDR,
	 PMIC_BUCK_VPROC_OC_THD_MASK, PMIC_BUCK_VPROC_OC_THD_SHIFT},
	{PMIC_BUCK_VS1_OC_DEG_EN, PMIC_BUCK_VS1_OC_DEG_EN_ADDR,
	 PMIC_BUCK_VS1_OC_DEG_EN_MASK, PMIC_BUCK_VS1_OC_DEG_EN_SHIFT},
	{PMIC_BUCK_VS1_OC_WND, PMIC_BUCK_VS1_OC_WND_ADDR, PMIC_BUCK_VS1_OC_WND_MASK,
	 PMIC_BUCK_VS1_OC_WND_SHIFT},
	{PMIC_BUCK_VS1_OC_THD, PMIC_BUCK_VS1_OC_THD_ADDR, PMIC_BUCK_VS1_OC_THD_MASK,
	 PMIC_BUCK_VS1_OC_THD_SHIFT},
	{PMIC_BUCK_VPA_OC_DEG_EN, PMIC_BUCK_VPA_OC_DEG_EN_ADDR,
	 PMIC_BUCK_VPA_OC_DEG_EN_MASK, PMIC_BUCK_VPA_OC_DEG_EN_SHIFT},
	{PMIC_BUCK_VPA_OC_WND, PMIC_BUCK_VPA_OC_WND_ADDR, PMIC_BUCK_VPA_OC_WND_MASK,
	 PMIC_BUCK_VPA_OC_WND_SHIFT},
	{PMIC_BUCK_VPA_OC_THD, PMIC_BUCK_VPA_OC_THD_ADDR, PMIC_BUCK_VPA_OC_THD_MASK,
	 PMIC_BUCK_VPA_OC_THD_SHIFT},
	{PMIC_RG_SMPS_TESTMODE_B, PMIC_RG_SMPS_TESTMODE_B_ADDR,
	 PMIC_RG_SMPS_TESTMODE_B_MASK, PMIC_RG_SMPS_TESTMODE_B_SHIFT},
	{PMIC_RG_VSRAM_PROC_TRIMH, PMIC_RG_VSRAM_PROC_TRIMH_ADDR,
	 PMIC_RG_VSRAM_PROC_TRIMH_MASK, PMIC_RG_VSRAM_PROC_TRIMH_SHIFT},
	{PMIC_RG_VSRAM_PROC_TRIML, PMIC_RG_VSRAM_PROC_TRIML_ADDR,
	 PMIC_RG_VSRAM_PROC_TRIML_MASK, PMIC_RG_VSRAM_PROC_TRIML_SHIFT},
	{PMIC_RG_VPROC_TRIMH, PMIC_RG_VPROC_TRIMH_ADDR, PMIC_RG_VPROC_TRIMH_MASK,
	 PMIC_RG_VPROC_TRIMH_SHIFT},
	{PMIC_RG_VPROC_TRIML, PMIC_RG_VPROC_TRIML_ADDR, PMIC_RG_VPROC_TRIML_MASK,
	 PMIC_RG_VPROC_TRIML_SHIFT},
	{PMIC_RG_VCORE_TRIMH, PMIC_RG_VCORE_TRIMH_ADDR, PMIC_RG_VCORE_TRIMH_MASK,
	 PMIC_RG_VCORE_TRIMH_SHIFT},
	{PMIC_RG_VCORE_TRIML, PMIC_RG_VCORE_TRIML_ADDR, PMIC_RG_VCORE_TRIML_MASK,
	 PMIC_RG_VCORE_TRIML_SHIFT},
	{PMIC_RG_VCORE2_TRIMH, PMIC_RG_VCORE2_TRIMH_ADDR, PMIC_RG_VCORE2_TRIMH_MASK,
	 PMIC_RG_VCORE2_TRIMH_SHIFT},
	{PMIC_RG_VCORE2_TRIML, PMIC_RG_VCORE2_TRIML_ADDR, PMIC_RG_VCORE2_TRIML_MASK,
	 PMIC_RG_VCORE2_TRIML_SHIFT},
	{PMIC_RG_VS1_TRIMH, PMIC_RG_VS1_TRIMH_ADDR, PMIC_RG_VS1_TRIMH_MASK,
	 PMIC_RG_VS1_TRIMH_SHIFT},
	{PMIC_RG_VS1_TRIML, PMIC_RG_VS1_TRIML_ADDR, PMIC_RG_VS1_TRIML_MASK,
	 PMIC_RG_VS1_TRIML_SHIFT},
	{PMIC_RG_VPA_TRIMH, PMIC_RG_VPA_TRIMH_ADDR, PMIC_RG_VPA_TRIMH_MASK,
	 PMIC_RG_VPA_TRIMH_SHIFT},
	{PMIC_RG_VPA_TRIML, PMIC_RG_VPA_TRIML_ADDR, PMIC_RG_VPA_TRIML_MASK,
	 PMIC_RG_VPA_TRIML_SHIFT},
	{PMIC_RG_VPA_TRIM_REF, PMIC_RG_VPA_TRIM_REF_ADDR, PMIC_RG_VPA_TRIM_REF_MASK,
	 PMIC_RG_VPA_TRIM_REF_SHIFT},
	{PMIC_RG_VSRAM_PROC_VSLEEP, PMIC_RG_VSRAM_PROC_VSLEEP_ADDR,
	 PMIC_RG_VSRAM_PROC_VSLEEP_MASK, PMIC_RG_VSRAM_PROC_VSLEEP_SHIFT},
	{PMIC_RG_VPROC_VSLEEP, PMIC_RG_VPROC_VSLEEP_ADDR, PMIC_RG_VPROC_VSLEEP_MASK,
	 PMIC_RG_VPROC_VSLEEP_SHIFT},
	{PMIC_RG_VCORE_VSLEEP, PMIC_RG_VCORE_VSLEEP_ADDR, PMIC_RG_VCORE_VSLEEP_MASK,
	 PMIC_RG_VCORE_VSLEEP_SHIFT},
	{PMIC_RG_VCORE2_VSLEEP, PMIC_RG_VCORE2_VSLEEP_ADDR,
	 PMIC_RG_VCORE2_VSLEEP_MASK, PMIC_RG_VCORE2_VSLEEP_SHIFT},
	{PMIC_RG_VPA_BURSTH, PMIC_RG_VPA_BURSTH_ADDR, PMIC_RG_VPA_BURSTH_MASK,
	 PMIC_RG_VPA_BURSTH_SHIFT},
	{PMIC_RG_VPA_BURSTL, PMIC_RG_VPA_BURSTL_ADDR, PMIC_RG_VPA_BURSTL_MASK,
	 PMIC_RG_VPA_BURSTL_SHIFT},
	{PMIC_RG_DMY100MA_EN, PMIC_RG_DMY100MA_EN_ADDR, PMIC_RG_DMY100MA_EN_MASK,
	 PMIC_RG_DMY100MA_EN_SHIFT},
	{PMIC_RG_DMY100MA_SEL, PMIC_RG_DMY100MA_SEL_ADDR, PMIC_RG_DMY100MA_SEL_MASK,
	 PMIC_RG_DMY100MA_SEL_SHIFT},
	{PMIC_RG_VSRAM_PROC_VSLEEP_VOLTAGE, PMIC_RG_VSRAM_PROC_VSLEEP_VOLTAGE_ADDR,
	 PMIC_RG_VSRAM_PROC_VSLEEP_VOLTAGE_MASK,
	 PMIC_RG_VSRAM_PROC_VSLEEP_VOLTAGE_SHIFT},
	{PMIC_RG_VPROC_VSLEEP_VOLTAGE, PMIC_RG_VPROC_VSLEEP_VOLTAGE_ADDR,
	 PMIC_RG_VPROC_VSLEEP_VOLTAGE_MASK, PMIC_RG_VPROC_VSLEEP_VOLTAGE_SHIFT},
	{PMIC_RG_VCORE_VSLEEP_VOLTAGE, PMIC_RG_VCORE_VSLEEP_VOLTAGE_ADDR,
	 PMIC_RG_VCORE_VSLEEP_VOLTAGE_MASK, PMIC_RG_VCORE_VSLEEP_VOLTAGE_SHIFT},
	{PMIC_RG_VCORE2_VSLEEP_VOLTAGE, PMIC_RG_VCORE2_VSLEEP_VOLTAGE_ADDR,
	 PMIC_RG_VCORE2_VSLEEP_VOLTAGE_MASK, PMIC_RG_VCORE2_VSLEEP_VOLTAGE_SHIFT},
	{PMIC_RG_VPA_RZSEL, PMIC_RG_VPA_RZSEL_ADDR, PMIC_RG_VPA_RZSEL_MASK,
	 PMIC_RG_VPA_RZSEL_SHIFT},
	{PMIC_RG_VPA_CC, PMIC_RG_VPA_CC_ADDR, PMIC_RG_VPA_CC_MASK,
	 PMIC_RG_VPA_CC_SHIFT},
	{PMIC_RG_VPA_CSR, PMIC_RG_VPA_CSR_ADDR, PMIC_RG_VPA_CSR_MASK,
	 PMIC_RG_VPA_CSR_SHIFT},
	{PMIC_RG_VPA_CSMIR, PMIC_RG_VPA_CSMIR_ADDR, PMIC_RG_VPA_CSMIR_MASK,
	 PMIC_RG_VPA_CSMIR_SHIFT},
	{PMIC_RG_VPA_CSL, PMIC_RG_VPA_CSL_ADDR, PMIC_RG_VPA_CSL_MASK,
	 PMIC_RG_VPA_CSL_SHIFT},
	{PMIC_RG_VPA_SLP, PMIC_RG_VPA_SLP_ADDR, PMIC_RG_VPA_SLP_MASK,
	 PMIC_RG_VPA_SLP_SHIFT},
	{PMIC_RG_VPA_ZX_OS_TRIM, PMIC_RG_VPA_ZX_OS_TRIM_ADDR,
	 PMIC_RG_VPA_ZX_OS_TRIM_MASK, PMIC_RG_VPA_ZX_OS_TRIM_SHIFT},
	{PMIC_RG_VPA_ZX_OS, PMIC_RG_VPA_ZX_OS_ADDR, PMIC_RG_VPA_ZX_OS_MASK,
	 PMIC_RG_VPA_ZX_OS_SHIFT},
	{PMIC_RG_VPA_HZP, PMIC_RG_VPA_HZP_ADDR, PMIC_RG_VPA_HZP_MASK,
	 PMIC_RG_VPA_HZP_SHIFT},
	{PMIC_RG_VPA_BWEX_GAT, PMIC_RG_VPA_BWEX_GAT_ADDR, PMIC_RG_VPA_BWEX_GAT_MASK,
	 PMIC_RG_VPA_BWEX_GAT_SHIFT},
	{PMIC_RG_VPA_MODESET, PMIC_RG_VPA_MODESET_ADDR, PMIC_RG_VPA_MODESET_MASK,
	 PMIC_RG_VPA_MODESET_SHIFT},
	{PMIC_RG_VPA_SLEW, PMIC_RG_VPA_SLEW_ADDR, PMIC_RG_VPA_SLEW_MASK,
	 PMIC_RG_VPA_SLEW_SHIFT},
	{PMIC_RG_VPA_SLEW_NMOS, PMIC_RG_VPA_SLEW_NMOS_ADDR,
	 PMIC_RG_VPA_SLEW_NMOS_MASK, PMIC_RG_VPA_SLEW_NMOS_SHIFT},
	{PMIC_RG_VPA_NDIS_EN, PMIC_RG_VPA_NDIS_EN_ADDR, PMIC_RG_VPA_NDIS_EN_MASK,
	 PMIC_RG_VPA_NDIS_EN_SHIFT},
	{PMIC_RG_VPA_MIN_ON, PMIC_RG_VPA_MIN_ON_ADDR, PMIC_RG_VPA_MIN_ON_MASK,
	 PMIC_RG_VPA_MIN_ON_SHIFT},
	{PMIC_RG_VPA_VBAT_DEL, PMIC_RG_VPA_VBAT_DEL_ADDR, PMIC_RG_VPA_VBAT_DEL_MASK,
	 PMIC_RG_VPA_VBAT_DEL_SHIFT},
	{PMIC_RG_VPA_RSV1, PMIC_RG_VPA_RSV1_ADDR, PMIC_RG_VPA_RSV1_MASK,
	 PMIC_RG_VPA_RSV1_SHIFT},
	{PMIC_RG_VPA_RSV2, PMIC_RG_VPA_RSV2_ADDR, PMIC_RG_VPA_RSV2_MASK,
	 PMIC_RG_VPA_RSV2_SHIFT},
	{PMIC_RGS_VPA_ZX_STATUS, PMIC_RGS_VPA_ZX_STATUS_ADDR,
	 PMIC_RGS_VPA_ZX_STATUS_MASK, PMIC_RGS_VPA_ZX_STATUS_SHIFT},
	{PMIC_RG_VCORE_MIN_OFF, PMIC_RG_VCORE_MIN_OFF_ADDR,
	 PMIC_RG_VCORE_MIN_OFF_MASK, PMIC_RG_VCORE_MIN_OFF_SHIFT},
	{PMIC_RG_VCORE_VRF18_SSTART_EN, PMIC_RG_VCORE_VRF18_SSTART_EN_ADDR,
	 PMIC_RG_VCORE_VRF18_SSTART_EN_MASK, PMIC_RG_VCORE_VRF18_SSTART_EN_SHIFT},
	{PMIC_RG_VCORE_1P35UP_SEL_EN, PMIC_RG_VCORE_1P35UP_SEL_EN_ADDR,
	 PMIC_RG_VCORE_1P35UP_SEL_EN_MASK, PMIC_RG_VCORE_1P35UP_SEL_EN_SHIFT},
	{PMIC_RG_VCORE_RZSEL, PMIC_RG_VCORE_RZSEL_ADDR, PMIC_RG_VCORE_RZSEL_MASK,
	 PMIC_RG_VCORE_RZSEL_SHIFT},
	{PMIC_RG_VCORE_CSR, PMIC_RG_VCORE_CSR_ADDR, PMIC_RG_VCORE_CSR_MASK,
	 PMIC_RG_VCORE_CSR_SHIFT},
	{PMIC_RG_VCORE_CSL, PMIC_RG_VCORE_CSL_ADDR, PMIC_RG_VCORE_CSL_MASK,
	 PMIC_RG_VCORE_CSL_SHIFT},
	{PMIC_RG_VCORE_SLP, PMIC_RG_VCORE_SLP_ADDR, PMIC_RG_VCORE_SLP_MASK,
	 PMIC_RG_VCORE_SLP_SHIFT},
	{PMIC_RG_VCORE_ZX_OS, PMIC_RG_VCORE_ZX_OS_ADDR, PMIC_RG_VCORE_ZX_OS_MASK,
	 PMIC_RG_VCORE_ZX_OS_SHIFT},
	{PMIC_RG_VCORE_ZXOS_TRIM, PMIC_RG_VCORE_ZXOS_TRIM_ADDR,
	 PMIC_RG_VCORE_ZXOS_TRIM_MASK, PMIC_RG_VCORE_ZXOS_TRIM_SHIFT},
	{PMIC_RG_VCORE_MODESET, PMIC_RG_VCORE_MODESET_ADDR,
	 PMIC_RG_VCORE_MODESET_MASK, PMIC_RG_VCORE_MODESET_SHIFT},
	{PMIC_RG_VCORE_NDIS_EN, PMIC_RG_VCORE_NDIS_EN_ADDR,
	 PMIC_RG_VCORE_NDIS_EN_MASK, PMIC_RG_VCORE_NDIS_EN_SHIFT},
	{PMIC_RG_VCORE_CSM_N, PMIC_RG_VCORE_CSM_N_ADDR, PMIC_RG_VCORE_CSM_N_MASK,
	 PMIC_RG_VCORE_CSM_N_SHIFT},
	{PMIC_RG_VCORE_CSM_P, PMIC_RG_VCORE_CSM_P_ADDR, PMIC_RG_VCORE_CSM_P_MASK,
	 PMIC_RG_VCORE_CSM_P_SHIFT},
	{PMIC_RG_VCORE_RSV, PMIC_RG_VCORE_RSV_ADDR, PMIC_RG_VCORE_RSV_MASK,
	 PMIC_RG_VCORE_RSV_SHIFT},
	{PMIC_RG_VCORE_PFM_RIP, PMIC_RG_VCORE_PFM_RIP_ADDR,
	 PMIC_RG_VCORE_PFM_RIP_MASK, PMIC_RG_VCORE_PFM_RIP_SHIFT},
	{PMIC_RG_VCORE_DTS_ENB, PMIC_RG_VCORE_DTS_ENB_ADDR,
	 PMIC_RG_VCORE_DTS_ENB_MASK, PMIC_RG_VCORE_DTS_ENB_SHIFT},
	{PMIC_RG_VCORE_AUTO_MODE, PMIC_RG_VCORE_AUTO_MODE_ADDR,
	 PMIC_RG_VCORE_AUTO_MODE_MASK, PMIC_RG_VCORE_AUTO_MODE_SHIFT},
	{PMIC_RG_VCORE_PWM_TRIG, PMIC_RG_VCORE_PWM_TRIG_ADDR,
	 PMIC_RG_VCORE_PWM_TRIG_MASK, PMIC_RG_VCORE_PWM_TRIG_SHIFT},
	{PMIC_RG_VCORE_TRAN_BST, PMIC_RG_VCORE_TRAN_BST_ADDR,
	 PMIC_RG_VCORE_TRAN_BST_MASK, PMIC_RG_VCORE_TRAN_BST_SHIFT},
	{PMIC_RGS_VCORE_ENPWM_STATUS, PMIC_RGS_VCORE_ENPWM_STATUS_ADDR,
	 PMIC_RGS_VCORE_ENPWM_STATUS_MASK, PMIC_RGS_VCORE_ENPWM_STATUS_SHIFT},
	{PMIC_RG_VPROC_MIN_OFF, PMIC_RG_VPROC_MIN_OFF_ADDR,
	 PMIC_RG_VPROC_MIN_OFF_MASK, PMIC_RG_VPROC_MIN_OFF_SHIFT},
	{PMIC_RG_VPROC_VRF18_SSTART_EN, PMIC_RG_VPROC_VRF18_SSTART_EN_ADDR,
	 PMIC_RG_VPROC_VRF18_SSTART_EN_MASK, PMIC_RG_VPROC_VRF18_SSTART_EN_SHIFT},
	{PMIC_RG_VPROC_1P35UP_SEL_EN, PMIC_RG_VPROC_1P35UP_SEL_EN_ADDR,
	 PMIC_RG_VPROC_1P35UP_SEL_EN_MASK, PMIC_RG_VPROC_1P35UP_SEL_EN_SHIFT},
	{PMIC_RG_VPROC_RZSEL, PMIC_RG_VPROC_RZSEL_ADDR, PMIC_RG_VPROC_RZSEL_MASK,
	 PMIC_RG_VPROC_RZSEL_SHIFT},
	{PMIC_RG_VPROC_CSR, PMIC_RG_VPROC_CSR_ADDR, PMIC_RG_VPROC_CSR_MASK,
	 PMIC_RG_VPROC_CSR_SHIFT},
	{PMIC_RG_VPROC_CSL, PMIC_RG_VPROC_CSL_ADDR, PMIC_RG_VPROC_CSL_MASK,
	 PMIC_RG_VPROC_CSL_SHIFT},
	{PMIC_RG_VPROC_SLP, PMIC_RG_VPROC_SLP_ADDR, PMIC_RG_VPROC_SLP_MASK,
	 PMIC_RG_VPROC_SLP_SHIFT},
	{PMIC_RG_VPROC_ZX_OS, PMIC_RG_VPROC_ZX_OS_ADDR, PMIC_RG_VPROC_ZX_OS_MASK,
	 PMIC_RG_VPROC_ZX_OS_SHIFT},
	{PMIC_RG_VPROC_ZXOS_TRIM, PMIC_RG_VPROC_ZXOS_TRIM_ADDR,
	 PMIC_RG_VPROC_ZXOS_TRIM_MASK, PMIC_RG_VPROC_ZXOS_TRIM_SHIFT},
	{PMIC_RG_VPROC_MODESET, PMIC_RG_VPROC_MODESET_ADDR,
	 PMIC_RG_VPROC_MODESET_MASK, PMIC_RG_VPROC_MODESET_SHIFT},
	{PMIC_RG_VPROC_NDIS_EN, PMIC_RG_VPROC_NDIS_EN_ADDR,
	 PMIC_RG_VPROC_NDIS_EN_MASK, PMIC_RG_VPROC_NDIS_EN_SHIFT},
	{PMIC_RG_VPROC_CSM_N, PMIC_RG_VPROC_CSM_N_ADDR, PMIC_RG_VPROC_CSM_N_MASK,
	 PMIC_RG_VPROC_CSM_N_SHIFT},
	{PMIC_RG_VPROC_CSM_P, PMIC_RG_VPROC_CSM_P_ADDR, PMIC_RG_VPROC_CSM_P_MASK,
	 PMIC_RG_VPROC_CSM_P_SHIFT},
	{PMIC_RG_VPROC_RSV, PMIC_RG_VPROC_RSV_ADDR, PMIC_RG_VPROC_RSV_MASK,
	 PMIC_RG_VPROC_RSV_SHIFT},
	{PMIC_RG_VPROC_PFM_RIP, PMIC_RG_VPROC_PFM_RIP_ADDR,
	 PMIC_RG_VPROC_PFM_RIP_MASK, PMIC_RG_VPROC_PFM_RIP_SHIFT},
	{PMIC_RG_VPROC_DTS_ENB, PMIC_RG_VPROC_DTS_ENB_ADDR,
	 PMIC_RG_VPROC_DTS_ENB_MASK, PMIC_RG_VPROC_DTS_ENB_SHIFT},
	{PMIC_RG_VPROC_BW_EXTEND, PMIC_RG_VPROC_BW_EXTEND_ADDR,
	 PMIC_RG_VPROC_BW_EXTEND_MASK, PMIC_RG_VPROC_BW_EXTEND_SHIFT},
	{PMIC_RG_VPROC_PWM_TRIG, PMIC_RG_VPROC_PWM_TRIG_ADDR,
	 PMIC_RG_VPROC_PWM_TRIG_MASK, PMIC_RG_VPROC_PWM_TRIG_SHIFT},
	{PMIC_RG_VPROC_TRAN_BST, PMIC_RG_VPROC_TRAN_BST_ADDR,
	 PMIC_RG_VPROC_TRAN_BST_MASK, PMIC_RG_VPROC_TRAN_BST_SHIFT},
	{PMIC_RGS_VPROC_ENPWM_STATUS, PMIC_RGS_VPROC_ENPWM_STATUS_ADDR,
	 PMIC_RGS_VPROC_ENPWM_STATUS_MASK, PMIC_RGS_VPROC_ENPWM_STATUS_SHIFT},
	{PMIC_RG_VS1_MIN_OFF, PMIC_RG_VS1_MIN_OFF_ADDR, PMIC_RG_VS1_MIN_OFF_MASK,
	 PMIC_RG_VS1_MIN_OFF_SHIFT},
	{PMIC_RG_VS1_NVT_BUFF_OFF_EN, PMIC_RG_VS1_NVT_BUFF_OFF_EN_ADDR,
	 PMIC_RG_VS1_NVT_BUFF_OFF_EN_MASK, PMIC_RG_VS1_NVT_BUFF_OFF_EN_SHIFT},
	{PMIC_RG_VS1_VRF18_SSTART_EN, PMIC_RG_VS1_VRF18_SSTART_EN_ADDR,
	 PMIC_RG_VS1_VRF18_SSTART_EN_MASK, PMIC_RG_VS1_VRF18_SSTART_EN_SHIFT},
	{PMIC_RG_VS1_1P35UP_SEL_EN, PMIC_RG_VS1_1P35UP_SEL_EN_ADDR,
	 PMIC_RG_VS1_1P35UP_SEL_EN_MASK, PMIC_RG_VS1_1P35UP_SEL_EN_SHIFT},
	{PMIC_RG_VS1_RZSEL, PMIC_RG_VS1_RZSEL_ADDR, PMIC_RG_VS1_RZSEL_MASK,
	 PMIC_RG_VS1_RZSEL_SHIFT},
	{PMIC_RG_VS1_CSR, PMIC_RG_VS1_CSR_ADDR, PMIC_RG_VS1_CSR_MASK,
	 PMIC_RG_VS1_CSR_SHIFT},
	{PMIC_RG_VS1_CSL, PMIC_RG_VS1_CSL_ADDR, PMIC_RG_VS1_CSL_MASK,
	 PMIC_RG_VS1_CSL_SHIFT},
	{PMIC_RG_VS1_SLP, PMIC_RG_VS1_SLP_ADDR, PMIC_RG_VS1_SLP_MASK,
	 PMIC_RG_VS1_SLP_SHIFT},
	{PMIC_RG_VS1_ZX_OS, PMIC_RG_VS1_ZX_OS_ADDR, PMIC_RG_VS1_ZX_OS_MASK,
	 PMIC_RG_VS1_ZX_OS_SHIFT},
	{PMIC_RG_VS1_NDIS_EN, PMIC_RG_VS1_NDIS_EN_ADDR, PMIC_RG_VS1_NDIS_EN_MASK,
	 PMIC_RG_VS1_NDIS_EN_SHIFT},
	{PMIC_RG_VS1_CSM_N, PMIC_RG_VS1_CSM_N_ADDR, PMIC_RG_VS1_CSM_N_MASK,
	 PMIC_RG_VS1_CSM_N_SHIFT},
	{PMIC_RG_VS1_CSM_P, PMIC_RG_VS1_CSM_P_ADDR, PMIC_RG_VS1_CSM_P_MASK,
	 PMIC_RG_VS1_CSM_P_SHIFT},
	{PMIC_RG_VS1_RSV, PMIC_RG_VS1_RSV_ADDR, PMIC_RG_VS1_RSV_MASK,
	 PMIC_RG_VS1_RSV_SHIFT},
	{PMIC_RG_VS1_ZXOS_TRIM, PMIC_RG_VS1_ZXOS_TRIM_ADDR,
	 PMIC_RG_VS1_ZXOS_TRIM_MASK, PMIC_RG_VS1_ZXOS_TRIM_SHIFT},
	{PMIC_RG_VS1_MODESET, PMIC_RG_VS1_MODESET_ADDR, PMIC_RG_VS1_MODESET_MASK,
	 PMIC_RG_VS1_MODESET_SHIFT},
	{PMIC_RG_VS1_PFM_RIP, PMIC_RG_VS1_PFM_RIP_ADDR, PMIC_RG_VS1_PFM_RIP_MASK,
	 PMIC_RG_VS1_PFM_RIP_SHIFT},
	{PMIC_RG_VS1_TRAN_BST, PMIC_RG_VS1_TRAN_BST_ADDR, PMIC_RG_VS1_TRAN_BST_MASK,
	 PMIC_RG_VS1_TRAN_BST_SHIFT},
	{PMIC_RG_VS1_DTS_ENB, PMIC_RG_VS1_DTS_ENB_ADDR, PMIC_RG_VS1_DTS_ENB_MASK,
	 PMIC_RG_VS1_DTS_ENB_SHIFT},
	{PMIC_RG_VS1_AUTO_MODE, PMIC_RG_VS1_AUTO_MODE_ADDR,
	 PMIC_RG_VS1_AUTO_MODE_MASK, PMIC_RG_VS1_AUTO_MODE_SHIFT},
	{PMIC_RG_VS1_PWM_TRIG, PMIC_RG_VS1_PWM_TRIG_ADDR, PMIC_RG_VS1_PWM_TRIG_MASK,
	 PMIC_RG_VS1_PWM_TRIG_SHIFT},
	{PMIC_RGS_VS1_ENPWM_STATUS, PMIC_RGS_VS1_ENPWM_STATUS_ADDR,
	 PMIC_RGS_VS1_ENPWM_STATUS_MASK, PMIC_RGS_VS1_ENPWM_STATUS_SHIFT},
	{PMIC_DA_QI_VCORE_BURST, PMIC_DA_QI_VCORE_BURST_ADDR,
	 PMIC_DA_QI_VCORE_BURST_MASK, PMIC_DA_QI_VCORE_BURST_SHIFT},
	{PMIC_DA_QI_VCORE2_BURST, PMIC_DA_QI_VCORE2_BURST_ADDR,
	 PMIC_DA_QI_VCORE2_BURST_MASK, PMIC_DA_QI_VCORE2_BURST_SHIFT},
	{PMIC_DA_QI_VS1_BURST, PMIC_DA_QI_VS1_BURST_ADDR, PMIC_DA_QI_VS1_BURST_MASK,
	 PMIC_DA_QI_VS1_BURST_SHIFT},
	{PMIC_DA_QI_VPROC_BURST, PMIC_DA_QI_VPROC_BURST_ADDR,
	 PMIC_DA_QI_VPROC_BURST_MASK, PMIC_DA_QI_VPROC_BURST_SHIFT},
	{PMIC_DA_QI_VCORE_DLC, PMIC_DA_QI_VCORE_DLC_ADDR, PMIC_DA_QI_VCORE_DLC_MASK,
	 PMIC_DA_QI_VCORE_DLC_SHIFT},
	{PMIC_DA_QI_VCORE_DLC_N, PMIC_DA_QI_VCORE_DLC_N_ADDR,
	 PMIC_DA_QI_VCORE_DLC_N_MASK, PMIC_DA_QI_VCORE_DLC_N_SHIFT},
	{PMIC_DA_QI_VCORE2_DLC, PMIC_DA_QI_VCORE2_DLC_ADDR,
	 PMIC_DA_QI_VCORE2_DLC_MASK, PMIC_DA_QI_VCORE2_DLC_SHIFT},
	{PMIC_DA_QI_VCORE2_DLC_N, PMIC_DA_QI_VCORE2_DLC_N_ADDR,
	 PMIC_DA_QI_VCORE2_DLC_N_MASK, PMIC_DA_QI_VCORE2_DLC_N_SHIFT},
	{PMIC_DA_QI_VS1_DLC, PMIC_DA_QI_VS1_DLC_ADDR, PMIC_DA_QI_VS1_DLC_MASK,
	 PMIC_DA_QI_VS1_DLC_SHIFT},
	{PMIC_DA_QI_VS1_DLC_N, PMIC_DA_QI_VS1_DLC_N_ADDR, PMIC_DA_QI_VS1_DLC_N_MASK,
	 PMIC_DA_QI_VS1_DLC_N_SHIFT},
	{PMIC_DA_QI_VPROC_DLC, PMIC_DA_QI_VPROC_DLC_ADDR, PMIC_DA_QI_VPROC_DLC_MASK,
	 PMIC_DA_QI_VPROC_DLC_SHIFT},
	{PMIC_DA_QI_VPROC_DLC_N, PMIC_DA_QI_VPROC_DLC_N_ADDR,
	 PMIC_DA_QI_VPROC_DLC_N_MASK, PMIC_DA_QI_VPROC_DLC_N_SHIFT},
	{PMIC_RG_VCORE2_MIN_OFF, PMIC_RG_VCORE2_MIN_OFF_ADDR,
	 PMIC_RG_VCORE2_MIN_OFF_MASK, PMIC_RG_VCORE2_MIN_OFF_SHIFT},
	{PMIC_RG_VCORE2_VRF18_SSTART_EN, PMIC_RG_VCORE2_VRF18_SSTART_EN_ADDR,
	 PMIC_RG_VCORE2_VRF18_SSTART_EN_MASK, PMIC_RG_VCORE2_VRF18_SSTART_EN_SHIFT},
	{PMIC_RG_VCORE2_1P35UP_SEL_EN, PMIC_RG_VCORE2_1P35UP_SEL_EN_ADDR,
	 PMIC_RG_VCORE2_1P35UP_SEL_EN_MASK, PMIC_RG_VCORE2_1P35UP_SEL_EN_SHIFT},
	{PMIC_RG_VCORE2_RZSEL, PMIC_RG_VCORE2_RZSEL_ADDR, PMIC_RG_VCORE2_RZSEL_MASK,
	 PMIC_RG_VCORE2_RZSEL_SHIFT},
	{PMIC_RG_VCORE2_CSR, PMIC_RG_VCORE2_CSR_ADDR, PMIC_RG_VCORE2_CSR_MASK,
	 PMIC_RG_VCORE2_CSR_SHIFT},
	{PMIC_RG_VCORE2_CSL, PMIC_RG_VCORE2_CSL_ADDR, PMIC_RG_VCORE2_CSL_MASK,
	 PMIC_RG_VCORE2_CSL_SHIFT},
	{PMIC_RG_VCORE2_SLP, PMIC_RG_VCORE2_SLP_ADDR, PMIC_RG_VCORE2_SLP_MASK,
	 PMIC_RG_VCORE2_SLP_SHIFT},
	{PMIC_RG_VCORE2_ZX_OS, PMIC_RG_VCORE2_ZX_OS_ADDR, PMIC_RG_VCORE2_ZX_OS_MASK,
	 PMIC_RG_VCORE2_ZX_OS_SHIFT},
	{PMIC_RG_VCORE2_ZXOS_TRIM, PMIC_RG_VCORE2_ZXOS_TRIM_ADDR,
	 PMIC_RG_VCORE2_ZXOS_TRIM_MASK, PMIC_RG_VCORE2_ZXOS_TRIM_SHIFT},
	{PMIC_RG_VCORE2_MODESET, PMIC_RG_VCORE2_MODESET_ADDR,
	 PMIC_RG_VCORE2_MODESET_MASK, PMIC_RG_VCORE2_MODESET_SHIFT},
	{PMIC_RG_VCORE2_NDIS_EN, PMIC_RG_VCORE2_NDIS_EN_ADDR,
	 PMIC_RG_VCORE2_NDIS_EN_MASK, PMIC_RG_VCORE2_NDIS_EN_SHIFT},
	{PMIC_RG_VCORE2_CSM_N, PMIC_RG_VCORE2_CSM_N_ADDR, PMIC_RG_VCORE2_CSM_N_MASK,
	 PMIC_RG_VCORE2_CSM_N_SHIFT},
	{PMIC_RG_VCORE2_CSM_P, PMIC_RG_VCORE2_CSM_P_ADDR, PMIC_RG_VCORE2_CSM_P_MASK,
	 PMIC_RG_VCORE2_CSM_P_SHIFT},
	{PMIC_RG_VCORE2_RSV, PMIC_RG_VCORE2_RSV_ADDR, PMIC_RG_VCORE2_RSV_MASK,
	 PMIC_RG_VCORE2_RSV_SHIFT},
	{PMIC_RG_VCORE2_PFM_RIP, PMIC_RG_VCORE2_PFM_RIP_ADDR,
	 PMIC_RG_VCORE2_PFM_RIP_MASK, PMIC_RG_VCORE2_PFM_RIP_SHIFT},
	{PMIC_RG_VCORE2_DTS_ENB, PMIC_RG_VCORE2_DTS_ENB_ADDR,
	 PMIC_RG_VCORE2_DTS_ENB_MASK, PMIC_RG_VCORE2_DTS_ENB_SHIFT},
	{PMIC_RG_VCORE2_AUTO_MODE, PMIC_RG_VCORE2_AUTO_MODE_ADDR,
	 PMIC_RG_VCORE2_AUTO_MODE_MASK, PMIC_RG_VCORE2_AUTO_MODE_SHIFT},
	{PMIC_RG_VCORE2_PWM_TRIG, PMIC_RG_VCORE2_PWM_TRIG_ADDR,
	 PMIC_RG_VCORE2_PWM_TRIG_MASK, PMIC_RG_VCORE2_PWM_TRIG_SHIFT},
	{PMIC_RG_VCORE2_TRAN_BST, PMIC_RG_VCORE2_TRAN_BST_ADDR,
	 PMIC_RG_VCORE2_TRAN_BST_MASK, PMIC_RG_VCORE2_TRAN_BST_SHIFT},
	{PMIC_RGS_VCORE2_ENPWM_STATUS, PMIC_RGS_VCORE2_ENPWM_STATUS_ADDR,
	 PMIC_RGS_VCORE2_ENPWM_STATUS_MASK, PMIC_RGS_VCORE2_ENPWM_STATUS_SHIFT},
	{PMIC_BUCK_VPROC_EN_CTRL, PMIC_BUCK_VPROC_EN_CTRL_ADDR,
	 PMIC_BUCK_VPROC_EN_CTRL_MASK, PMIC_BUCK_VPROC_EN_CTRL_SHIFT},
	{PMIC_BUCK_VPROC_VOSEL_CTRL, PMIC_BUCK_VPROC_VOSEL_CTRL_ADDR,
	 PMIC_BUCK_VPROC_VOSEL_CTRL_MASK, PMIC_BUCK_VPROC_VOSEL_CTRL_SHIFT},
	{PMIC_BUCK_VPROC_EN_SEL, PMIC_BUCK_VPROC_EN_SEL_ADDR,
	 PMIC_BUCK_VPROC_EN_SEL_MASK, PMIC_BUCK_VPROC_EN_SEL_SHIFT},
	{PMIC_BUCK_VPROC_VOSEL_SEL, PMIC_BUCK_VPROC_VOSEL_SEL_ADDR,
	 PMIC_BUCK_VPROC_VOSEL_SEL_MASK, PMIC_BUCK_VPROC_VOSEL_SEL_SHIFT},
	{PMIC_BUCK_VPROC_EN, PMIC_BUCK_VPROC_EN_ADDR, PMIC_BUCK_VPROC_EN_MASK,
	 PMIC_BUCK_VPROC_EN_SHIFT},
	{PMIC_BUCK_VPROC_STBTD, PMIC_BUCK_VPROC_STBTD_ADDR,
	 PMIC_BUCK_VPROC_STBTD_MASK, PMIC_BUCK_VPROC_STBTD_SHIFT},
	{PMIC_DA_VPROC_STB, PMIC_DA_VPROC_STB_ADDR, PMIC_DA_VPROC_STB_MASK,
	 PMIC_DA_VPROC_STB_SHIFT},
	{PMIC_DA_QI_VPROC_EN, PMIC_DA_QI_VPROC_EN_ADDR, PMIC_DA_QI_VPROC_EN_MASK,
	 PMIC_DA_QI_VPROC_EN_SHIFT},
	{PMIC_BUCK_VPROC_SFCHG_FRATE, PMIC_BUCK_VPROC_SFCHG_FRATE_ADDR,
	 PMIC_BUCK_VPROC_SFCHG_FRATE_MASK, PMIC_BUCK_VPROC_SFCHG_FRATE_SHIFT},
	{PMIC_BUCK_VPROC_SFCHG_FEN, PMIC_BUCK_VPROC_SFCHG_FEN_ADDR,
	 PMIC_BUCK_VPROC_SFCHG_FEN_MASK, PMIC_BUCK_VPROC_SFCHG_FEN_SHIFT},
	{PMIC_BUCK_VPROC_SFCHG_RRATE, PMIC_BUCK_VPROC_SFCHG_RRATE_ADDR,
	 PMIC_BUCK_VPROC_SFCHG_RRATE_MASK, PMIC_BUCK_VPROC_SFCHG_RRATE_SHIFT},
	{PMIC_BUCK_VPROC_SFCHG_REN, PMIC_BUCK_VPROC_SFCHG_REN_ADDR,
	 PMIC_BUCK_VPROC_SFCHG_REN_MASK, PMIC_BUCK_VPROC_SFCHG_REN_SHIFT},
	{PMIC_DA_NI_VPROC_VOSEL, PMIC_DA_NI_VPROC_VOSEL_ADDR,
	 PMIC_DA_NI_VPROC_VOSEL_MASK, PMIC_DA_NI_VPROC_VOSEL_SHIFT},
	{PMIC_BUCK_VPROC_VOSEL, PMIC_BUCK_VPROC_VOSEL_ADDR,
	 PMIC_BUCK_VPROC_VOSEL_MASK, PMIC_BUCK_VPROC_VOSEL_SHIFT},
	{PMIC_BUCK_VPROC_VOSEL_ON, PMIC_BUCK_VPROC_VOSEL_ON_ADDR,
	 PMIC_BUCK_VPROC_VOSEL_ON_MASK, PMIC_BUCK_VPROC_VOSEL_ON_SHIFT},
	{PMIC_BUCK_VPROC_VOSEL_SLEEP, PMIC_BUCK_VPROC_VOSEL_SLEEP_ADDR,
	 PMIC_BUCK_VPROC_VOSEL_SLEEP_MASK, PMIC_BUCK_VPROC_VOSEL_SLEEP_SHIFT},
	{PMIC_BUCK_VPROC_TRANS_TD, PMIC_BUCK_VPROC_TRANS_TD_ADDR,
	 PMIC_BUCK_VPROC_TRANS_TD_MASK, PMIC_BUCK_VPROC_TRANS_TD_SHIFT},
	{PMIC_BUCK_VPROC_TRANS_CTRL, PMIC_BUCK_VPROC_TRANS_CTRL_ADDR,
	 PMIC_BUCK_VPROC_TRANS_CTRL_MASK, PMIC_BUCK_VPROC_TRANS_CTRL_SHIFT},
	{PMIC_BUCK_VPROC_TRANS_ONCE, PMIC_BUCK_VPROC_TRANS_ONCE_ADDR,
	 PMIC_BUCK_VPROC_TRANS_ONCE_MASK, PMIC_BUCK_VPROC_TRANS_ONCE_SHIFT},
	{PMIC_DA_QI_VPROC_DVS_EN, PMIC_DA_QI_VPROC_DVS_EN_ADDR,
	 PMIC_DA_QI_VPROC_DVS_EN_MASK, PMIC_DA_QI_VPROC_DVS_EN_SHIFT},
	{PMIC_BUCK_VPROC_VSLEEP_EN, PMIC_BUCK_VPROC_VSLEEP_EN_ADDR,
	 PMIC_BUCK_VPROC_VSLEEP_EN_MASK, PMIC_BUCK_VPROC_VSLEEP_EN_SHIFT},
	{PMIC_BUCK_VPROC_R2R_PDN, PMIC_BUCK_VPROC_R2R_PDN_ADDR,
	 PMIC_BUCK_VPROC_R2R_PDN_MASK, PMIC_BUCK_VPROC_R2R_PDN_SHIFT},
	{PMIC_BUCK_VPROC_VSLEEP_SEL, PMIC_BUCK_VPROC_VSLEEP_SEL_ADDR,
	 PMIC_BUCK_VPROC_VSLEEP_SEL_MASK, PMIC_BUCK_VPROC_VSLEEP_SEL_SHIFT},
	{PMIC_DA_NI_VPROC_R2R_PDN, PMIC_DA_NI_VPROC_R2R_PDN_ADDR,
	 PMIC_DA_NI_VPROC_R2R_PDN_MASK, PMIC_DA_NI_VPROC_R2R_PDN_SHIFT},
	{PMIC_DA_NI_VPROC_VSLEEP_SEL, PMIC_DA_NI_VPROC_VSLEEP_SEL_ADDR,
	 PMIC_DA_NI_VPROC_VSLEEP_SEL_MASK, PMIC_DA_NI_VPROC_VSLEEP_SEL_SHIFT},
	{PMIC_BUCK_VS1_EN_CTRL, PMIC_BUCK_VS1_EN_CTRL_ADDR,
	 PMIC_BUCK_VS1_EN_CTRL_MASK, PMIC_BUCK_VS1_EN_CTRL_SHIFT},
	{PMIC_BUCK_VS1_VOSEL_CTRL, PMIC_BUCK_VS1_VOSEL_CTRL_ADDR,
	 PMIC_BUCK_VS1_VOSEL_CTRL_MASK, PMIC_BUCK_VS1_VOSEL_CTRL_SHIFT},
	{PMIC_BUCK_VS1_VOSEL_CTRL_0, PMIC_BUCK_VS1_VOSEL_CTRL_0_ADDR,
	 PMIC_BUCK_VS1_VOSEL_CTRL_0_MASK, PMIC_BUCK_VS1_VOSEL_CTRL_0_SHIFT},
	{PMIC_BUCK_VS1_VOSEL_CTRL_1, PMIC_BUCK_VS1_VOSEL_CTRL_1_ADDR,
	 PMIC_BUCK_VS1_VOSEL_CTRL_1_MASK, PMIC_BUCK_VS1_VOSEL_CTRL_1_SHIFT},
	{PMIC_BUCK_VS1_VOSEL_CTRL_2, PMIC_BUCK_VS1_VOSEL_CTRL_2_ADDR,
	 PMIC_BUCK_VS1_VOSEL_CTRL_2_MASK, PMIC_BUCK_VS1_VOSEL_CTRL_2_SHIFT},
	{PMIC_BUCK_VS1_MODESET_0, PMIC_BUCK_VS1_MODESET_0_ADDR,
	 PMIC_BUCK_VS1_MODESET_0_MASK, PMIC_BUCK_VS1_MODESET_0_SHIFT},
	{PMIC_BUCK_VS1_MODESET_1, PMIC_BUCK_VS1_MODESET_1_ADDR,
	 PMIC_BUCK_VS1_MODESET_1_MASK, PMIC_BUCK_VS1_MODESET_1_SHIFT},
	{PMIC_BUCK_VS1_MODESET_2, PMIC_BUCK_VS1_MODESET_2_ADDR,
	 PMIC_BUCK_VS1_MODESET_2_MASK, PMIC_BUCK_VS1_MODESET_2_SHIFT},
	{PMIC_DA_VS1_MODESET, PMIC_DA_VS1_MODESET_ADDR, PMIC_DA_VS1_MODESET_MASK,
	 PMIC_DA_VS1_MODESET_SHIFT},
	{PMIC_BUCK_VS1_VOSEL_CTRL_INV, PMIC_BUCK_VS1_VOSEL_CTRL_INV_ADDR,
	 PMIC_BUCK_VS1_VOSEL_CTRL_INV_MASK, PMIC_BUCK_VS1_VOSEL_CTRL_INV_SHIFT},
	{PMIC_BUCK_VS1_HWM_CON0_SET, PMIC_BUCK_VS1_HWM_CON0_SET_ADDR,
	 PMIC_BUCK_VS1_HWM_CON0_SET_MASK, PMIC_BUCK_VS1_HWM_CON0_SET_SHIFT},
	{PMIC_BUCK_VS1_HWM_CON0_CLR, PMIC_BUCK_VS1_HWM_CON0_CLR_ADDR,
	 PMIC_BUCK_VS1_HWM_CON0_CLR_MASK, PMIC_BUCK_VS1_HWM_CON0_CLR_SHIFT},
	{PMIC_BUCK_VS1_EN_SEL, PMIC_BUCK_VS1_EN_SEL_ADDR, PMIC_BUCK_VS1_EN_SEL_MASK,
	 PMIC_BUCK_VS1_EN_SEL_SHIFT},
	{PMIC_BUCK_VS1_VOSEL_SEL, PMIC_BUCK_VS1_VOSEL_SEL_ADDR,
	 PMIC_BUCK_VS1_VOSEL_SEL_MASK, PMIC_BUCK_VS1_VOSEL_SEL_SHIFT},
	{PMIC_BUCK_VS1_EN, PMIC_BUCK_VS1_EN_ADDR, PMIC_BUCK_VS1_EN_MASK,
	 PMIC_BUCK_VS1_EN_SHIFT},
	{PMIC_BUCK_VS1_STBTD, PMIC_BUCK_VS1_STBTD_ADDR, PMIC_BUCK_VS1_STBTD_MASK,
	 PMIC_BUCK_VS1_STBTD_SHIFT},
	{PMIC_DA_VS1_STB, PMIC_DA_VS1_STB_ADDR, PMIC_DA_VS1_STB_MASK,
	 PMIC_DA_VS1_STB_SHIFT},
	{PMIC_DA_QI_VS1_EN, PMIC_DA_QI_VS1_EN_ADDR, PMIC_DA_QI_VS1_EN_MASK,
	 PMIC_DA_QI_VS1_EN_SHIFT},
	{PMIC_BUCK_VS1_SFCHG_FRATE, PMIC_BUCK_VS1_SFCHG_FRATE_ADDR,
	 PMIC_BUCK_VS1_SFCHG_FRATE_MASK, PMIC_BUCK_VS1_SFCHG_FRATE_SHIFT},
	{PMIC_BUCK_VS1_SFCHG_FEN, PMIC_BUCK_VS1_SFCHG_FEN_ADDR,
	 PMIC_BUCK_VS1_SFCHG_FEN_MASK, PMIC_BUCK_VS1_SFCHG_FEN_SHIFT},
	{PMIC_BUCK_VS1_SFCHG_RRATE, PMIC_BUCK_VS1_SFCHG_RRATE_ADDR,
	 PMIC_BUCK_VS1_SFCHG_RRATE_MASK, PMIC_BUCK_VS1_SFCHG_RRATE_SHIFT},
	{PMIC_BUCK_VS1_SFCHG_REN, PMIC_BUCK_VS1_SFCHG_REN_ADDR,
	 PMIC_BUCK_VS1_SFCHG_REN_MASK, PMIC_BUCK_VS1_SFCHG_REN_SHIFT},
	{PMIC_DA_NI_VS1_VOSEL, PMIC_DA_NI_VS1_VOSEL_ADDR, PMIC_DA_NI_VS1_VOSEL_MASK,
	 PMIC_DA_NI_VS1_VOSEL_SHIFT},
	{PMIC_BUCK_VS1_VOSEL, PMIC_BUCK_VS1_VOSEL_ADDR, PMIC_BUCK_VS1_VOSEL_MASK,
	 PMIC_BUCK_VS1_VOSEL_SHIFT},
	{PMIC_BUCK_VS1_VOSEL_ON, PMIC_BUCK_VS1_VOSEL_ON_ADDR,
	 PMIC_BUCK_VS1_VOSEL_ON_MASK, PMIC_BUCK_VS1_VOSEL_ON_SHIFT},
	{PMIC_BUCK_VS1_VOSEL_SLEEP, PMIC_BUCK_VS1_VOSEL_SLEEP_ADDR,
	 PMIC_BUCK_VS1_VOSEL_SLEEP_MASK, PMIC_BUCK_VS1_VOSEL_SLEEP_SHIFT},
	{PMIC_BUCK_VS1_TRANS_TD, PMIC_BUCK_VS1_TRANS_TD_ADDR,
	 PMIC_BUCK_VS1_TRANS_TD_MASK, PMIC_BUCK_VS1_TRANS_TD_SHIFT},
	{PMIC_BUCK_VS1_TRANS_CTRL, PMIC_BUCK_VS1_TRANS_CTRL_ADDR,
	 PMIC_BUCK_VS1_TRANS_CTRL_MASK, PMIC_BUCK_VS1_TRANS_CTRL_SHIFT},
	{PMIC_BUCK_VS1_TRANS_ONCE, PMIC_BUCK_VS1_TRANS_ONCE_ADDR,
	 PMIC_BUCK_VS1_TRANS_ONCE_MASK, PMIC_BUCK_VS1_TRANS_ONCE_SHIFT},
	{PMIC_DA_QI_VS1_DVS_EN, PMIC_DA_QI_VS1_DVS_EN_ADDR,
	 PMIC_DA_QI_VS1_DVS_EN_MASK, PMIC_DA_QI_VS1_DVS_EN_SHIFT},
	{PMIC_BUCK_VS1_VSLEEP_EN, PMIC_BUCK_VS1_VSLEEP_EN_ADDR,
	 PMIC_BUCK_VS1_VSLEEP_EN_MASK, PMIC_BUCK_VS1_VSLEEP_EN_SHIFT},
	{PMIC_BUCK_VS1_R2R_PDN, PMIC_BUCK_VS1_R2R_PDN_ADDR,
	 PMIC_BUCK_VS1_R2R_PDN_MASK, PMIC_BUCK_VS1_R2R_PDN_SHIFT},
	{PMIC_BUCK_VS1_VSLEEP_SEL, PMIC_BUCK_VS1_VSLEEP_SEL_ADDR,
	 PMIC_BUCK_VS1_VSLEEP_SEL_MASK, PMIC_BUCK_VS1_VSLEEP_SEL_SHIFT},
	{PMIC_DA_NI_VS1_R2R_PDN, PMIC_DA_NI_VS1_R2R_PDN_ADDR,
	 PMIC_DA_NI_VS1_R2R_PDN_MASK, PMIC_DA_NI_VS1_R2R_PDN_SHIFT},
	{PMIC_DA_NI_VS1_VSLEEP_SEL, PMIC_DA_NI_VS1_VSLEEP_SEL_ADDR,
	 PMIC_DA_NI_VS1_VSLEEP_SEL_MASK, PMIC_DA_NI_VS1_VSLEEP_SEL_SHIFT},
	{PMIC_BUCK_VCORE_EN_CTRL, PMIC_BUCK_VCORE_EN_CTRL_ADDR,
	 PMIC_BUCK_VCORE_EN_CTRL_MASK, PMIC_BUCK_VCORE_EN_CTRL_SHIFT},
	{PMIC_BUCK_VCORE_VOSEL_CTRL, PMIC_BUCK_VCORE_VOSEL_CTRL_ADDR,
	 PMIC_BUCK_VCORE_VOSEL_CTRL_MASK, PMIC_BUCK_VCORE_VOSEL_CTRL_SHIFT},
	{PMIC_BUCK_VCORE_EN_SEL, PMIC_BUCK_VCORE_EN_SEL_ADDR,
	 PMIC_BUCK_VCORE_EN_SEL_MASK, PMIC_BUCK_VCORE_EN_SEL_SHIFT},
	{PMIC_BUCK_VCORE_VOSEL_SEL, PMIC_BUCK_VCORE_VOSEL_SEL_ADDR,
	 PMIC_BUCK_VCORE_VOSEL_SEL_MASK, PMIC_BUCK_VCORE_VOSEL_SEL_SHIFT},
	{PMIC_BUCK_VCORE_EN, PMIC_BUCK_VCORE_EN_ADDR, PMIC_BUCK_VCORE_EN_MASK,
	 PMIC_BUCK_VCORE_EN_SHIFT},
	{PMIC_BUCK_VCORE_STBTD, PMIC_BUCK_VCORE_STBTD_ADDR,
	 PMIC_BUCK_VCORE_STBTD_MASK, PMIC_BUCK_VCORE_STBTD_SHIFT},
	{PMIC_DA_VCORE_STB, PMIC_DA_VCORE_STB_ADDR, PMIC_DA_VCORE_STB_MASK,
	 PMIC_DA_VCORE_STB_SHIFT},
	{PMIC_DA_QI_VCORE_EN, PMIC_DA_QI_VCORE_EN_ADDR, PMIC_DA_QI_VCORE_EN_MASK,
	 PMIC_DA_QI_VCORE_EN_SHIFT},
	{PMIC_BUCK_VCORE_SFCHG_FRATE, PMIC_BUCK_VCORE_SFCHG_FRATE_ADDR,
	 PMIC_BUCK_VCORE_SFCHG_FRATE_MASK, PMIC_BUCK_VCORE_SFCHG_FRATE_SHIFT},
	{PMIC_BUCK_VCORE_SFCHG_FEN, PMIC_BUCK_VCORE_SFCHG_FEN_ADDR,
	 PMIC_BUCK_VCORE_SFCHG_FEN_MASK, PMIC_BUCK_VCORE_SFCHG_FEN_SHIFT},
	{PMIC_BUCK_VCORE_SFCHG_RRATE, PMIC_BUCK_VCORE_SFCHG_RRATE_ADDR,
	 PMIC_BUCK_VCORE_SFCHG_RRATE_MASK, PMIC_BUCK_VCORE_SFCHG_RRATE_SHIFT},
	{PMIC_BUCK_VCORE_SFCHG_REN, PMIC_BUCK_VCORE_SFCHG_REN_ADDR,
	 PMIC_BUCK_VCORE_SFCHG_REN_MASK, PMIC_BUCK_VCORE_SFCHG_REN_SHIFT},
	{PMIC_DA_NI_VCORE_VOSEL, PMIC_DA_NI_VCORE_VOSEL_ADDR,
	 PMIC_DA_NI_VCORE_VOSEL_MASK, PMIC_DA_NI_VCORE_VOSEL_SHIFT},
	{PMIC_BUCK_VCORE_VOSEL, PMIC_BUCK_VCORE_VOSEL_ADDR,
	 PMIC_BUCK_VCORE_VOSEL_MASK, PMIC_BUCK_VCORE_VOSEL_SHIFT},
	{PMIC_BUCK_VCORE_VOSEL_ON, PMIC_BUCK_VCORE_VOSEL_ON_ADDR,
	 PMIC_BUCK_VCORE_VOSEL_ON_MASK, PMIC_BUCK_VCORE_VOSEL_ON_SHIFT},
	{PMIC_BUCK_VCORE_VOSEL_SLEEP, PMIC_BUCK_VCORE_VOSEL_SLEEP_ADDR,
	 PMIC_BUCK_VCORE_VOSEL_SLEEP_MASK, PMIC_BUCK_VCORE_VOSEL_SLEEP_SHIFT},
	{PMIC_BUCK_VCORE_TRANS_TD, PMIC_BUCK_VCORE_TRANS_TD_ADDR,
	 PMIC_BUCK_VCORE_TRANS_TD_MASK, PMIC_BUCK_VCORE_TRANS_TD_SHIFT},
	{PMIC_BUCK_VCORE_TRANS_CTRL, PMIC_BUCK_VCORE_TRANS_CTRL_ADDR,
	 PMIC_BUCK_VCORE_TRANS_CTRL_MASK, PMIC_BUCK_VCORE_TRANS_CTRL_SHIFT},
	{PMIC_BUCK_VCORE_TRANS_ONCE, PMIC_BUCK_VCORE_TRANS_ONCE_ADDR,
	 PMIC_BUCK_VCORE_TRANS_ONCE_MASK, PMIC_BUCK_VCORE_TRANS_ONCE_SHIFT},
	{PMIC_DA_QI_VCORE_DVS_EN, PMIC_DA_QI_VCORE_DVS_EN_ADDR,
	 PMIC_DA_QI_VCORE_DVS_EN_MASK, PMIC_DA_QI_VCORE_DVS_EN_SHIFT},
	{PMIC_BUCK_VCORE_VSLEEP_EN, PMIC_BUCK_VCORE_VSLEEP_EN_ADDR,
	 PMIC_BUCK_VCORE_VSLEEP_EN_MASK, PMIC_BUCK_VCORE_VSLEEP_EN_SHIFT},
	{PMIC_BUCK_VCORE_R2R_PDN, PMIC_BUCK_VCORE_R2R_PDN_ADDR,
	 PMIC_BUCK_VCORE_R2R_PDN_MASK, PMIC_BUCK_VCORE_R2R_PDN_SHIFT},
	{PMIC_BUCK_VCORE_VSLEEP_SEL, PMIC_BUCK_VCORE_VSLEEP_SEL_ADDR,
	 PMIC_BUCK_VCORE_VSLEEP_SEL_MASK, PMIC_BUCK_VCORE_VSLEEP_SEL_SHIFT},
	{PMIC_DA_NI_VCORE_R2R_PDN, PMIC_DA_NI_VCORE_R2R_PDN_ADDR,
	 PMIC_DA_NI_VCORE_R2R_PDN_MASK, PMIC_DA_NI_VCORE_R2R_PDN_SHIFT},
	{PMIC_DA_NI_VCORE_VSLEEP_SEL, PMIC_DA_NI_VCORE_VSLEEP_SEL_ADDR,
	 PMIC_DA_NI_VCORE_VSLEEP_SEL_MASK, PMIC_DA_NI_VCORE_VSLEEP_SEL_SHIFT},
	{PMIC_BUCK_VCORE2_EN_CTRL, PMIC_BUCK_VCORE2_EN_CTRL_ADDR,
	 PMIC_BUCK_VCORE2_EN_CTRL_MASK, PMIC_BUCK_VCORE2_EN_CTRL_SHIFT},
	{PMIC_BUCK_VCORE2_VOSEL_CTRL, PMIC_BUCK_VCORE2_VOSEL_CTRL_ADDR,
	 PMIC_BUCK_VCORE2_VOSEL_CTRL_MASK, PMIC_BUCK_VCORE2_VOSEL_CTRL_SHIFT},
	{PMIC_BUCK_VCORE2_EN_SEL, PMIC_BUCK_VCORE2_EN_SEL_ADDR,
	 PMIC_BUCK_VCORE2_EN_SEL_MASK, PMIC_BUCK_VCORE2_EN_SEL_SHIFT},
	{PMIC_BUCK_VCORE2_VOSEL_SEL, PMIC_BUCK_VCORE2_VOSEL_SEL_ADDR,
	 PMIC_BUCK_VCORE2_VOSEL_SEL_MASK, PMIC_BUCK_VCORE2_VOSEL_SEL_SHIFT},
	{PMIC_BUCK_VCORE2_EN, PMIC_BUCK_VCORE2_EN_ADDR, PMIC_BUCK_VCORE2_EN_MASK,
	 PMIC_BUCK_VCORE2_EN_SHIFT},
	{PMIC_BUCK_VCORE2_STBTD, PMIC_BUCK_VCORE2_STBTD_ADDR,
	 PMIC_BUCK_VCORE2_STBTD_MASK, PMIC_BUCK_VCORE2_STBTD_SHIFT},
	{PMIC_DA_VCORE2_STB, PMIC_DA_VCORE2_STB_ADDR, PMIC_DA_VCORE2_STB_MASK,
	 PMIC_DA_VCORE2_STB_SHIFT},
	{PMIC_DA_QI_VCORE2_EN, PMIC_DA_QI_VCORE2_EN_ADDR, PMIC_DA_QI_VCORE2_EN_MASK,
	 PMIC_DA_QI_VCORE2_EN_SHIFT},
	{PMIC_BUCK_VCORE2_SFCHG_FRATE, PMIC_BUCK_VCORE2_SFCHG_FRATE_ADDR,
	 PMIC_BUCK_VCORE2_SFCHG_FRATE_MASK, PMIC_BUCK_VCORE2_SFCHG_FRATE_SHIFT},
	{PMIC_BUCK_VCORE2_SFCHG_FEN, PMIC_BUCK_VCORE2_SFCHG_FEN_ADDR,
	 PMIC_BUCK_VCORE2_SFCHG_FEN_MASK, PMIC_BUCK_VCORE2_SFCHG_FEN_SHIFT},
	{PMIC_BUCK_VCORE2_SFCHG_RRATE, PMIC_BUCK_VCORE2_SFCHG_RRATE_ADDR,
	 PMIC_BUCK_VCORE2_SFCHG_RRATE_MASK, PMIC_BUCK_VCORE2_SFCHG_RRATE_SHIFT},
	{PMIC_BUCK_VCORE2_SFCHG_REN, PMIC_BUCK_VCORE2_SFCHG_REN_ADDR,
	 PMIC_BUCK_VCORE2_SFCHG_REN_MASK, PMIC_BUCK_VCORE2_SFCHG_REN_SHIFT},
	{PMIC_DA_NI_VCORE2_VOSEL, PMIC_DA_NI_VCORE2_VOSEL_ADDR,
	 PMIC_DA_NI_VCORE2_VOSEL_MASK, PMIC_DA_NI_VCORE2_VOSEL_SHIFT},
	{PMIC_BUCK_VCORE2_VOSEL, PMIC_BUCK_VCORE2_VOSEL_ADDR,
	 PMIC_BUCK_VCORE2_VOSEL_MASK, PMIC_BUCK_VCORE2_VOSEL_SHIFT},
	{PMIC_BUCK_VCORE2_VOSEL_ON, PMIC_BUCK_VCORE2_VOSEL_ON_ADDR,
	 PMIC_BUCK_VCORE2_VOSEL_ON_MASK, PMIC_BUCK_VCORE2_VOSEL_ON_SHIFT},
	{PMIC_BUCK_VCORE2_VOSEL_SLEEP, PMIC_BUCK_VCORE2_VOSEL_SLEEP_ADDR,
	 PMIC_BUCK_VCORE2_VOSEL_SLEEP_MASK, PMIC_BUCK_VCORE2_VOSEL_SLEEP_SHIFT},
	{PMIC_BUCK_VCORE2_TRANS_TD, PMIC_BUCK_VCORE2_TRANS_TD_ADDR,
	 PMIC_BUCK_VCORE2_TRANS_TD_MASK, PMIC_BUCK_VCORE2_TRANS_TD_SHIFT},
	{PMIC_BUCK_VCORE2_TRANS_CTRL, PMIC_BUCK_VCORE2_TRANS_CTRL_ADDR,
	 PMIC_BUCK_VCORE2_TRANS_CTRL_MASK, PMIC_BUCK_VCORE2_TRANS_CTRL_SHIFT},
	{PMIC_BUCK_VCORE2_TRANS_ONCE, PMIC_BUCK_VCORE2_TRANS_ONCE_ADDR,
	 PMIC_BUCK_VCORE2_TRANS_ONCE_MASK, PMIC_BUCK_VCORE2_TRANS_ONCE_SHIFT},
	{PMIC_DA_QI_VCORE2_DVS_EN, PMIC_DA_QI_VCORE2_DVS_EN_ADDR,
	 PMIC_DA_QI_VCORE2_DVS_EN_MASK, PMIC_DA_QI_VCORE2_DVS_EN_SHIFT},
	{PMIC_BUCK_VCORE2_VSLEEP_EN, PMIC_BUCK_VCORE2_VSLEEP_EN_ADDR,
	 PMIC_BUCK_VCORE2_VSLEEP_EN_MASK, PMIC_BUCK_VCORE2_VSLEEP_EN_SHIFT},
	{PMIC_BUCK_VCORE2_R2R_PDN, PMIC_BUCK_VCORE2_R2R_PDN_ADDR,
	 PMIC_BUCK_VCORE2_R2R_PDN_MASK, PMIC_BUCK_VCORE2_R2R_PDN_SHIFT},
	{PMIC_BUCK_VCORE2_VSLEEP_SEL, PMIC_BUCK_VCORE2_VSLEEP_SEL_ADDR,
	 PMIC_BUCK_VCORE2_VSLEEP_SEL_MASK, PMIC_BUCK_VCORE2_VSLEEP_SEL_SHIFT},
	{PMIC_DA_NI_VCORE2_R2R_PDN, PMIC_DA_NI_VCORE2_R2R_PDN_ADDR,
	 PMIC_DA_NI_VCORE2_R2R_PDN_MASK, PMIC_DA_NI_VCORE2_R2R_PDN_SHIFT},
	{PMIC_DA_NI_VCORE2_VSLEEP_SEL, PMIC_DA_NI_VCORE2_VSLEEP_SEL_ADDR,
	 PMIC_DA_NI_VCORE2_VSLEEP_SEL_MASK, PMIC_DA_NI_VCORE2_VSLEEP_SEL_SHIFT},
	{PMIC_BUCK_VPA_EN, PMIC_BUCK_VPA_EN_ADDR, PMIC_BUCK_VPA_EN_MASK,
	 PMIC_BUCK_VPA_EN_SHIFT},
	{PMIC_BUCK_VPA_STBTD, PMIC_BUCK_VPA_STBTD_ADDR, PMIC_BUCK_VPA_STBTD_MASK,
	 PMIC_BUCK_VPA_STBTD_SHIFT},
	{PMIC_DA_VPA_STB, PMIC_DA_VPA_STB_ADDR, PMIC_DA_VPA_STB_MASK,
	 PMIC_DA_VPA_STB_SHIFT},
	{PMIC_DA_QI_VPA_EN, PMIC_DA_QI_VPA_EN_ADDR, PMIC_DA_QI_VPA_EN_MASK,
	 PMIC_DA_QI_VPA_EN_SHIFT},
	{PMIC_BUCK_VPA_SFCHG_FRATE, PMIC_BUCK_VPA_SFCHG_FRATE_ADDR,
	 PMIC_BUCK_VPA_SFCHG_FRATE_MASK, PMIC_BUCK_VPA_SFCHG_FRATE_SHIFT},
	{PMIC_BUCK_VPA_SFCHG_FEN, PMIC_BUCK_VPA_SFCHG_FEN_ADDR,
	 PMIC_BUCK_VPA_SFCHG_FEN_MASK, PMIC_BUCK_VPA_SFCHG_FEN_SHIFT},
	{PMIC_BUCK_VPA_SFCHG_RRATE, PMIC_BUCK_VPA_SFCHG_RRATE_ADDR,
	 PMIC_BUCK_VPA_SFCHG_RRATE_MASK, PMIC_BUCK_VPA_SFCHG_RRATE_SHIFT},
	{PMIC_BUCK_VPA_SFCHG_REN, PMIC_BUCK_VPA_SFCHG_REN_ADDR,
	 PMIC_BUCK_VPA_SFCHG_REN_MASK, PMIC_BUCK_VPA_SFCHG_REN_SHIFT},
	{PMIC_DA_NI_VPA_VOSEL, PMIC_DA_NI_VPA_VOSEL_ADDR, PMIC_DA_NI_VPA_VOSEL_MASK,
	 PMIC_DA_NI_VPA_VOSEL_SHIFT},
	{PMIC_BUCK_VPA_VOSEL, PMIC_BUCK_VPA_VOSEL_ADDR, PMIC_BUCK_VPA_VOSEL_MASK,
	 PMIC_BUCK_VPA_VOSEL_SHIFT},
	{PMIC_BUCK_VPA_TRANS_TD, PMIC_BUCK_VPA_TRANS_TD_ADDR,
	 PMIC_BUCK_VPA_TRANS_TD_MASK, PMIC_BUCK_VPA_TRANS_TD_SHIFT},
	{PMIC_BUCK_VPA_TRANS_CTRL, PMIC_BUCK_VPA_TRANS_CTRL_ADDR,
	 PMIC_BUCK_VPA_TRANS_CTRL_MASK, PMIC_BUCK_VPA_TRANS_CTRL_SHIFT},
	{PMIC_BUCK_VPA_TRANS_ONCE, PMIC_BUCK_VPA_TRANS_ONCE_ADDR,
	 PMIC_BUCK_VPA_TRANS_ONCE_MASK, PMIC_BUCK_VPA_TRANS_ONCE_SHIFT},
	{PMIC_DA_NI_VPA_DVS_TRANST, PMIC_DA_NI_VPA_DVS_TRANST_ADDR,
	 PMIC_DA_NI_VPA_DVS_TRANST_MASK, PMIC_DA_NI_VPA_DVS_TRANST_SHIFT},
	{PMIC_BUCK_VPA_DVS_BW_TD, PMIC_BUCK_VPA_DVS_BW_TD_ADDR,
	 PMIC_BUCK_VPA_DVS_BW_TD_MASK, PMIC_BUCK_VPA_DVS_BW_TD_SHIFT},
	{PMIC_BUCK_VPA_DVS_BW_CTRL, PMIC_BUCK_VPA_DVS_BW_CTRL_ADDR,
	 PMIC_BUCK_VPA_DVS_BW_CTRL_MASK, PMIC_BUCK_VPA_DVS_BW_CTRL_SHIFT},
	{PMIC_BUCK_VPA_DVS_BW_ONCE, PMIC_BUCK_VPA_DVS_BW_ONCE_ADDR,
	 PMIC_BUCK_VPA_DVS_BW_ONCE_MASK, PMIC_BUCK_VPA_DVS_BW_ONCE_SHIFT},
	{PMIC_DA_NI_VPA_DVS_BW, PMIC_DA_NI_VPA_DVS_BW_ADDR,
	 PMIC_DA_NI_VPA_DVS_BW_MASK, PMIC_DA_NI_VPA_DVS_BW_SHIFT},
	{PMIC_BUCK_K_RST_DONE, PMIC_BUCK_K_RST_DONE_ADDR, PMIC_BUCK_K_RST_DONE_MASK,
	 PMIC_BUCK_K_RST_DONE_SHIFT},
	{PMIC_BUCK_K_MAP_SEL, PMIC_BUCK_K_MAP_SEL_ADDR, PMIC_BUCK_K_MAP_SEL_MASK,
	 PMIC_BUCK_K_MAP_SEL_SHIFT},
	{PMIC_BUCK_K_ONCE_EN, PMIC_BUCK_K_ONCE_EN_ADDR, PMIC_BUCK_K_ONCE_EN_MASK,
	 PMIC_BUCK_K_ONCE_EN_SHIFT},
	{PMIC_BUCK_K_ONCE, PMIC_BUCK_K_ONCE_ADDR, PMIC_BUCK_K_ONCE_MASK,
	 PMIC_BUCK_K_ONCE_SHIFT},
	{PMIC_BUCK_K_START_MANUAL, PMIC_BUCK_K_START_MANUAL_ADDR,
	 PMIC_BUCK_K_START_MANUAL_MASK, PMIC_BUCK_K_START_MANUAL_SHIFT},
	{PMIC_BUCK_K_SRC_SEL, PMIC_BUCK_K_SRC_SEL_ADDR, PMIC_BUCK_K_SRC_SEL_MASK,
	 PMIC_BUCK_K_SRC_SEL_SHIFT},
	{PMIC_BUCK_K_AUTO_EN, PMIC_BUCK_K_AUTO_EN_ADDR, PMIC_BUCK_K_AUTO_EN_MASK,
	 PMIC_BUCK_K_AUTO_EN_SHIFT},
	{PMIC_BUCK_K_INV, PMIC_BUCK_K_INV_ADDR, PMIC_BUCK_K_INV_MASK,
	 PMIC_BUCK_K_INV_SHIFT},
	{PMIC_BUCK_K_CONTROL_SMPS, PMIC_BUCK_K_CONTROL_SMPS_ADDR,
	 PMIC_BUCK_K_CONTROL_SMPS_MASK, PMIC_BUCK_K_CONTROL_SMPS_SHIFT},
	{PMIC_K_RESULT, PMIC_K_RESULT_ADDR, PMIC_K_RESULT_MASK,
	 PMIC_K_RESULT_SHIFT},
	{PMIC_K_DONE, PMIC_K_DONE_ADDR, PMIC_K_DONE_MASK, PMIC_K_DONE_SHIFT},
	{PMIC_K_CONTROL, PMIC_K_CONTROL_ADDR, PMIC_K_CONTROL_MASK,
	 PMIC_K_CONTROL_SHIFT},
	{PMIC_DA_QI_SMPS_OSC_CAL, PMIC_DA_QI_SMPS_OSC_CAL_ADDR,
	 PMIC_DA_QI_SMPS_OSC_CAL_MASK, PMIC_DA_QI_SMPS_OSC_CAL_SHIFT},
	{PMIC_BUCK_K_BUCK_CK_CNT, PMIC_BUCK_K_BUCK_CK_CNT_ADDR,
	 PMIC_BUCK_K_BUCK_CK_CNT_MASK, PMIC_BUCK_K_BUCK_CK_CNT_SHIFT},
	{PMIC_WDTDBG_CLR, PMIC_WDTDBG_CLR_ADDR, PMIC_WDTDBG_CLR_MASK,
	 PMIC_WDTDBG_CLR_SHIFT},
	{PMIC_WDTDBG_CON0_RSV0, PMIC_WDTDBG_CON0_RSV0_ADDR,
	 PMIC_WDTDBG_CON0_RSV0_MASK, PMIC_WDTDBG_CON0_RSV0_SHIFT},
	{PMIC_VPROC_VOSEL_WDTDBG, PMIC_VPROC_VOSEL_WDTDBG_ADDR,
	 PMIC_VPROC_VOSEL_WDTDBG_MASK, PMIC_VPROC_VOSEL_WDTDBG_SHIFT},
	{PMIC_VCORE_VOSEL_WDTDBG, PMIC_VCORE_VOSEL_WDTDBG_ADDR,
	 PMIC_VCORE_VOSEL_WDTDBG_MASK, PMIC_VCORE_VOSEL_WDTDBG_SHIFT},
	{PMIC_VPA_VOSEL_WDTDBG, PMIC_VPA_VOSEL_WDTDBG_ADDR,
	 PMIC_VPA_VOSEL_WDTDBG_MASK, PMIC_VPA_VOSEL_WDTDBG_SHIFT},
	{PMIC_VS1_VOSEL_WDTDBG, PMIC_VS1_VOSEL_WDTDBG_ADDR,
	 PMIC_VS1_VOSEL_WDTDBG_MASK, PMIC_VS1_VOSEL_WDTDBG_SHIFT},
	{PMIC_VSRAM_PROC_VOSEL_WDTDBG, PMIC_VSRAM_PROC_VOSEL_WDTDBG_ADDR,
	 PMIC_VSRAM_PROC_VOSEL_WDTDBG_MASK, PMIC_VSRAM_PROC_VOSEL_WDTDBG_SHIFT},
	{PMIC_RG_AUDZCDENABLE, PMIC_RG_AUDZCDENABLE_ADDR, PMIC_RG_AUDZCDENABLE_MASK,
	 PMIC_RG_AUDZCDENABLE_SHIFT},
	{PMIC_RG_AUDZCDGAINSTEPTIME, PMIC_RG_AUDZCDGAINSTEPTIME_ADDR,
	 PMIC_RG_AUDZCDGAINSTEPTIME_MASK, PMIC_RG_AUDZCDGAINSTEPTIME_SHIFT},
	{PMIC_RG_AUDZCDGAINSTEPSIZE, PMIC_RG_AUDZCDGAINSTEPSIZE_ADDR,
	 PMIC_RG_AUDZCDGAINSTEPSIZE_MASK, PMIC_RG_AUDZCDGAINSTEPSIZE_SHIFT},
	{PMIC_RG_AUDZCDTIMEOUTMODESEL, PMIC_RG_AUDZCDTIMEOUTMODESEL_ADDR,
	 PMIC_RG_AUDZCDTIMEOUTMODESEL_MASK, PMIC_RG_AUDZCDTIMEOUTMODESEL_SHIFT},
	{PMIC_RG_AUDZCDCLKSEL_VAUDP15, PMIC_RG_AUDZCDCLKSEL_VAUDP15_ADDR,
	 PMIC_RG_AUDZCDCLKSEL_VAUDP15_MASK, PMIC_RG_AUDZCDCLKSEL_VAUDP15_SHIFT},
	{PMIC_RG_AUDZCDMUXSEL_VAUDP15, PMIC_RG_AUDZCDMUXSEL_VAUDP15_ADDR,
	 PMIC_RG_AUDZCDMUXSEL_VAUDP15_MASK, PMIC_RG_AUDZCDMUXSEL_VAUDP15_SHIFT},
	{PMIC_RG_AUDLOLGAIN, PMIC_RG_AUDLOLGAIN_ADDR, PMIC_RG_AUDLOLGAIN_MASK,
	 PMIC_RG_AUDLOLGAIN_SHIFT},
	{PMIC_RG_AUDLORGAIN, PMIC_RG_AUDLORGAIN_ADDR, PMIC_RG_AUDLORGAIN_MASK,
	 PMIC_RG_AUDLORGAIN_SHIFT},
	{PMIC_RG_AUDHPLGAIN, PMIC_RG_AUDHPLGAIN_ADDR, PMIC_RG_AUDHPLGAIN_MASK,
	 PMIC_RG_AUDHPLGAIN_SHIFT},
	{PMIC_RG_AUDHPRGAIN, PMIC_RG_AUDHPRGAIN_ADDR, PMIC_RG_AUDHPRGAIN_MASK,
	 PMIC_RG_AUDHPRGAIN_SHIFT},
	{PMIC_RG_AUDHSGAIN, PMIC_RG_AUDHSGAIN_ADDR, PMIC_RG_AUDHSGAIN_MASK,
	 PMIC_RG_AUDHSGAIN_SHIFT},
	{PMIC_RG_AUDIVLGAIN, PMIC_RG_AUDIVLGAIN_ADDR, PMIC_RG_AUDIVLGAIN_MASK,
	 PMIC_RG_AUDIVLGAIN_SHIFT},
	{PMIC_RG_AUDIVRGAIN, PMIC_RG_AUDIVRGAIN_ADDR, PMIC_RG_AUDIVRGAIN_MASK,
	 PMIC_RG_AUDIVRGAIN_SHIFT},
	{PMIC_RG_AUDINTGAIN1, PMIC_RG_AUDINTGAIN1_ADDR, PMIC_RG_AUDINTGAIN1_MASK,
	 PMIC_RG_AUDINTGAIN1_SHIFT},
	{PMIC_RG_AUDINTGAIN2, PMIC_RG_AUDINTGAIN2_ADDR, PMIC_RG_AUDINTGAIN2_MASK,
	 PMIC_RG_AUDINTGAIN2_SHIFT},
	{PMIC_LDO_LDO_RSV1, PMIC_LDO_LDO_RSV1_ADDR, PMIC_LDO_LDO_RSV1_MASK,
	 PMIC_LDO_LDO_RSV1_SHIFT},
	{PMIC_LDO_LDO_RSV0, PMIC_LDO_LDO_RSV0_ADDR, PMIC_LDO_LDO_RSV0_MASK,
	 PMIC_LDO_LDO_RSV0_SHIFT},
	{PMIC_LDO_LDO_RSV1_RO, PMIC_LDO_LDO_RSV1_RO_ADDR, PMIC_LDO_LDO_RSV1_RO_MASK,
	 PMIC_LDO_LDO_RSV1_RO_SHIFT},
	{PMIC_LDO_LDO_RSV2, PMIC_LDO_LDO_RSV2_ADDR, PMIC_LDO_LDO_RSV2_MASK,
	 PMIC_LDO_LDO_RSV2_SHIFT},
	{PMIC_LDO_VAUX18_AUXADC_PWDB_EN, PMIC_LDO_VAUX18_AUXADC_PWDB_EN_ADDR,
	 PMIC_LDO_VAUX18_AUXADC_PWDB_EN_MASK, PMIC_LDO_VAUX18_AUXADC_PWDB_EN_SHIFT},
	{PMIC_LDO_VIBR_THER_SDN_EN, PMIC_LDO_VIBR_THER_SDN_EN_ADDR,
	 PMIC_LDO_VIBR_THER_SDN_EN_MASK, PMIC_LDO_VIBR_THER_SDN_EN_SHIFT},
	{PMIC_LDO_TOP_CON0_RSV, PMIC_LDO_TOP_CON0_RSV_ADDR,
	 PMIC_LDO_TOP_CON0_RSV_MASK, PMIC_LDO_TOP_CON0_RSV_SHIFT},
	{PMIC_LDO_VTCXO24_SWITCH, PMIC_LDO_VTCXO24_SWITCH_ADDR,
	 PMIC_LDO_VTCXO24_SWITCH_MASK, PMIC_LDO_VTCXO24_SWITCH_SHIFT},
	{PMIC_LDO_VXO22_SWITCH, PMIC_LDO_VXO22_SWITCH_ADDR,
	 PMIC_LDO_VXO22_SWITCH_MASK, PMIC_LDO_VXO22_SWITCH_SHIFT},
	{PMIC_LDO_DEGTD_SEL, PMIC_LDO_DEGTD_SEL_ADDR, PMIC_LDO_DEGTD_SEL_MASK,
	 PMIC_LDO_DEGTD_SEL_SHIFT},
	{PMIC_LDO_VRTC_EN, PMIC_LDO_VRTC_EN_ADDR, PMIC_LDO_VRTC_EN_MASK,
	 PMIC_LDO_VRTC_EN_SHIFT},
	{PMIC_DA_QI_VRTC_EN, PMIC_DA_QI_VRTC_EN_ADDR, PMIC_DA_QI_VRTC_EN_MASK,
	 PMIC_DA_QI_VRTC_EN_SHIFT},
	{PMIC_LDO_VCN33_EN_BT, PMIC_LDO_VCN33_EN_BT_ADDR, PMIC_LDO_VCN33_EN_BT_MASK,
	 PMIC_LDO_VCN33_EN_BT_SHIFT},
	{PMIC_LDO_VCN33_EN_CTRL_BT, PMIC_LDO_VCN33_EN_CTRL_BT_ADDR,
	 PMIC_LDO_VCN33_EN_CTRL_BT_MASK, PMIC_LDO_VCN33_EN_CTRL_BT_SHIFT},
	{PMIC_LDO_VCN33_EN_SEL_BT, PMIC_LDO_VCN33_EN_SEL_BT_ADDR,
	 PMIC_LDO_VCN33_EN_SEL_BT_MASK, PMIC_LDO_VCN33_EN_SEL_BT_SHIFT},
	{PMIC_LDO_VCN33_EN_WIFI, PMIC_LDO_VCN33_EN_WIFI_ADDR,
	 PMIC_LDO_VCN33_EN_WIFI_MASK, PMIC_LDO_VCN33_EN_WIFI_SHIFT},
	{PMIC_LDO_VCN33_EN_CTRL_WIFI, PMIC_LDO_VCN33_EN_CTRL_WIFI_ADDR,
	 PMIC_LDO_VCN33_EN_CTRL_WIFI_MASK, PMIC_LDO_VCN33_EN_CTRL_WIFI_SHIFT},
	{PMIC_LDO_VCN33_EN_SEL_WIFI, PMIC_LDO_VCN33_EN_SEL_WIFI_ADDR,
	 PMIC_LDO_VCN33_EN_SEL_WIFI_MASK, PMIC_LDO_VCN33_EN_SEL_WIFI_SHIFT},
	{PMIC_LDO_VCN33_LP_MODE, PMIC_LDO_VCN33_LP_MODE_ADDR,
	 PMIC_LDO_VCN33_LP_MODE_MASK, PMIC_LDO_VCN33_LP_MODE_SHIFT},
	{PMIC_LDO_VCN33_LP_CTRL, PMIC_LDO_VCN33_LP_CTRL_ADDR,
	 PMIC_LDO_VCN33_LP_CTRL_MASK, PMIC_LDO_VCN33_LP_CTRL_SHIFT},
	{PMIC_LDO_VCN33_LP_SEL, PMIC_LDO_VCN33_LP_SEL_ADDR,
	 PMIC_LDO_VCN33_LP_SEL_MASK, PMIC_LDO_VCN33_LP_SEL_SHIFT},
	{PMIC_DA_QI_VCN33_MODE, PMIC_DA_QI_VCN33_MODE_ADDR,
	 PMIC_DA_QI_VCN33_MODE_MASK, PMIC_DA_QI_VCN33_MODE_SHIFT},
	{PMIC_LDO_VCN33_STBTD, PMIC_LDO_VCN33_STBTD_ADDR, PMIC_LDO_VCN33_STBTD_MASK,
	 PMIC_LDO_VCN33_STBTD_SHIFT},
	{PMIC_DA_QI_VCN33_STB, PMIC_DA_QI_VCN33_STB_ADDR, PMIC_DA_QI_VCN33_STB_MASK,
	 PMIC_DA_QI_VCN33_STB_SHIFT},
	{PMIC_DA_QI_VCN33_EN, PMIC_DA_QI_VCN33_EN_ADDR, PMIC_DA_QI_VCN33_EN_MASK,
	 PMIC_DA_QI_VCN33_EN_SHIFT},
	{PMIC_LDO_VCN33_OCFB_EN, PMIC_LDO_VCN33_OCFB_EN_ADDR,
	 PMIC_LDO_VCN33_OCFB_EN_MASK, PMIC_LDO_VCN33_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VCN33_OCFB_EN, PMIC_DA_QI_VCN33_OCFB_EN_ADDR,
	 PMIC_DA_QI_VCN33_OCFB_EN_MASK, PMIC_DA_QI_VCN33_OCFB_EN_SHIFT},
	{PMIC_LDO_VLDO28_EN_0, PMIC_LDO_VLDO28_EN_0_ADDR, PMIC_LDO_VLDO28_EN_0_MASK,
	 PMIC_LDO_VLDO28_EN_0_SHIFT},
	{PMIC_LDO_VLDO28_EN_1, PMIC_LDO_VLDO28_EN_1_ADDR, PMIC_LDO_VLDO28_EN_1_MASK,
	 PMIC_LDO_VLDO28_EN_1_SHIFT},
	{PMIC_LDO_VLDO28_LP_MODE, PMIC_LDO_VLDO28_LP_MODE_ADDR,
	 PMIC_LDO_VLDO28_LP_MODE_MASK, PMIC_LDO_VLDO28_LP_MODE_SHIFT},
	{PMIC_LDO_VLDO28_LP_CTRL, PMIC_LDO_VLDO28_LP_CTRL_ADDR,
	 PMIC_LDO_VLDO28_LP_CTRL_MASK, PMIC_LDO_VLDO28_LP_CTRL_SHIFT},
	{PMIC_LDO_VLDO28_LP_SEL, PMIC_LDO_VLDO28_LP_SEL_ADDR,
	 PMIC_LDO_VLDO28_LP_SEL_MASK, PMIC_LDO_VLDO28_LP_SEL_SHIFT},
	{PMIC_DA_QI_VLDO28_MODE, PMIC_DA_QI_VLDO28_MODE_ADDR,
	 PMIC_DA_QI_VLDO28_MODE_MASK, PMIC_DA_QI_VLDO28_MODE_SHIFT},
	{PMIC_LDO_VLDO28_STBTD, PMIC_LDO_VLDO28_STBTD_ADDR,
	 PMIC_LDO_VLDO28_STBTD_MASK, PMIC_LDO_VLDO28_STBTD_SHIFT},
	{PMIC_DA_QI_VLDO28_STB, PMIC_DA_QI_VLDO28_STB_ADDR,
	 PMIC_DA_QI_VLDO28_STB_MASK, PMIC_DA_QI_VLDO28_STB_SHIFT},
	{PMIC_DA_QI_VLDO28_EN, PMIC_DA_QI_VLDO28_EN_ADDR, PMIC_DA_QI_VLDO28_EN_MASK,
	 PMIC_DA_QI_VLDO28_EN_SHIFT},
	{PMIC_LDO_VLDO28_OCFB_EN, PMIC_LDO_VLDO28_OCFB_EN_ADDR,
	 PMIC_LDO_VLDO28_OCFB_EN_MASK, PMIC_LDO_VLDO28_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VLDO28_OCFB_EN, PMIC_DA_QI_VLDO28_OCFB_EN_ADDR,
	 PMIC_DA_QI_VLDO28_OCFB_EN_MASK, PMIC_DA_QI_VLDO28_OCFB_EN_SHIFT},
	{PMIC_LDO_VLDO28_FAST_TRAN_DL_EN, PMIC_LDO_VLDO28_FAST_TRAN_DL_EN_ADDR,
	 PMIC_LDO_VLDO28_FAST_TRAN_DL_EN_MASK, PMIC_LDO_VLDO28_FAST_TRAN_DL_EN_SHIFT},
	{PMIC_LDO_VLDO28_FAST_TRAN_DL_CTRL, PMIC_LDO_VLDO28_FAST_TRAN_DL_CTRL_ADDR,
	 PMIC_LDO_VLDO28_FAST_TRAN_DL_CTRL_MASK,
	 PMIC_LDO_VLDO28_FAST_TRAN_DL_CTRL_SHIFT},
	{PMIC_LDO_VLDO28_FAST_TRAN_DL_SRCLKEN_SEL,
	 PMIC_LDO_VLDO28_FAST_TRAN_DL_SRCLKEN_SEL_ADDR,
	 PMIC_LDO_VLDO28_FAST_TRAN_DL_SRCLKEN_SEL_MASK,
	 PMIC_LDO_VLDO28_FAST_TRAN_DL_SRCLKEN_SEL_SHIFT},
	{PMIC_DA_QI_VLDO28_FAST_TRAN_DL_EN, PMIC_DA_QI_VLDO28_FAST_TRAN_DL_EN_ADDR,
	 PMIC_DA_QI_VLDO28_FAST_TRAN_DL_EN_MASK,
	 PMIC_DA_QI_VLDO28_FAST_TRAN_DL_EN_SHIFT},
	{PMIC_LDO_VLDO28_FAST_TRAN_CL_EN, PMIC_LDO_VLDO28_FAST_TRAN_CL_EN_ADDR,
	 PMIC_LDO_VLDO28_FAST_TRAN_CL_EN_MASK, PMIC_LDO_VLDO28_FAST_TRAN_CL_EN_SHIFT},
	{PMIC_LDO_VLDO28_FAST_TRAN_CL_CTRL, PMIC_LDO_VLDO28_FAST_TRAN_CL_CTRL_ADDR,
	 PMIC_LDO_VLDO28_FAST_TRAN_CL_CTRL_MASK,
	 PMIC_LDO_VLDO28_FAST_TRAN_CL_CTRL_SHIFT},
	{PMIC_LDO_VLDO28_FAST_TRAN_CL_SRCLKEN_SEL,
	 PMIC_LDO_VLDO28_FAST_TRAN_CL_SRCLKEN_SEL_ADDR,
	 PMIC_LDO_VLDO28_FAST_TRAN_CL_SRCLKEN_SEL_MASK,
	 PMIC_LDO_VLDO28_FAST_TRAN_CL_SRCLKEN_SEL_SHIFT},
	{PMIC_DA_QI_VLDO28_FAST_TRAN_CL_EN, PMIC_DA_QI_VLDO28_FAST_TRAN_CL_EN_ADDR,
	 PMIC_DA_QI_VLDO28_FAST_TRAN_CL_EN_MASK,
	 PMIC_DA_QI_VLDO28_FAST_TRAN_CL_EN_SHIFT},
	{PMIC_LDO_VSRAM_PROC_VOSEL_CTRL, PMIC_LDO_VSRAM_PROC_VOSEL_CTRL_ADDR,
	 PMIC_LDO_VSRAM_PROC_VOSEL_CTRL_MASK, PMIC_LDO_VSRAM_PROC_VOSEL_CTRL_SHIFT},
	{PMIC_LDO_VSRAM_PROC_VOSEL_SEL, PMIC_LDO_VSRAM_PROC_VOSEL_SEL_ADDR,
	 PMIC_LDO_VSRAM_PROC_VOSEL_SEL_MASK, PMIC_LDO_VSRAM_PROC_VOSEL_SEL_SHIFT},
	{PMIC_LDO_VSRAM_PROC_SFCHG_FRATE, PMIC_LDO_VSRAM_PROC_SFCHG_FRATE_ADDR,
	 PMIC_LDO_VSRAM_PROC_SFCHG_FRATE_MASK, PMIC_LDO_VSRAM_PROC_SFCHG_FRATE_SHIFT},
	{PMIC_LDO_VSRAM_PROC_SFCHG_FEN, PMIC_LDO_VSRAM_PROC_SFCHG_FEN_ADDR,
	 PMIC_LDO_VSRAM_PROC_SFCHG_FEN_MASK, PMIC_LDO_VSRAM_PROC_SFCHG_FEN_SHIFT},
	{PMIC_LDO_VSRAM_PROC_SFCHG_RRATE, PMIC_LDO_VSRAM_PROC_SFCHG_RRATE_ADDR,
	 PMIC_LDO_VSRAM_PROC_SFCHG_RRATE_MASK, PMIC_LDO_VSRAM_PROC_SFCHG_RRATE_SHIFT},
	{PMIC_LDO_VSRAM_PROC_SFCHG_REN, PMIC_LDO_VSRAM_PROC_SFCHG_REN_ADDR,
	 PMIC_LDO_VSRAM_PROC_SFCHG_REN_MASK, PMIC_LDO_VSRAM_PROC_SFCHG_REN_SHIFT},
	{PMIC_DA_NI_VSRAM_PROC_VOSEL, PMIC_DA_NI_VSRAM_PROC_VOSEL_ADDR,
	 PMIC_DA_NI_VSRAM_PROC_VOSEL_MASK, PMIC_DA_NI_VSRAM_PROC_VOSEL_SHIFT},
	{PMIC_LDO_VSRAM_PROC_VOSEL, PMIC_LDO_VSRAM_PROC_VOSEL_ADDR,
	 PMIC_LDO_VSRAM_PROC_VOSEL_MASK, PMIC_LDO_VSRAM_PROC_VOSEL_SHIFT},
	{PMIC_LDO_VSRAM_PROC_VOSEL_ON, PMIC_LDO_VSRAM_PROC_VOSEL_ON_ADDR,
	 PMIC_LDO_VSRAM_PROC_VOSEL_ON_MASK, PMIC_LDO_VSRAM_PROC_VOSEL_ON_SHIFT},
	{PMIC_LDO_VSRAM_PROC_VOSEL_SLEEP, PMIC_LDO_VSRAM_PROC_VOSEL_SLEEP_ADDR,
	 PMIC_LDO_VSRAM_PROC_VOSEL_SLEEP_MASK, PMIC_LDO_VSRAM_PROC_VOSEL_SLEEP_SHIFT},
	{PMIC_LDO_VSRAM_PROC_TRANS_TD, PMIC_LDO_VSRAM_PROC_TRANS_TD_ADDR,
	 PMIC_LDO_VSRAM_PROC_TRANS_TD_MASK, PMIC_LDO_VSRAM_PROC_TRANS_TD_SHIFT},
	{PMIC_LDO_VSRAM_PROC_TRANS_CTRL, PMIC_LDO_VSRAM_PROC_TRANS_CTRL_ADDR,
	 PMIC_LDO_VSRAM_PROC_TRANS_CTRL_MASK, PMIC_LDO_VSRAM_PROC_TRANS_CTRL_SHIFT},
	{PMIC_LDO_VSRAM_PROC_TRANS_ONCE, PMIC_LDO_VSRAM_PROC_TRANS_ONCE_ADDR,
	 PMIC_LDO_VSRAM_PROC_TRANS_ONCE_MASK, PMIC_LDO_VSRAM_PROC_TRANS_ONCE_SHIFT},
	{PMIC_DA_QI_VSRAM_PROC_DVS_EN, PMIC_DA_QI_VSRAM_PROC_DVS_EN_ADDR,
	 PMIC_DA_QI_VSRAM_PROC_DVS_EN_MASK, PMIC_DA_QI_VSRAM_PROC_DVS_EN_SHIFT},
	{PMIC_LDO_VSRAM_PROC_VSLEEP_EN, PMIC_LDO_VSRAM_PROC_VSLEEP_EN_ADDR,
	 PMIC_LDO_VSRAM_PROC_VSLEEP_EN_MASK, PMIC_LDO_VSRAM_PROC_VSLEEP_EN_SHIFT},
	{PMIC_LDO_VSRAM_PROC_R2R_PDN, PMIC_LDO_VSRAM_PROC_R2R_PDN_ADDR,
	 PMIC_LDO_VSRAM_PROC_R2R_PDN_MASK, PMIC_LDO_VSRAM_PROC_R2R_PDN_SHIFT},
	{PMIC_LDO_VSRAM_PROC_VSLEEP_SEL, PMIC_LDO_VSRAM_PROC_VSLEEP_SEL_ADDR,
	 PMIC_LDO_VSRAM_PROC_VSLEEP_SEL_MASK, PMIC_LDO_VSRAM_PROC_VSLEEP_SEL_SHIFT},
	{PMIC_DA_NI_VSRAM_PROC_R2R_PDN, PMIC_DA_NI_VSRAM_PROC_R2R_PDN_ADDR,
	 PMIC_DA_NI_VSRAM_PROC_R2R_PDN_MASK, PMIC_DA_NI_VSRAM_PROC_R2R_PDN_SHIFT},
	{PMIC_DA_NI_VSRAM_PROC_VSLEEP_SEL, PMIC_DA_NI_VSRAM_PROC_VSLEEP_SEL_ADDR,
	 PMIC_DA_NI_VSRAM_PROC_VSLEEP_SEL_MASK,
	 PMIC_DA_NI_VSRAM_PROC_VSLEEP_SEL_SHIFT},
	{PMIC_LDO_BATON_HT_EN, PMIC_LDO_BATON_HT_EN_ADDR, PMIC_LDO_BATON_HT_EN_MASK,
	 PMIC_LDO_BATON_HT_EN_SHIFT},
	{PMIC_LDO_BATON_HT_EN_DLY_TIME, PMIC_LDO_BATON_HT_EN_DLY_TIME_ADDR,
	 PMIC_LDO_BATON_HT_EN_DLY_TIME_MASK, PMIC_LDO_BATON_HT_EN_DLY_TIME_SHIFT},
	{PMIC_DA_QI_BATON_HT_EN, PMIC_DA_QI_BATON_HT_EN_ADDR,
	 PMIC_DA_QI_BATON_HT_EN_MASK, PMIC_DA_QI_BATON_HT_EN_SHIFT},
	{PMIC_LDO_TREF_EN, PMIC_LDO_TREF_EN_ADDR, PMIC_LDO_TREF_EN_MASK,
	 PMIC_LDO_TREF_EN_SHIFT},
	{PMIC_LDO_TREF_EN_CTRL, PMIC_LDO_TREF_EN_CTRL_ADDR,
	 PMIC_LDO_TREF_EN_CTRL_MASK, PMIC_LDO_TREF_EN_CTRL_SHIFT},
	{PMIC_LDO_TREF_EN_SEL, PMIC_LDO_TREF_EN_SEL_ADDR, PMIC_LDO_TREF_EN_SEL_MASK,
	 PMIC_LDO_TREF_EN_SEL_SHIFT},
	{PMIC_DA_QI_TREF_EN, PMIC_DA_QI_TREF_EN_ADDR, PMIC_DA_QI_TREF_EN_MASK,
	 PMIC_DA_QI_TREF_EN_SHIFT},
	{PMIC_LDO_VTCXO28_LP_MODE, PMIC_LDO_VTCXO28_LP_MODE_ADDR,
	 PMIC_LDO_VTCXO28_LP_MODE_MASK, PMIC_LDO_VTCXO28_LP_MODE_SHIFT},
	{PMIC_LDO_VTCXO28_EN, PMIC_LDO_VTCXO28_EN_ADDR, PMIC_LDO_VTCXO28_EN_MASK,
	 PMIC_LDO_VTCXO28_EN_SHIFT},
	{PMIC_LDO_VTCXO28_LP_CTRL, PMIC_LDO_VTCXO28_LP_CTRL_ADDR,
	 PMIC_LDO_VTCXO28_LP_CTRL_MASK, PMIC_LDO_VTCXO28_LP_CTRL_SHIFT},
	{PMIC_LDO_VTCXO28_EN_CTRL, PMIC_LDO_VTCXO28_EN_CTRL_ADDR,
	 PMIC_LDO_VTCXO28_EN_CTRL_MASK, PMIC_LDO_VTCXO28_EN_CTRL_SHIFT},
	{PMIC_LDO_VTCXO28_LP_SEL, PMIC_LDO_VTCXO28_LP_SEL_ADDR,
	 PMIC_LDO_VTCXO28_LP_SEL_MASK, PMIC_LDO_VTCXO28_LP_SEL_SHIFT},
	{PMIC_DA_QI_VTCXO28_MODE, PMIC_DA_QI_VTCXO28_MODE_ADDR,
	 PMIC_DA_QI_VTCXO28_MODE_MASK, PMIC_DA_QI_VTCXO28_MODE_SHIFT},
	{PMIC_LDO_VTCXO28_STBTD, PMIC_LDO_VTCXO28_STBTD_ADDR,
	 PMIC_LDO_VTCXO28_STBTD_MASK, PMIC_LDO_VTCXO28_STBTD_SHIFT},
	{PMIC_LDO_VTCXO28_EN_SEL, PMIC_LDO_VTCXO28_EN_SEL_ADDR,
	 PMIC_LDO_VTCXO28_EN_SEL_MASK, PMIC_LDO_VTCXO28_EN_SEL_SHIFT},
	{PMIC_DA_QI_VTCXO28_STB, PMIC_DA_QI_VTCXO28_STB_ADDR,
	 PMIC_DA_QI_VTCXO28_STB_MASK, PMIC_DA_QI_VTCXO28_STB_SHIFT},
	{PMIC_DA_QI_VTCXO28_EN, PMIC_DA_QI_VTCXO28_EN_ADDR,
	 PMIC_DA_QI_VTCXO28_EN_MASK, PMIC_DA_QI_VTCXO28_EN_SHIFT},
	{PMIC_LDO_VTCXO28_OCFB_EN, PMIC_LDO_VTCXO28_OCFB_EN_ADDR,
	 PMIC_LDO_VTCXO28_OCFB_EN_MASK, PMIC_LDO_VTCXO28_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VTCXO28_OCFB_EN, PMIC_DA_QI_VTCXO28_OCFB_EN_ADDR,
	 PMIC_DA_QI_VTCXO28_OCFB_EN_MASK, PMIC_DA_QI_VTCXO28_OCFB_EN_SHIFT},
	{PMIC_LDO_VTCXO24_LP_MODE, PMIC_LDO_VTCXO24_LP_MODE_ADDR,
	 PMIC_LDO_VTCXO24_LP_MODE_MASK, PMIC_LDO_VTCXO24_LP_MODE_SHIFT},
	{PMIC_LDO_VTCXO24_EN, PMIC_LDO_VTCXO24_EN_ADDR, PMIC_LDO_VTCXO24_EN_MASK,
	 PMIC_LDO_VTCXO24_EN_SHIFT},
	{PMIC_LDO_VTCXO24_LP_CTRL, PMIC_LDO_VTCXO24_LP_CTRL_ADDR,
	 PMIC_LDO_VTCXO24_LP_CTRL_MASK, PMIC_LDO_VTCXO24_LP_CTRL_SHIFT},
	{PMIC_LDO_VTCXO24_EN_CTRL, PMIC_LDO_VTCXO24_EN_CTRL_ADDR,
	 PMIC_LDO_VTCXO24_EN_CTRL_MASK, PMIC_LDO_VTCXO24_EN_CTRL_SHIFT},
	{PMIC_LDO_VTCXO24_LP_SEL, PMIC_LDO_VTCXO24_LP_SEL_ADDR,
	 PMIC_LDO_VTCXO24_LP_SEL_MASK, PMIC_LDO_VTCXO24_LP_SEL_SHIFT},
	{PMIC_DA_QI_VTCXO24_MODE, PMIC_DA_QI_VTCXO24_MODE_ADDR,
	 PMIC_DA_QI_VTCXO24_MODE_MASK, PMIC_DA_QI_VTCXO24_MODE_SHIFT},
	{PMIC_LDO_VTCXO24_STBTD, PMIC_LDO_VTCXO24_STBTD_ADDR,
	 PMIC_LDO_VTCXO24_STBTD_MASK, PMIC_LDO_VTCXO24_STBTD_SHIFT},
	{PMIC_LDO_VTCXO24_EN_SEL, PMIC_LDO_VTCXO24_EN_SEL_ADDR,
	 PMIC_LDO_VTCXO24_EN_SEL_MASK, PMIC_LDO_VTCXO24_EN_SEL_SHIFT},
	{PMIC_DA_QI_VTCXO24_STB, PMIC_DA_QI_VTCXO24_STB_ADDR,
	 PMIC_DA_QI_VTCXO24_STB_MASK, PMIC_DA_QI_VTCXO24_STB_SHIFT},
	{PMIC_DA_QI_VTCXO24_EN, PMIC_DA_QI_VTCXO24_EN_ADDR,
	 PMIC_DA_QI_VTCXO24_EN_MASK, PMIC_DA_QI_VTCXO24_EN_SHIFT},
	{PMIC_LDO_VTCXO24_OCFB_EN, PMIC_LDO_VTCXO24_OCFB_EN_ADDR,
	 PMIC_LDO_VTCXO24_OCFB_EN_MASK, PMIC_LDO_VTCXO24_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VTCXO24_OCFB_EN, PMIC_DA_QI_VTCXO24_OCFB_EN_ADDR,
	 PMIC_DA_QI_VTCXO24_OCFB_EN_MASK, PMIC_DA_QI_VTCXO24_OCFB_EN_SHIFT},
	{PMIC_LDO_VXO22_LP_MODE, PMIC_LDO_VXO22_LP_MODE_ADDR,
	 PMIC_LDO_VXO22_LP_MODE_MASK, PMIC_LDO_VXO22_LP_MODE_SHIFT},
	{PMIC_LDO_VXO22_EN, PMIC_LDO_VXO22_EN_ADDR, PMIC_LDO_VXO22_EN_MASK,
	 PMIC_LDO_VXO22_EN_SHIFT},
	{PMIC_LDO_VXO22_LP_CTRL, PMIC_LDO_VXO22_LP_CTRL_ADDR,
	 PMIC_LDO_VXO22_LP_CTRL_MASK, PMIC_LDO_VXO22_LP_CTRL_SHIFT},
	{PMIC_LDO_VXO22_EN_CTRL, PMIC_LDO_VXO22_EN_CTRL_ADDR,
	 PMIC_LDO_VXO22_EN_CTRL_MASK, PMIC_LDO_VXO22_EN_CTRL_SHIFT},
	{PMIC_LDO_VXO22_LP_SEL, PMIC_LDO_VXO22_LP_SEL_ADDR,
	 PMIC_LDO_VXO22_LP_SEL_MASK, PMIC_LDO_VXO22_LP_SEL_SHIFT},
	{PMIC_DA_QI_VXO22_MODE, PMIC_DA_QI_VXO22_MODE_ADDR,
	 PMIC_DA_QI_VXO22_MODE_MASK, PMIC_DA_QI_VXO22_MODE_SHIFT},
	{PMIC_LDO_VXO22_STBTD, PMIC_LDO_VXO22_STBTD_ADDR, PMIC_LDO_VXO22_STBTD_MASK,
	 PMIC_LDO_VXO22_STBTD_SHIFT},
	{PMIC_LDO_VXO22_EN_SEL, PMIC_LDO_VXO22_EN_SEL_ADDR,
	 PMIC_LDO_VXO22_EN_SEL_MASK, PMIC_LDO_VXO22_EN_SEL_SHIFT},
	{PMIC_DA_QI_VXO22_STB, PMIC_DA_QI_VXO22_STB_ADDR, PMIC_DA_QI_VXO22_STB_MASK,
	 PMIC_DA_QI_VXO22_STB_SHIFT},
	{PMIC_DA_QI_VXO22_EN, PMIC_DA_QI_VXO22_EN_ADDR, PMIC_DA_QI_VXO22_EN_MASK,
	 PMIC_DA_QI_VXO22_EN_SHIFT},
	{PMIC_LDO_VXO22_OCFB_EN, PMIC_LDO_VXO22_OCFB_EN_ADDR,
	 PMIC_LDO_VXO22_OCFB_EN_MASK, PMIC_LDO_VXO22_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VXO22_OCFB_EN, PMIC_DA_QI_VXO22_OCFB_EN_ADDR,
	 PMIC_DA_QI_VXO22_OCFB_EN_MASK, PMIC_DA_QI_VXO22_OCFB_EN_SHIFT},
	{PMIC_LDO_VRF18_LP_MODE, PMIC_LDO_VRF18_LP_MODE_ADDR,
	 PMIC_LDO_VRF18_LP_MODE_MASK, PMIC_LDO_VRF18_LP_MODE_SHIFT},
	{PMIC_LDO_VRF18_EN, PMIC_LDO_VRF18_EN_ADDR, PMIC_LDO_VRF18_EN_MASK,
	 PMIC_LDO_VRF18_EN_SHIFT},
	{PMIC_LDO_VRF18_LP_CTRL, PMIC_LDO_VRF18_LP_CTRL_ADDR,
	 PMIC_LDO_VRF18_LP_CTRL_MASK, PMIC_LDO_VRF18_LP_CTRL_SHIFT},
	{PMIC_LDO_VRF18_EN_CTRL, PMIC_LDO_VRF18_EN_CTRL_ADDR,
	 PMIC_LDO_VRF18_EN_CTRL_MASK, PMIC_LDO_VRF18_EN_CTRL_SHIFT},
	{PMIC_LDO_VRF18_LP_SEL, PMIC_LDO_VRF18_LP_SEL_ADDR,
	 PMIC_LDO_VRF18_LP_SEL_MASK, PMIC_LDO_VRF18_LP_SEL_SHIFT},
	{PMIC_DA_QI_VRF18_MODE, PMIC_DA_QI_VRF18_MODE_ADDR,
	 PMIC_DA_QI_VRF18_MODE_MASK, PMIC_DA_QI_VRF18_MODE_SHIFT},
	{PMIC_LDO_VRF18_STBTD, PMIC_LDO_VRF18_STBTD_ADDR, PMIC_LDO_VRF18_STBTD_MASK,
	 PMIC_LDO_VRF18_STBTD_SHIFT},
	{PMIC_LDO_VRF18_EN_SEL, PMIC_LDO_VRF18_EN_SEL_ADDR,
	 PMIC_LDO_VRF18_EN_SEL_MASK, PMIC_LDO_VRF18_EN_SEL_SHIFT},
	{PMIC_DA_QI_VRF18_STB, PMIC_DA_QI_VRF18_STB_ADDR, PMIC_DA_QI_VRF18_STB_MASK,
	 PMIC_DA_QI_VRF18_STB_SHIFT},
	{PMIC_DA_QI_VRF18_EN, PMIC_DA_QI_VRF18_EN_ADDR, PMIC_DA_QI_VRF18_EN_MASK,
	 PMIC_DA_QI_VRF18_EN_SHIFT},
	{PMIC_LDO_VRF18_OCFB_EN, PMIC_LDO_VRF18_OCFB_EN_ADDR,
	 PMIC_LDO_VRF18_OCFB_EN_MASK, PMIC_LDO_VRF18_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VRF18_OCFB_EN, PMIC_DA_QI_VRF18_OCFB_EN_ADDR,
	 PMIC_DA_QI_VRF18_OCFB_EN_MASK, PMIC_DA_QI_VRF18_OCFB_EN_SHIFT},
	{PMIC_LDO_VRF12_LP_MODE, PMIC_LDO_VRF12_LP_MODE_ADDR,
	 PMIC_LDO_VRF12_LP_MODE_MASK, PMIC_LDO_VRF12_LP_MODE_SHIFT},
	{PMIC_LDO_VRF12_EN, PMIC_LDO_VRF12_EN_ADDR, PMIC_LDO_VRF12_EN_MASK,
	 PMIC_LDO_VRF12_EN_SHIFT},
	{PMIC_LDO_VRF12_LP_CTRL, PMIC_LDO_VRF12_LP_CTRL_ADDR,
	 PMIC_LDO_VRF12_LP_CTRL_MASK, PMIC_LDO_VRF12_LP_CTRL_SHIFT},
	{PMIC_LDO_VRF12_EN_CTRL, PMIC_LDO_VRF12_EN_CTRL_ADDR,
	 PMIC_LDO_VRF12_EN_CTRL_MASK, PMIC_LDO_VRF12_EN_CTRL_SHIFT},
	{PMIC_LDO_VRF12_LP_SEL, PMIC_LDO_VRF12_LP_SEL_ADDR,
	 PMIC_LDO_VRF12_LP_SEL_MASK, PMIC_LDO_VRF12_LP_SEL_SHIFT},
	{PMIC_DA_QI_VRF12_MODE, PMIC_DA_QI_VRF12_MODE_ADDR,
	 PMIC_DA_QI_VRF12_MODE_MASK, PMIC_DA_QI_VRF12_MODE_SHIFT},
	{PMIC_LDO_VRF12_STBTD, PMIC_LDO_VRF12_STBTD_ADDR, PMIC_LDO_VRF12_STBTD_MASK,
	 PMIC_LDO_VRF12_STBTD_SHIFT},
	{PMIC_LDO_VRF12_EN_SEL, PMIC_LDO_VRF12_EN_SEL_ADDR,
	 PMIC_LDO_VRF12_EN_SEL_MASK, PMIC_LDO_VRF12_EN_SEL_SHIFT},
	{PMIC_DA_QI_VRF12_STB, PMIC_DA_QI_VRF12_STB_ADDR, PMIC_DA_QI_VRF12_STB_MASK,
	 PMIC_DA_QI_VRF12_STB_SHIFT},
	{PMIC_DA_QI_VRF12_EN, PMIC_DA_QI_VRF12_EN_ADDR, PMIC_DA_QI_VRF12_EN_MASK,
	 PMIC_DA_QI_VRF12_EN_SHIFT},
	{PMIC_LDO_VRF12_OCFB_EN, PMIC_LDO_VRF12_OCFB_EN_ADDR,
	 PMIC_LDO_VRF12_OCFB_EN_MASK, PMIC_LDO_VRF12_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VRF12_OCFB_EN, PMIC_DA_QI_VRF12_OCFB_EN_ADDR,
	 PMIC_DA_QI_VRF12_OCFB_EN_MASK, PMIC_DA_QI_VRF12_OCFB_EN_SHIFT},
	{PMIC_LDO_VRF12_FAST_TRAN_DL_EN, PMIC_LDO_VRF12_FAST_TRAN_DL_EN_ADDR,
	 PMIC_LDO_VRF12_FAST_TRAN_DL_EN_MASK, PMIC_LDO_VRF12_FAST_TRAN_DL_EN_SHIFT},
	{PMIC_LDO_VRF12_FAST_TRAN_DL_CTRL, PMIC_LDO_VRF12_FAST_TRAN_DL_CTRL_ADDR,
	 PMIC_LDO_VRF12_FAST_TRAN_DL_CTRL_MASK,
	 PMIC_LDO_VRF12_FAST_TRAN_DL_CTRL_SHIFT},
	{PMIC_LDO_VRF12_FAST_TRAN_DL_SRCLKEN_SEL,
	 PMIC_LDO_VRF12_FAST_TRAN_DL_SRCLKEN_SEL_ADDR,
	 PMIC_LDO_VRF12_FAST_TRAN_DL_SRCLKEN_SEL_MASK,
	 PMIC_LDO_VRF12_FAST_TRAN_DL_SRCLKEN_SEL_SHIFT},
	{PMIC_DA_QI_VRF12_FAST_TRAN_DL_EN, PMIC_DA_QI_VRF12_FAST_TRAN_DL_EN_ADDR,
	 PMIC_DA_QI_VRF12_FAST_TRAN_DL_EN_MASK,
	 PMIC_DA_QI_VRF12_FAST_TRAN_DL_EN_SHIFT},
	{PMIC_LDO_VRF12_FAST_TRAN_CL_EN, PMIC_LDO_VRF12_FAST_TRAN_CL_EN_ADDR,
	 PMIC_LDO_VRF12_FAST_TRAN_CL_EN_MASK, PMIC_LDO_VRF12_FAST_TRAN_CL_EN_SHIFT},
	{PMIC_LDO_VRF12_FAST_TRAN_CL_CTRL, PMIC_LDO_VRF12_FAST_TRAN_CL_CTRL_ADDR,
	 PMIC_LDO_VRF12_FAST_TRAN_CL_CTRL_MASK,
	 PMIC_LDO_VRF12_FAST_TRAN_CL_CTRL_SHIFT},
	{PMIC_LDO_VRF12_FAST_TRAN_CL_SRCLKEN_SEL,
	 PMIC_LDO_VRF12_FAST_TRAN_CL_SRCLKEN_SEL_ADDR,
	 PMIC_LDO_VRF12_FAST_TRAN_CL_SRCLKEN_SEL_MASK,
	 PMIC_LDO_VRF12_FAST_TRAN_CL_SRCLKEN_SEL_SHIFT},
	{PMIC_DA_QI_VRF12_FAST_TRAN_CL_EN, PMIC_DA_QI_VRF12_FAST_TRAN_CL_EN_ADDR,
	 PMIC_DA_QI_VRF12_FAST_TRAN_CL_EN_MASK,
	 PMIC_DA_QI_VRF12_FAST_TRAN_CL_EN_SHIFT},
	{PMIC_LDO_VCN28_LP_MODE, PMIC_LDO_VCN28_LP_MODE_ADDR,
	 PMIC_LDO_VCN28_LP_MODE_MASK, PMIC_LDO_VCN28_LP_MODE_SHIFT},
	{PMIC_LDO_VCN28_EN, PMIC_LDO_VCN28_EN_ADDR, PMIC_LDO_VCN28_EN_MASK,
	 PMIC_LDO_VCN28_EN_SHIFT},
	{PMIC_LDO_VCN28_LP_CTRL, PMIC_LDO_VCN28_LP_CTRL_ADDR,
	 PMIC_LDO_VCN28_LP_CTRL_MASK, PMIC_LDO_VCN28_LP_CTRL_SHIFT},
	{PMIC_LDO_VCN28_EN_CTRL, PMIC_LDO_VCN28_EN_CTRL_ADDR,
	 PMIC_LDO_VCN28_EN_CTRL_MASK, PMIC_LDO_VCN28_EN_CTRL_SHIFT},
	{PMIC_LDO_VCN28_LP_SEL, PMIC_LDO_VCN28_LP_SEL_ADDR,
	 PMIC_LDO_VCN28_LP_SEL_MASK, PMIC_LDO_VCN28_LP_SEL_SHIFT},
	{PMIC_DA_QI_VCN28_MODE, PMIC_DA_QI_VCN28_MODE_ADDR,
	 PMIC_DA_QI_VCN28_MODE_MASK, PMIC_DA_QI_VCN28_MODE_SHIFT},
	{PMIC_LDO_VCN28_STBTD, PMIC_LDO_VCN28_STBTD_ADDR, PMIC_LDO_VCN28_STBTD_MASK,
	 PMIC_LDO_VCN28_STBTD_SHIFT},
	{PMIC_LDO_VCN28_EN_SEL, PMIC_LDO_VCN28_EN_SEL_ADDR,
	 PMIC_LDO_VCN28_EN_SEL_MASK, PMIC_LDO_VCN28_EN_SEL_SHIFT},
	{PMIC_DA_QI_VCN28_STB, PMIC_DA_QI_VCN28_STB_ADDR, PMIC_DA_QI_VCN28_STB_MASK,
	 PMIC_DA_QI_VCN28_STB_SHIFT},
	{PMIC_DA_QI_VCN28_EN, PMIC_DA_QI_VCN28_EN_ADDR, PMIC_DA_QI_VCN28_EN_MASK,
	 PMIC_DA_QI_VCN28_EN_SHIFT},
	{PMIC_LDO_VCN28_OCFB_EN, PMIC_LDO_VCN28_OCFB_EN_ADDR,
	 PMIC_LDO_VCN28_OCFB_EN_MASK, PMIC_LDO_VCN28_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VCN28_OCFB_EN, PMIC_DA_QI_VCN28_OCFB_EN_ADDR,
	 PMIC_DA_QI_VCN28_OCFB_EN_MASK, PMIC_DA_QI_VCN28_OCFB_EN_SHIFT},
	{PMIC_LDO_VCN18_LP_MODE, PMIC_LDO_VCN18_LP_MODE_ADDR,
	 PMIC_LDO_VCN18_LP_MODE_MASK, PMIC_LDO_VCN18_LP_MODE_SHIFT},
	{PMIC_LDO_VCN18_EN, PMIC_LDO_VCN18_EN_ADDR, PMIC_LDO_VCN18_EN_MASK,
	 PMIC_LDO_VCN18_EN_SHIFT},
	{PMIC_LDO_VCN18_LP_CTRL, PMIC_LDO_VCN18_LP_CTRL_ADDR,
	 PMIC_LDO_VCN18_LP_CTRL_MASK, PMIC_LDO_VCN18_LP_CTRL_SHIFT},
	{PMIC_LDO_VCN18_EN_CTRL, PMIC_LDO_VCN18_EN_CTRL_ADDR,
	 PMIC_LDO_VCN18_EN_CTRL_MASK, PMIC_LDO_VCN18_EN_CTRL_SHIFT},
	{PMIC_LDO_VCN18_LP_SEL, PMIC_LDO_VCN18_LP_SEL_ADDR,
	 PMIC_LDO_VCN18_LP_SEL_MASK, PMIC_LDO_VCN18_LP_SEL_SHIFT},
	{PMIC_DA_QI_VCN18_MODE, PMIC_DA_QI_VCN18_MODE_ADDR,
	 PMIC_DA_QI_VCN18_MODE_MASK, PMIC_DA_QI_VCN18_MODE_SHIFT},
	{PMIC_LDO_VCN18_STBTD, PMIC_LDO_VCN18_STBTD_ADDR, PMIC_LDO_VCN18_STBTD_MASK,
	 PMIC_LDO_VCN18_STBTD_SHIFT},
	{PMIC_LDO_VCN18_EN_SEL, PMIC_LDO_VCN18_EN_SEL_ADDR,
	 PMIC_LDO_VCN18_EN_SEL_MASK, PMIC_LDO_VCN18_EN_SEL_SHIFT},
	{PMIC_DA_QI_VCN18_STB, PMIC_DA_QI_VCN18_STB_ADDR, PMIC_DA_QI_VCN18_STB_MASK,
	 PMIC_DA_QI_VCN18_STB_SHIFT},
	{PMIC_DA_QI_VCN18_EN, PMIC_DA_QI_VCN18_EN_ADDR, PMIC_DA_QI_VCN18_EN_MASK,
	 PMIC_DA_QI_VCN18_EN_SHIFT},
	{PMIC_LDO_VCN18_OCFB_EN, PMIC_LDO_VCN18_OCFB_EN_ADDR,
	 PMIC_LDO_VCN18_OCFB_EN_MASK, PMIC_LDO_VCN18_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VCN18_OCFB_EN, PMIC_DA_QI_VCN18_OCFB_EN_ADDR,
	 PMIC_DA_QI_VCN18_OCFB_EN_MASK, PMIC_DA_QI_VCN18_OCFB_EN_SHIFT},
	{PMIC_LDO_VCAMA_LP_MODE, PMIC_LDO_VCAMA_LP_MODE_ADDR,
	 PMIC_LDO_VCAMA_LP_MODE_MASK, PMIC_LDO_VCAMA_LP_MODE_SHIFT},
	{PMIC_LDO_VCAMA_EN, PMIC_LDO_VCAMA_EN_ADDR, PMIC_LDO_VCAMA_EN_MASK,
	 PMIC_LDO_VCAMA_EN_SHIFT},
	{PMIC_DA_QI_VCAMA_MODE, PMIC_DA_QI_VCAMA_MODE_ADDR,
	 PMIC_DA_QI_VCAMA_MODE_MASK, PMIC_DA_QI_VCAMA_MODE_SHIFT},
	{PMIC_LDO_VCAMA_STBTD, PMIC_LDO_VCAMA_STBTD_ADDR, PMIC_LDO_VCAMA_STBTD_MASK,
	 PMIC_LDO_VCAMA_STBTD_SHIFT},
	{PMIC_DA_QI_VCAMA_STB, PMIC_DA_QI_VCAMA_STB_ADDR, PMIC_DA_QI_VCAMA_STB_MASK,
	 PMIC_DA_QI_VCAMA_STB_SHIFT},
	{PMIC_DA_QI_VCAMA_EN, PMIC_DA_QI_VCAMA_EN_ADDR, PMIC_DA_QI_VCAMA_EN_MASK,
	 PMIC_DA_QI_VCAMA_EN_SHIFT},
	{PMIC_LDO_VCAMA_OCFB_EN, PMIC_LDO_VCAMA_OCFB_EN_ADDR,
	 PMIC_LDO_VCAMA_OCFB_EN_MASK, PMIC_LDO_VCAMA_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VCAMA_OCFB_EN, PMIC_DA_QI_VCAMA_OCFB_EN_ADDR,
	 PMIC_DA_QI_VCAMA_OCFB_EN_MASK, PMIC_DA_QI_VCAMA_OCFB_EN_SHIFT},
	{PMIC_LDO_VCAMIO_LP_MODE, PMIC_LDO_VCAMIO_LP_MODE_ADDR,
	 PMIC_LDO_VCAMIO_LP_MODE_MASK, PMIC_LDO_VCAMIO_LP_MODE_SHIFT},
	{PMIC_LDO_VCAMIO_EN, PMIC_LDO_VCAMIO_EN_ADDR, PMIC_LDO_VCAMIO_EN_MASK,
	 PMIC_LDO_VCAMIO_EN_SHIFT},
	{PMIC_DA_QI_VCAMIO_MODE, PMIC_DA_QI_VCAMIO_MODE_ADDR,
	 PMIC_DA_QI_VCAMIO_MODE_MASK, PMIC_DA_QI_VCAMIO_MODE_SHIFT},
	{PMIC_LDO_VCAMIO_STBTD, PMIC_LDO_VCAMIO_STBTD_ADDR,
	 PMIC_LDO_VCAMIO_STBTD_MASK, PMIC_LDO_VCAMIO_STBTD_SHIFT},
	{PMIC_DA_QI_VCAMIO_STB, PMIC_DA_QI_VCAMIO_STB_ADDR,
	 PMIC_DA_QI_VCAMIO_STB_MASK, PMIC_DA_QI_VCAMIO_STB_SHIFT},
	{PMIC_DA_QI_VCAMIO_EN, PMIC_DA_QI_VCAMIO_EN_ADDR, PMIC_DA_QI_VCAMIO_EN_MASK,
	 PMIC_DA_QI_VCAMIO_EN_SHIFT},
	{PMIC_LDO_VCAMIO_OCFB_EN, PMIC_LDO_VCAMIO_OCFB_EN_ADDR,
	 PMIC_LDO_VCAMIO_OCFB_EN_MASK, PMIC_LDO_VCAMIO_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VCAMIO_OCFB_EN, PMIC_DA_QI_VCAMIO_OCFB_EN_ADDR,
	 PMIC_DA_QI_VCAMIO_OCFB_EN_MASK, PMIC_DA_QI_VCAMIO_OCFB_EN_SHIFT},
	{PMIC_LDO_VCAMD_LP_MODE, PMIC_LDO_VCAMD_LP_MODE_ADDR,
	 PMIC_LDO_VCAMD_LP_MODE_MASK, PMIC_LDO_VCAMD_LP_MODE_SHIFT},
	{PMIC_LDO_VCAMD_EN, PMIC_LDO_VCAMD_EN_ADDR, PMIC_LDO_VCAMD_EN_MASK,
	 PMIC_LDO_VCAMD_EN_SHIFT},
	{PMIC_DA_QI_VCAMD_MODE, PMIC_DA_QI_VCAMD_MODE_ADDR,
	 PMIC_DA_QI_VCAMD_MODE_MASK, PMIC_DA_QI_VCAMD_MODE_SHIFT},
	{PMIC_LDO_VCAMD_STBTD, PMIC_LDO_VCAMD_STBTD_ADDR, PMIC_LDO_VCAMD_STBTD_MASK,
	 PMIC_LDO_VCAMD_STBTD_SHIFT},
	{PMIC_DA_QI_VCAMD_STB, PMIC_DA_QI_VCAMD_STB_ADDR, PMIC_DA_QI_VCAMD_STB_MASK,
	 PMIC_DA_QI_VCAMD_STB_SHIFT},
	{PMIC_DA_QI_VCAMD_EN, PMIC_DA_QI_VCAMD_EN_ADDR, PMIC_DA_QI_VCAMD_EN_MASK,
	 PMIC_DA_QI_VCAMD_EN_SHIFT},
	{PMIC_LDO_VCAMD_OCFB_EN, PMIC_LDO_VCAMD_OCFB_EN_ADDR,
	 PMIC_LDO_VCAMD_OCFB_EN_MASK, PMIC_LDO_VCAMD_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VCAMD_OCFB_EN, PMIC_DA_QI_VCAMD_OCFB_EN_ADDR,
	 PMIC_DA_QI_VCAMD_OCFB_EN_MASK, PMIC_DA_QI_VCAMD_OCFB_EN_SHIFT},
	{PMIC_LDO_VAUX18_LP_MODE, PMIC_LDO_VAUX18_LP_MODE_ADDR,
	 PMIC_LDO_VAUX18_LP_MODE_MASK, PMIC_LDO_VAUX18_LP_MODE_SHIFT},
	{PMIC_LDO_VAUX18_EN, PMIC_LDO_VAUX18_EN_ADDR, PMIC_LDO_VAUX18_EN_MASK,
	 PMIC_LDO_VAUX18_EN_SHIFT},
	{PMIC_LDO_VAUX18_LP_CTRL, PMIC_LDO_VAUX18_LP_CTRL_ADDR,
	 PMIC_LDO_VAUX18_LP_CTRL_MASK, PMIC_LDO_VAUX18_LP_CTRL_SHIFT},
	{PMIC_LDO_VAUX18_EN_CTRL, PMIC_LDO_VAUX18_EN_CTRL_ADDR,
	 PMIC_LDO_VAUX18_EN_CTRL_MASK, PMIC_LDO_VAUX18_EN_CTRL_SHIFT},
	{PMIC_LDO_VAUX18_LP_SEL, PMIC_LDO_VAUX18_LP_SEL_ADDR,
	 PMIC_LDO_VAUX18_LP_SEL_MASK, PMIC_LDO_VAUX18_LP_SEL_SHIFT},
	{PMIC_DA_QI_VAUX18_MODE, PMIC_DA_QI_VAUX18_MODE_ADDR,
	 PMIC_DA_QI_VAUX18_MODE_MASK, PMIC_DA_QI_VAUX18_MODE_SHIFT},
	{PMIC_LDO_VAUX18_STBTD, PMIC_LDO_VAUX18_STBTD_ADDR,
	 PMIC_LDO_VAUX18_STBTD_MASK, PMIC_LDO_VAUX18_STBTD_SHIFT},
	{PMIC_LDO_VAUX18_EN_SEL, PMIC_LDO_VAUX18_EN_SEL_ADDR,
	 PMIC_LDO_VAUX18_EN_SEL_MASK, PMIC_LDO_VAUX18_EN_SEL_SHIFT},
	{PMIC_DA_QI_VAUX18_STB, PMIC_DA_QI_VAUX18_STB_ADDR,
	 PMIC_DA_QI_VAUX18_STB_MASK, PMIC_DA_QI_VAUX18_STB_SHIFT},
	{PMIC_DA_QI_VAUX18_EN, PMIC_DA_QI_VAUX18_EN_ADDR, PMIC_DA_QI_VAUX18_EN_MASK,
	 PMIC_DA_QI_VAUX18_EN_SHIFT},
	{PMIC_LDO_VAUX18_OCFB_EN, PMIC_LDO_VAUX18_OCFB_EN_ADDR,
	 PMIC_LDO_VAUX18_OCFB_EN_MASK, PMIC_LDO_VAUX18_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VAUX18_OCFB_EN, PMIC_DA_QI_VAUX18_OCFB_EN_ADDR,
	 PMIC_DA_QI_VAUX18_OCFB_EN_MASK, PMIC_DA_QI_VAUX18_OCFB_EN_SHIFT},
	{PMIC_LDO_VAUD28_LP_MODE, PMIC_LDO_VAUD28_LP_MODE_ADDR,
	 PMIC_LDO_VAUD28_LP_MODE_MASK, PMIC_LDO_VAUD28_LP_MODE_SHIFT},
	{PMIC_LDO_VAUD28_EN, PMIC_LDO_VAUD28_EN_ADDR, PMIC_LDO_VAUD28_EN_MASK,
	 PMIC_LDO_VAUD28_EN_SHIFT},
	{PMIC_LDO_VAUD28_LP_CTRL, PMIC_LDO_VAUD28_LP_CTRL_ADDR,
	 PMIC_LDO_VAUD28_LP_CTRL_MASK, PMIC_LDO_VAUD28_LP_CTRL_SHIFT},
	{PMIC_LDO_VAUD28_EN_CTRL, PMIC_LDO_VAUD28_EN_CTRL_ADDR,
	 PMIC_LDO_VAUD28_EN_CTRL_MASK, PMIC_LDO_VAUD28_EN_CTRL_SHIFT},
	{PMIC_LDO_VAUD28_LP_SEL, PMIC_LDO_VAUD28_LP_SEL_ADDR,
	 PMIC_LDO_VAUD28_LP_SEL_MASK, PMIC_LDO_VAUD28_LP_SEL_SHIFT},
	{PMIC_DA_QI_VAUD28_MODE, PMIC_DA_QI_VAUD28_MODE_ADDR,
	 PMIC_DA_QI_VAUD28_MODE_MASK, PMIC_DA_QI_VAUD28_MODE_SHIFT},
	{PMIC_LDO_VAUD28_STBTD, PMIC_LDO_VAUD28_STBTD_ADDR,
	 PMIC_LDO_VAUD28_STBTD_MASK, PMIC_LDO_VAUD28_STBTD_SHIFT},
	{PMIC_LDO_VAUD28_EN_SEL, PMIC_LDO_VAUD28_EN_SEL_ADDR,
	 PMIC_LDO_VAUD28_EN_SEL_MASK, PMIC_LDO_VAUD28_EN_SEL_SHIFT},
	{PMIC_DA_QI_VAUD28_STB, PMIC_DA_QI_VAUD28_STB_ADDR,
	 PMIC_DA_QI_VAUD28_STB_MASK, PMIC_DA_QI_VAUD28_STB_SHIFT},
	{PMIC_DA_QI_VAUD28_EN, PMIC_DA_QI_VAUD28_EN_ADDR, PMIC_DA_QI_VAUD28_EN_MASK,
	 PMIC_DA_QI_VAUD28_EN_SHIFT},
	{PMIC_LDO_VAUD28_OCFB_EN, PMIC_LDO_VAUD28_OCFB_EN_ADDR,
	 PMIC_LDO_VAUD28_OCFB_EN_MASK, PMIC_LDO_VAUD28_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VAUD28_OCFB_EN, PMIC_DA_QI_VAUD28_OCFB_EN_ADDR,
	 PMIC_DA_QI_VAUD28_OCFB_EN_MASK, PMIC_DA_QI_VAUD28_OCFB_EN_SHIFT},
	{PMIC_LDO_VSRAM_PROC_LP_MODE, PMIC_LDO_VSRAM_PROC_LP_MODE_ADDR,
	 PMIC_LDO_VSRAM_PROC_LP_MODE_MASK, PMIC_LDO_VSRAM_PROC_LP_MODE_SHIFT},
	{PMIC_LDO_VSRAM_PROC_EN, PMIC_LDO_VSRAM_PROC_EN_ADDR,
	 PMIC_LDO_VSRAM_PROC_EN_MASK, PMIC_LDO_VSRAM_PROC_EN_SHIFT},
	{PMIC_LDO_VSRAM_PROC_LP_CTRL, PMIC_LDO_VSRAM_PROC_LP_CTRL_ADDR,
	 PMIC_LDO_VSRAM_PROC_LP_CTRL_MASK, PMIC_LDO_VSRAM_PROC_LP_CTRL_SHIFT},
	{PMIC_LDO_VSRAM_PROC_EN_CTRL, PMIC_LDO_VSRAM_PROC_EN_CTRL_ADDR,
	 PMIC_LDO_VSRAM_PROC_EN_CTRL_MASK, PMIC_LDO_VSRAM_PROC_EN_CTRL_SHIFT},
	{PMIC_LDO_VSRAM_PROC_LP_SEL, PMIC_LDO_VSRAM_PROC_LP_SEL_ADDR,
	 PMIC_LDO_VSRAM_PROC_LP_SEL_MASK, PMIC_LDO_VSRAM_PROC_LP_SEL_SHIFT},
	{PMIC_DA_QI_VSRAM_PROC_MODE, PMIC_DA_QI_VSRAM_PROC_MODE_ADDR,
	 PMIC_DA_QI_VSRAM_PROC_MODE_MASK, PMIC_DA_QI_VSRAM_PROC_MODE_SHIFT},
	{PMIC_LDO_VSRAM_PROC_STBTD, PMIC_LDO_VSRAM_PROC_STBTD_ADDR,
	 PMIC_LDO_VSRAM_PROC_STBTD_MASK, PMIC_LDO_VSRAM_PROC_STBTD_SHIFT},
	{PMIC_LDO_VSRAM_PROC_EN_SEL, PMIC_LDO_VSRAM_PROC_EN_SEL_ADDR,
	 PMIC_LDO_VSRAM_PROC_EN_SEL_MASK, PMIC_LDO_VSRAM_PROC_EN_SEL_SHIFT},
	{PMIC_DA_QI_VSRAM_PROC_STB, PMIC_DA_QI_VSRAM_PROC_STB_ADDR,
	 PMIC_DA_QI_VSRAM_PROC_STB_MASK, PMIC_DA_QI_VSRAM_PROC_STB_SHIFT},
	{PMIC_DA_QI_VSRAM_PROC_EN, PMIC_DA_QI_VSRAM_PROC_EN_ADDR,
	 PMIC_DA_QI_VSRAM_PROC_EN_MASK, PMIC_DA_QI_VSRAM_PROC_EN_SHIFT},
	{PMIC_LDO_VSRAM_PROC_OCFB_EN, PMIC_LDO_VSRAM_PROC_OCFB_EN_ADDR,
	 PMIC_LDO_VSRAM_PROC_OCFB_EN_MASK, PMIC_LDO_VSRAM_PROC_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VSRAM_PROC_OCFB_EN, PMIC_DA_QI_VSRAM_PROC_OCFB_EN_ADDR,
	 PMIC_DA_QI_VSRAM_PROC_OCFB_EN_MASK, PMIC_DA_QI_VSRAM_PROC_OCFB_EN_SHIFT},
	{PMIC_LDO_VDRAM_LP_MODE, PMIC_LDO_VDRAM_LP_MODE_ADDR,
	 PMIC_LDO_VDRAM_LP_MODE_MASK, PMIC_LDO_VDRAM_LP_MODE_SHIFT},
	{PMIC_LDO_VDRAM_EN, PMIC_LDO_VDRAM_EN_ADDR, PMIC_LDO_VDRAM_EN_MASK,
	 PMIC_LDO_VDRAM_EN_SHIFT},
	{PMIC_LDO_VDRAM_LP_CTRL, PMIC_LDO_VDRAM_LP_CTRL_ADDR,
	 PMIC_LDO_VDRAM_LP_CTRL_MASK, PMIC_LDO_VDRAM_LP_CTRL_SHIFT},
	{PMIC_LDO_VDRAM_LP_SEL, PMIC_LDO_VDRAM_LP_SEL_ADDR,
	 PMIC_LDO_VDRAM_LP_SEL_MASK, PMIC_LDO_VDRAM_LP_SEL_SHIFT},
	{PMIC_DA_QI_VDRAM_MODE, PMIC_DA_QI_VDRAM_MODE_ADDR,
	 PMIC_DA_QI_VDRAM_MODE_MASK, PMIC_DA_QI_VDRAM_MODE_SHIFT},
	{PMIC_LDO_VDRAM_STBTD, PMIC_LDO_VDRAM_STBTD_ADDR, PMIC_LDO_VDRAM_STBTD_MASK,
	 PMIC_LDO_VDRAM_STBTD_SHIFT},
	{PMIC_DA_QI_VDRAM_STB, PMIC_DA_QI_VDRAM_STB_ADDR, PMIC_DA_QI_VDRAM_STB_MASK,
	 PMIC_DA_QI_VDRAM_STB_SHIFT},
	{PMIC_DA_QI_VDRAM_EN, PMIC_DA_QI_VDRAM_EN_ADDR, PMIC_DA_QI_VDRAM_EN_MASK,
	 PMIC_DA_QI_VDRAM_EN_SHIFT},
	{PMIC_LDO_VDRAM_OCFB_EN, PMIC_LDO_VDRAM_OCFB_EN_ADDR,
	 PMIC_LDO_VDRAM_OCFB_EN_MASK, PMIC_LDO_VDRAM_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VDRAM_OCFB_EN, PMIC_DA_QI_VDRAM_OCFB_EN_ADDR,
	 PMIC_DA_QI_VDRAM_OCFB_EN_MASK, PMIC_DA_QI_VDRAM_OCFB_EN_SHIFT},
	{PMIC_LDO_VDRAM_FAST_TRAN_DL_EN, PMIC_LDO_VDRAM_FAST_TRAN_DL_EN_ADDR,
	 PMIC_LDO_VDRAM_FAST_TRAN_DL_EN_MASK, PMIC_LDO_VDRAM_FAST_TRAN_DL_EN_SHIFT},
	{PMIC_LDO_VDRAM_FAST_TRAN_DL_CTRL, PMIC_LDO_VDRAM_FAST_TRAN_DL_CTRL_ADDR,
	 PMIC_LDO_VDRAM_FAST_TRAN_DL_CTRL_MASK,
	 PMIC_LDO_VDRAM_FAST_TRAN_DL_CTRL_SHIFT},
	{PMIC_LDO_VDRAM_FAST_TRAN_DL_SRCLKEN_SEL,
	 PMIC_LDO_VDRAM_FAST_TRAN_DL_SRCLKEN_SEL_ADDR,
	 PMIC_LDO_VDRAM_FAST_TRAN_DL_SRCLKEN_SEL_MASK,
	 PMIC_LDO_VDRAM_FAST_TRAN_DL_SRCLKEN_SEL_SHIFT},
	{PMIC_DA_QI_VDRAM_FAST_TRAN_DL_EN, PMIC_DA_QI_VDRAM_FAST_TRAN_DL_EN_ADDR,
	 PMIC_DA_QI_VDRAM_FAST_TRAN_DL_EN_MASK,
	 PMIC_DA_QI_VDRAM_FAST_TRAN_DL_EN_SHIFT},
	{PMIC_LDO_VDRAM_FAST_TRAN_CL_EN, PMIC_LDO_VDRAM_FAST_TRAN_CL_EN_ADDR,
	 PMIC_LDO_VDRAM_FAST_TRAN_CL_EN_MASK, PMIC_LDO_VDRAM_FAST_TRAN_CL_EN_SHIFT},
	{PMIC_LDO_VDRAM_FAST_TRAN_CL_CTRL, PMIC_LDO_VDRAM_FAST_TRAN_CL_CTRL_ADDR,
	 PMIC_LDO_VDRAM_FAST_TRAN_CL_CTRL_MASK,
	 PMIC_LDO_VDRAM_FAST_TRAN_CL_CTRL_SHIFT},
	{PMIC_LDO_VDRAM_FAST_TRAN_CL_SRCLKEN_SEL,
	 PMIC_LDO_VDRAM_FAST_TRAN_CL_SRCLKEN_SEL_ADDR,
	 PMIC_LDO_VDRAM_FAST_TRAN_CL_SRCLKEN_SEL_MASK,
	 PMIC_LDO_VDRAM_FAST_TRAN_CL_SRCLKEN_SEL_SHIFT},
	{PMIC_DA_QI_VDRAM_FAST_TRAN_CL_EN, PMIC_DA_QI_VDRAM_FAST_TRAN_CL_EN_ADDR,
	 PMIC_DA_QI_VDRAM_FAST_TRAN_CL_EN_MASK,
	 PMIC_DA_QI_VDRAM_FAST_TRAN_CL_EN_SHIFT},
	{PMIC_LDO_VSIM1_LP_MODE, PMIC_LDO_VSIM1_LP_MODE_ADDR,
	 PMIC_LDO_VSIM1_LP_MODE_MASK, PMIC_LDO_VSIM1_LP_MODE_SHIFT},
	{PMIC_LDO_VSIM1_EN, PMIC_LDO_VSIM1_EN_ADDR, PMIC_LDO_VSIM1_EN_MASK,
	 PMIC_LDO_VSIM1_EN_SHIFT},
	{PMIC_LDO_VSIM1_LP_CTRL, PMIC_LDO_VSIM1_LP_CTRL_ADDR,
	 PMIC_LDO_VSIM1_LP_CTRL_MASK, PMIC_LDO_VSIM1_LP_CTRL_SHIFT},
	{PMIC_LDO_VSIM1_LP_SEL, PMIC_LDO_VSIM1_LP_SEL_ADDR,
	 PMIC_LDO_VSIM1_LP_SEL_MASK, PMIC_LDO_VSIM1_LP_SEL_SHIFT},
	{PMIC_DA_QI_VSIM1_MODE, PMIC_DA_QI_VSIM1_MODE_ADDR,
	 PMIC_DA_QI_VSIM1_MODE_MASK, PMIC_DA_QI_VSIM1_MODE_SHIFT},
	{PMIC_LDO_VSIM1_STBTD, PMIC_LDO_VSIM1_STBTD_ADDR, PMIC_LDO_VSIM1_STBTD_MASK,
	 PMIC_LDO_VSIM1_STBTD_SHIFT},
	{PMIC_DA_QI_VSIM1_STB, PMIC_DA_QI_VSIM1_STB_ADDR, PMIC_DA_QI_VSIM1_STB_MASK,
	 PMIC_DA_QI_VSIM1_STB_SHIFT},
	{PMIC_DA_QI_VSIM1_EN, PMIC_DA_QI_VSIM1_EN_ADDR, PMIC_DA_QI_VSIM1_EN_MASK,
	 PMIC_DA_QI_VSIM1_EN_SHIFT},
	{PMIC_LDO_VSIM1_OCFB_EN, PMIC_LDO_VSIM1_OCFB_EN_ADDR,
	 PMIC_LDO_VSIM1_OCFB_EN_MASK, PMIC_LDO_VSIM1_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VSIM1_OCFB_EN, PMIC_DA_QI_VSIM1_OCFB_EN_ADDR,
	 PMIC_DA_QI_VSIM1_OCFB_EN_MASK, PMIC_DA_QI_VSIM1_OCFB_EN_SHIFT},
	{PMIC_LDO_VSIM2_LP_MODE, PMIC_LDO_VSIM2_LP_MODE_ADDR,
	 PMIC_LDO_VSIM2_LP_MODE_MASK, PMIC_LDO_VSIM2_LP_MODE_SHIFT},
	{PMIC_LDO_VSIM2_EN, PMIC_LDO_VSIM2_EN_ADDR, PMIC_LDO_VSIM2_EN_MASK,
	 PMIC_LDO_VSIM2_EN_SHIFT},
	{PMIC_LDO_VSIM2_LP_CTRL, PMIC_LDO_VSIM2_LP_CTRL_ADDR,
	 PMIC_LDO_VSIM2_LP_CTRL_MASK, PMIC_LDO_VSIM2_LP_CTRL_SHIFT},
	{PMIC_LDO_VSIM2_LP_SEL, PMIC_LDO_VSIM2_LP_SEL_ADDR,
	 PMIC_LDO_VSIM2_LP_SEL_MASK, PMIC_LDO_VSIM2_LP_SEL_SHIFT},
	{PMIC_DA_QI_VSIM2_MODE, PMIC_DA_QI_VSIM2_MODE_ADDR,
	 PMIC_DA_QI_VSIM2_MODE_MASK, PMIC_DA_QI_VSIM2_MODE_SHIFT},
	{PMIC_LDO_VSIM2_STBTD, PMIC_LDO_VSIM2_STBTD_ADDR, PMIC_LDO_VSIM2_STBTD_MASK,
	 PMIC_LDO_VSIM2_STBTD_SHIFT},
	{PMIC_DA_QI_VSIM2_STB, PMIC_DA_QI_VSIM2_STB_ADDR, PMIC_DA_QI_VSIM2_STB_MASK,
	 PMIC_DA_QI_VSIM2_STB_SHIFT},
	{PMIC_DA_QI_VSIM2_EN, PMIC_DA_QI_VSIM2_EN_ADDR, PMIC_DA_QI_VSIM2_EN_MASK,
	 PMIC_DA_QI_VSIM2_EN_SHIFT},
	{PMIC_LDO_VSIM2_OCFB_EN, PMIC_LDO_VSIM2_OCFB_EN_ADDR,
	 PMIC_LDO_VSIM2_OCFB_EN_MASK, PMIC_LDO_VSIM2_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VSIM2_OCFB_EN, PMIC_DA_QI_VSIM2_OCFB_EN_ADDR,
	 PMIC_DA_QI_VSIM2_OCFB_EN_MASK, PMIC_DA_QI_VSIM2_OCFB_EN_SHIFT},
	{PMIC_LDO_VIO28_LP_MODE, PMIC_LDO_VIO28_LP_MODE_ADDR,
	 PMIC_LDO_VIO28_LP_MODE_MASK, PMIC_LDO_VIO28_LP_MODE_SHIFT},
	{PMIC_LDO_VIO28_EN, PMIC_LDO_VIO28_EN_ADDR, PMIC_LDO_VIO28_EN_MASK,
	 PMIC_LDO_VIO28_EN_SHIFT},
	{PMIC_LDO_VIO28_LP_CTRL, PMIC_LDO_VIO28_LP_CTRL_ADDR,
	 PMIC_LDO_VIO28_LP_CTRL_MASK, PMIC_LDO_VIO28_LP_CTRL_SHIFT},
	{PMIC_LDO_VIO28_LP_SEL, PMIC_LDO_VIO28_LP_SEL_ADDR,
	 PMIC_LDO_VIO28_LP_SEL_MASK, PMIC_LDO_VIO28_LP_SEL_SHIFT},
	{PMIC_DA_QI_VIO28_MODE, PMIC_DA_QI_VIO28_MODE_ADDR,
	 PMIC_DA_QI_VIO28_MODE_MASK, PMIC_DA_QI_VIO28_MODE_SHIFT},
	{PMIC_LDO_VIO28_STBTD, PMIC_LDO_VIO28_STBTD_ADDR, PMIC_LDO_VIO28_STBTD_MASK,
	 PMIC_LDO_VIO28_STBTD_SHIFT},
	{PMIC_DA_QI_VIO28_STB, PMIC_DA_QI_VIO28_STB_ADDR, PMIC_DA_QI_VIO28_STB_MASK,
	 PMIC_DA_QI_VIO28_STB_SHIFT},
	{PMIC_DA_QI_VIO28_EN, PMIC_DA_QI_VIO28_EN_ADDR, PMIC_DA_QI_VIO28_EN_MASK,
	 PMIC_DA_QI_VIO28_EN_SHIFT},
	{PMIC_LDO_VIO28_OCFB_EN, PMIC_LDO_VIO28_OCFB_EN_ADDR,
	 PMIC_LDO_VIO28_OCFB_EN_MASK, PMIC_LDO_VIO28_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VIO28_OCFB_EN, PMIC_DA_QI_VIO28_OCFB_EN_ADDR,
	 PMIC_DA_QI_VIO28_OCFB_EN_MASK, PMIC_DA_QI_VIO28_OCFB_EN_SHIFT},
	{PMIC_LDO_VMC_LP_MODE, PMIC_LDO_VMC_LP_MODE_ADDR, PMIC_LDO_VMC_LP_MODE_MASK,
	 PMIC_LDO_VMC_LP_MODE_SHIFT},
	{PMIC_LDO_VMC_EN, PMIC_LDO_VMC_EN_ADDR, PMIC_LDO_VMC_EN_MASK,
	 PMIC_LDO_VMC_EN_SHIFT},
	{PMIC_LDO_VMC_LP_CTRL, PMIC_LDO_VMC_LP_CTRL_ADDR, PMIC_LDO_VMC_LP_CTRL_MASK,
	 PMIC_LDO_VMC_LP_CTRL_SHIFT},
	{PMIC_LDO_VMC_LP_SEL, PMIC_LDO_VMC_LP_SEL_ADDR, PMIC_LDO_VMC_LP_SEL_MASK,
	 PMIC_LDO_VMC_LP_SEL_SHIFT},
	{PMIC_DA_QI_VMC_MODE, PMIC_DA_QI_VMC_MODE_ADDR, PMIC_DA_QI_VMC_MODE_MASK,
	 PMIC_DA_QI_VMC_MODE_SHIFT},
	{PMIC_LDO_VMC_STBTD, PMIC_LDO_VMC_STBTD_ADDR, PMIC_LDO_VMC_STBTD_MASK,
	 PMIC_LDO_VMC_STBTD_SHIFT},
	{PMIC_DA_QI_VMC_STB, PMIC_DA_QI_VMC_STB_ADDR, PMIC_DA_QI_VMC_STB_MASK,
	 PMIC_DA_QI_VMC_STB_SHIFT},
	{PMIC_DA_QI_VMC_EN, PMIC_DA_QI_VMC_EN_ADDR, PMIC_DA_QI_VMC_EN_MASK,
	 PMIC_DA_QI_VMC_EN_SHIFT},
	{PMIC_LDO_VMC_OCFB_EN, PMIC_LDO_VMC_OCFB_EN_ADDR, PMIC_LDO_VMC_OCFB_EN_MASK,
	 PMIC_LDO_VMC_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VMC_OCFB_EN, PMIC_DA_QI_VMC_OCFB_EN_ADDR,
	 PMIC_DA_QI_VMC_OCFB_EN_MASK, PMIC_DA_QI_VMC_OCFB_EN_SHIFT},
	{PMIC_LDO_VMC_FAST_TRAN_DL_EN, PMIC_LDO_VMC_FAST_TRAN_DL_EN_ADDR,
	 PMIC_LDO_VMC_FAST_TRAN_DL_EN_MASK, PMIC_LDO_VMC_FAST_TRAN_DL_EN_SHIFT},
	{PMIC_LDO_VMC_FAST_TRAN_DL_CTRL, PMIC_LDO_VMC_FAST_TRAN_DL_CTRL_ADDR,
	 PMIC_LDO_VMC_FAST_TRAN_DL_CTRL_MASK, PMIC_LDO_VMC_FAST_TRAN_DL_CTRL_SHIFT},
	{PMIC_LDO_VMC_FAST_TRAN_DL_SRCLKEN_SEL, PMIC_LDO_VMC_FAST_TRAN_DL_SRCLKEN_SEL_ADDR,
	 PMIC_LDO_VMC_FAST_TRAN_DL_SRCLKEN_SEL_MASK,
	 PMIC_LDO_VMC_FAST_TRAN_DL_SRCLKEN_SEL_SHIFT},
	{PMIC_DA_QI_VMC_FAST_TRAN_DL_EN, PMIC_DA_QI_VMC_FAST_TRAN_DL_EN_ADDR,
	 PMIC_DA_QI_VMC_FAST_TRAN_DL_EN_MASK, PMIC_DA_QI_VMC_FAST_TRAN_DL_EN_SHIFT},
	{PMIC_LDO_VMC_FAST_TRAN_CL_EN, PMIC_LDO_VMC_FAST_TRAN_CL_EN_ADDR,
	 PMIC_LDO_VMC_FAST_TRAN_CL_EN_MASK, PMIC_LDO_VMC_FAST_TRAN_CL_EN_SHIFT},
	{PMIC_LDO_VMC_FAST_TRAN_CL_CTRL, PMIC_LDO_VMC_FAST_TRAN_CL_CTRL_ADDR,
	 PMIC_LDO_VMC_FAST_TRAN_CL_CTRL_MASK, PMIC_LDO_VMC_FAST_TRAN_CL_CTRL_SHIFT},
	{PMIC_LDO_VMC_FAST_TRAN_CL_SRCLKEN_SEL, PMIC_LDO_VMC_FAST_TRAN_CL_SRCLKEN_SEL_ADDR,
	 PMIC_LDO_VMC_FAST_TRAN_CL_SRCLKEN_SEL_MASK,
	 PMIC_LDO_VMC_FAST_TRAN_CL_SRCLKEN_SEL_SHIFT},
	{PMIC_DA_QI_VMC_FAST_TRAN_CL_EN, PMIC_DA_QI_VMC_FAST_TRAN_CL_EN_ADDR,
	 PMIC_DA_QI_VMC_FAST_TRAN_CL_EN_MASK, PMIC_DA_QI_VMC_FAST_TRAN_CL_EN_SHIFT},
	{PMIC_LDO_VMCH_LP_MODE, PMIC_LDO_VMCH_LP_MODE_ADDR,
	 PMIC_LDO_VMCH_LP_MODE_MASK, PMIC_LDO_VMCH_LP_MODE_SHIFT},
	{PMIC_LDO_VMCH_EN, PMIC_LDO_VMCH_EN_ADDR, PMIC_LDO_VMCH_EN_MASK,
	 PMIC_LDO_VMCH_EN_SHIFT},
	{PMIC_LDO_VMCH_LP_CTRL, PMIC_LDO_VMCH_LP_CTRL_ADDR,
	 PMIC_LDO_VMCH_LP_CTRL_MASK, PMIC_LDO_VMCH_LP_CTRL_SHIFT},
	{PMIC_LDO_VMCH_LP_SEL, PMIC_LDO_VMCH_LP_SEL_ADDR, PMIC_LDO_VMCH_LP_SEL_MASK,
	 PMIC_LDO_VMCH_LP_SEL_SHIFT},
	{PMIC_DA_QI_VMCH_MODE, PMIC_DA_QI_VMCH_MODE_ADDR, PMIC_DA_QI_VMCH_MODE_MASK,
	 PMIC_DA_QI_VMCH_MODE_SHIFT},
	{PMIC_LDO_VMCH_STBTD, PMIC_LDO_VMCH_STBTD_ADDR, PMIC_LDO_VMCH_STBTD_MASK,
	 PMIC_LDO_VMCH_STBTD_SHIFT},
	{PMIC_DA_QI_VMCH_STB, PMIC_DA_QI_VMCH_STB_ADDR, PMIC_DA_QI_VMCH_STB_MASK,
	 PMIC_DA_QI_VMCH_STB_SHIFT},
	{PMIC_DA_QI_VMCH_EN, PMIC_DA_QI_VMCH_EN_ADDR, PMIC_DA_QI_VMCH_EN_MASK,
	 PMIC_DA_QI_VMCH_EN_SHIFT},
	{PMIC_LDO_VMCH_OCFB_EN, PMIC_LDO_VMCH_OCFB_EN_ADDR,
	 PMIC_LDO_VMCH_OCFB_EN_MASK, PMIC_LDO_VMCH_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VMCH_OCFB_EN, PMIC_DA_QI_VMCH_OCFB_EN_ADDR,
	 PMIC_DA_QI_VMCH_OCFB_EN_MASK, PMIC_DA_QI_VMCH_OCFB_EN_SHIFT},
	{PMIC_LDO_VMCH_FAST_TRAN_DL_EN, PMIC_LDO_VMCH_FAST_TRAN_DL_EN_ADDR,
	 PMIC_LDO_VMCH_FAST_TRAN_DL_EN_MASK, PMIC_LDO_VMCH_FAST_TRAN_DL_EN_SHIFT},
	{PMIC_LDO_VMCH_FAST_TRAN_DL_CTRL, PMIC_LDO_VMCH_FAST_TRAN_DL_CTRL_ADDR,
	 PMIC_LDO_VMCH_FAST_TRAN_DL_CTRL_MASK, PMIC_LDO_VMCH_FAST_TRAN_DL_CTRL_SHIFT},
	{PMIC_LDO_VMCH_FAST_TRAN_DL_SRCLKEN_SEL, PMIC_LDO_VMCH_FAST_TRAN_DL_SRCLKEN_SEL_ADDR,
	 PMIC_LDO_VMCH_FAST_TRAN_DL_SRCLKEN_SEL_MASK,
	 PMIC_LDO_VMCH_FAST_TRAN_DL_SRCLKEN_SEL_SHIFT},
	{PMIC_DA_QI_VMCH_FAST_TRAN_DL_EN, PMIC_DA_QI_VMCH_FAST_TRAN_DL_EN_ADDR,
	 PMIC_DA_QI_VMCH_FAST_TRAN_DL_EN_MASK, PMIC_DA_QI_VMCH_FAST_TRAN_DL_EN_SHIFT},
	{PMIC_LDO_VMCH_FAST_TRAN_CL_EN, PMIC_LDO_VMCH_FAST_TRAN_CL_EN_ADDR,
	 PMIC_LDO_VMCH_FAST_TRAN_CL_EN_MASK, PMIC_LDO_VMCH_FAST_TRAN_CL_EN_SHIFT},
	{PMIC_LDO_VMCH_FAST_TRAN_CL_CTRL, PMIC_LDO_VMCH_FAST_TRAN_CL_CTRL_ADDR,
	 PMIC_LDO_VMCH_FAST_TRAN_CL_CTRL_MASK, PMIC_LDO_VMCH_FAST_TRAN_CL_CTRL_SHIFT},
	{PMIC_LDO_VMCH_FAST_TRAN_CL_SRCLKEN_SEL, PMIC_LDO_VMCH_FAST_TRAN_CL_SRCLKEN_SEL_ADDR,
	 PMIC_LDO_VMCH_FAST_TRAN_CL_SRCLKEN_SEL_MASK,
	 PMIC_LDO_VMCH_FAST_TRAN_CL_SRCLKEN_SEL_SHIFT},
	{PMIC_DA_QI_VMCH_FAST_TRAN_CL_EN, PMIC_DA_QI_VMCH_FAST_TRAN_CL_EN_ADDR,
	 PMIC_DA_QI_VMCH_FAST_TRAN_CL_EN_MASK, PMIC_DA_QI_VMCH_FAST_TRAN_CL_EN_SHIFT},
	{PMIC_LDO_VUSB33_LP_MODE, PMIC_LDO_VUSB33_LP_MODE_ADDR,
	 PMIC_LDO_VUSB33_LP_MODE_MASK, PMIC_LDO_VUSB33_LP_MODE_SHIFT},
	{PMIC_LDO_VUSB33_EN, PMIC_LDO_VUSB33_EN_ADDR, PMIC_LDO_VUSB33_EN_MASK,
	 PMIC_LDO_VUSB33_EN_SHIFT},
	{PMIC_LDO_VUSB33_LP_CTRL, PMIC_LDO_VUSB33_LP_CTRL_ADDR,
	 PMIC_LDO_VUSB33_LP_CTRL_MASK, PMIC_LDO_VUSB33_LP_CTRL_SHIFT},
	{PMIC_LDO_VUSB33_LP_SEL, PMIC_LDO_VUSB33_LP_SEL_ADDR,
	 PMIC_LDO_VUSB33_LP_SEL_MASK, PMIC_LDO_VUSB33_LP_SEL_SHIFT},
	{PMIC_DA_QI_VUSB33_MODE, PMIC_DA_QI_VUSB33_MODE_ADDR,
	 PMIC_DA_QI_VUSB33_MODE_MASK, PMIC_DA_QI_VUSB33_MODE_SHIFT},
	{PMIC_LDO_VUSB33_STBTD, PMIC_LDO_VUSB33_STBTD_ADDR,
	 PMIC_LDO_VUSB33_STBTD_MASK, PMIC_LDO_VUSB33_STBTD_SHIFT},
	{PMIC_DA_QI_VUSB33_STB, PMIC_DA_QI_VUSB33_STB_ADDR,
	 PMIC_DA_QI_VUSB33_STB_MASK, PMIC_DA_QI_VUSB33_STB_SHIFT},
	{PMIC_DA_QI_VUSB33_EN, PMIC_DA_QI_VUSB33_EN_ADDR, PMIC_DA_QI_VUSB33_EN_MASK,
	 PMIC_DA_QI_VUSB33_EN_SHIFT},
	{PMIC_LDO_VUSB33_OCFB_EN, PMIC_LDO_VUSB33_OCFB_EN_ADDR,
	 PMIC_LDO_VUSB33_OCFB_EN_MASK, PMIC_LDO_VUSB33_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VUSB33_OCFB_EN, PMIC_DA_QI_VUSB33_OCFB_EN_ADDR,
	 PMIC_DA_QI_VUSB33_OCFB_EN_MASK, PMIC_DA_QI_VUSB33_OCFB_EN_SHIFT},
	{PMIC_LDO_VEMC33_LP_MODE, PMIC_LDO_VEMC33_LP_MODE_ADDR,
	 PMIC_LDO_VEMC33_LP_MODE_MASK, PMIC_LDO_VEMC33_LP_MODE_SHIFT},
	{PMIC_LDO_VEMC33_EN, PMIC_LDO_VEMC33_EN_ADDR, PMIC_LDO_VEMC33_EN_MASK,
	 PMIC_LDO_VEMC33_EN_SHIFT},
	{PMIC_LDO_VEMC33_LP_CTRL, PMIC_LDO_VEMC33_LP_CTRL_ADDR,
	 PMIC_LDO_VEMC33_LP_CTRL_MASK, PMIC_LDO_VEMC33_LP_CTRL_SHIFT},
	{PMIC_LDO_VEMC33_LP_SEL, PMIC_LDO_VEMC33_LP_SEL_ADDR,
	 PMIC_LDO_VEMC33_LP_SEL_MASK, PMIC_LDO_VEMC33_LP_SEL_SHIFT},
	{PMIC_DA_QI_VEMC33_MODE, PMIC_DA_QI_VEMC33_MODE_ADDR,
	 PMIC_DA_QI_VEMC33_MODE_MASK, PMIC_DA_QI_VEMC33_MODE_SHIFT},
	{PMIC_LDO_VEMC33_STBTD, PMIC_LDO_VEMC33_STBTD_ADDR,
	 PMIC_LDO_VEMC33_STBTD_MASK, PMIC_LDO_VEMC33_STBTD_SHIFT},
	{PMIC_DA_QI_VEMC33_STB, PMIC_DA_QI_VEMC33_STB_ADDR,
	 PMIC_DA_QI_VEMC33_STB_MASK, PMIC_DA_QI_VEMC33_STB_SHIFT},
	{PMIC_DA_QI_VEMC33_EN, PMIC_DA_QI_VEMC33_EN_ADDR, PMIC_DA_QI_VEMC33_EN_MASK,
	 PMIC_DA_QI_VEMC33_EN_SHIFT},
	{PMIC_LDO_VEMC33_OCFB_EN, PMIC_LDO_VEMC33_OCFB_EN_ADDR,
	 PMIC_LDO_VEMC33_OCFB_EN_MASK, PMIC_LDO_VEMC33_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VEMC33_OCFB_EN, PMIC_DA_QI_VEMC33_OCFB_EN_ADDR,
	 PMIC_DA_QI_VEMC33_OCFB_EN_MASK, PMIC_DA_QI_VEMC33_OCFB_EN_SHIFT},
	{PMIC_LDO_VEMC33_FAST_TRAN_DL_EN, PMIC_LDO_VEMC33_FAST_TRAN_DL_EN_ADDR,
	 PMIC_LDO_VEMC33_FAST_TRAN_DL_EN_MASK, PMIC_LDO_VEMC33_FAST_TRAN_DL_EN_SHIFT},
	{PMIC_LDO_VEMC33_FAST_TRAN_DL_CTRL, PMIC_LDO_VEMC33_FAST_TRAN_DL_CTRL_ADDR,
	 PMIC_LDO_VEMC33_FAST_TRAN_DL_CTRL_MASK,
	 PMIC_LDO_VEMC33_FAST_TRAN_DL_CTRL_SHIFT},
	{PMIC_LDO_VEMC33_FAST_TRAN_DL_SRCLKEN_SEL,
	 PMIC_LDO_VEMC33_FAST_TRAN_DL_SRCLKEN_SEL_ADDR,
	 PMIC_LDO_VEMC33_FAST_TRAN_DL_SRCLKEN_SEL_MASK,
	 PMIC_LDO_VEMC33_FAST_TRAN_DL_SRCLKEN_SEL_SHIFT},
	{PMIC_DA_QI_VEMC33_FAST_TRAN_DL_EN, PMIC_DA_QI_VEMC33_FAST_TRAN_DL_EN_ADDR,
	 PMIC_DA_QI_VEMC33_FAST_TRAN_DL_EN_MASK,
	 PMIC_DA_QI_VEMC33_FAST_TRAN_DL_EN_SHIFT},
	{PMIC_LDO_VEMC33_FAST_TRAN_CL_EN, PMIC_LDO_VEMC33_FAST_TRAN_CL_EN_ADDR,
	 PMIC_LDO_VEMC33_FAST_TRAN_CL_EN_MASK, PMIC_LDO_VEMC33_FAST_TRAN_CL_EN_SHIFT},
	{PMIC_LDO_VEMC33_FAST_TRAN_CL_CTRL, PMIC_LDO_VEMC33_FAST_TRAN_CL_CTRL_ADDR,
	 PMIC_LDO_VEMC33_FAST_TRAN_CL_CTRL_MASK,
	 PMIC_LDO_VEMC33_FAST_TRAN_CL_CTRL_SHIFT},
	{PMIC_LDO_VEMC33_FAST_TRAN_CL_SRCLKEN_SEL,
	 PMIC_LDO_VEMC33_FAST_TRAN_CL_SRCLKEN_SEL_ADDR,
	 PMIC_LDO_VEMC33_FAST_TRAN_CL_SRCLKEN_SEL_MASK,
	 PMIC_LDO_VEMC33_FAST_TRAN_CL_SRCLKEN_SEL_SHIFT},
	{PMIC_DA_QI_VEMC33_FAST_TRAN_CL_EN, PMIC_DA_QI_VEMC33_FAST_TRAN_CL_EN_ADDR,
	 PMIC_DA_QI_VEMC33_FAST_TRAN_CL_EN_MASK,
	 PMIC_DA_QI_VEMC33_FAST_TRAN_CL_EN_SHIFT},
	{PMIC_LDO_VIO18_LP_MODE, PMIC_LDO_VIO18_LP_MODE_ADDR,
	 PMIC_LDO_VIO18_LP_MODE_MASK, PMIC_LDO_VIO18_LP_MODE_SHIFT},
	{PMIC_LDO_VIO18_EN, PMIC_LDO_VIO18_EN_ADDR, PMIC_LDO_VIO18_EN_MASK,
	 PMIC_LDO_VIO18_EN_SHIFT},
	{PMIC_LDO_VIO18_LP_CTRL, PMIC_LDO_VIO18_LP_CTRL_ADDR,
	 PMIC_LDO_VIO18_LP_CTRL_MASK, PMIC_LDO_VIO18_LP_CTRL_SHIFT},
	{PMIC_LDO_VIO18_LP_SEL, PMIC_LDO_VIO18_LP_SEL_ADDR,
	 PMIC_LDO_VIO18_LP_SEL_MASK, PMIC_LDO_VIO18_LP_SEL_SHIFT},
	{PMIC_DA_QI_VIO18_MODE, PMIC_DA_QI_VIO18_MODE_ADDR,
	 PMIC_DA_QI_VIO18_MODE_MASK, PMIC_DA_QI_VIO18_MODE_SHIFT},
	{PMIC_LDO_VIO18_STBTD, PMIC_LDO_VIO18_STBTD_ADDR, PMIC_LDO_VIO18_STBTD_MASK,
	 PMIC_LDO_VIO18_STBTD_SHIFT},
	{PMIC_DA_QI_VIO18_STB, PMIC_DA_QI_VIO18_STB_ADDR, PMIC_DA_QI_VIO18_STB_MASK,
	 PMIC_DA_QI_VIO18_STB_SHIFT},
	{PMIC_DA_QI_VIO18_EN, PMIC_DA_QI_VIO18_EN_ADDR, PMIC_DA_QI_VIO18_EN_MASK,
	 PMIC_DA_QI_VIO18_EN_SHIFT},
	{PMIC_LDO_VIO18_OCFB_EN, PMIC_LDO_VIO18_OCFB_EN_ADDR,
	 PMIC_LDO_VIO18_OCFB_EN_MASK, PMIC_LDO_VIO18_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VIO18_OCFB_EN, PMIC_DA_QI_VIO18_OCFB_EN_ADDR,
	 PMIC_DA_QI_VIO18_OCFB_EN_MASK, PMIC_DA_QI_VIO18_OCFB_EN_SHIFT},
	{PMIC_LDO_VIBR_LP_MODE, PMIC_LDO_VIBR_LP_MODE_ADDR,
	 PMIC_LDO_VIBR_LP_MODE_MASK, PMIC_LDO_VIBR_LP_MODE_SHIFT},
	{PMIC_LDO_VIBR_EN, PMIC_LDO_VIBR_EN_ADDR, PMIC_LDO_VIBR_EN_MASK,
	 PMIC_LDO_VIBR_EN_SHIFT},
	{PMIC_DA_QI_VIBR_MODE, PMIC_DA_QI_VIBR_MODE_ADDR, PMIC_DA_QI_VIBR_MODE_MASK,
	 PMIC_DA_QI_VIBR_MODE_SHIFT},
	{PMIC_LDO_VIBR_STBTD, PMIC_LDO_VIBR_STBTD_ADDR, PMIC_LDO_VIBR_STBTD_MASK,
	 PMIC_LDO_VIBR_STBTD_SHIFT},
	{PMIC_DA_QI_VIBR_STB, PMIC_DA_QI_VIBR_STB_ADDR, PMIC_DA_QI_VIBR_STB_MASK,
	 PMIC_DA_QI_VIBR_STB_SHIFT},
	{PMIC_DA_QI_VIBR_EN, PMIC_DA_QI_VIBR_EN_ADDR, PMIC_DA_QI_VIBR_EN_MASK,
	 PMIC_DA_QI_VIBR_EN_SHIFT},
	{PMIC_LDO_VIBR_OCFB_EN, PMIC_LDO_VIBR_OCFB_EN_ADDR,
	 PMIC_LDO_VIBR_OCFB_EN_MASK, PMIC_LDO_VIBR_OCFB_EN_SHIFT},
	{PMIC_DA_QI_VIBR_OCFB_EN, PMIC_DA_QI_VIBR_OCFB_EN_ADDR,
	 PMIC_DA_QI_VIBR_OCFB_EN_MASK, PMIC_DA_QI_VIBR_OCFB_EN_SHIFT},
	{PMIC_RG_VTCXO28_CAL, PMIC_RG_VTCXO28_CAL_ADDR, PMIC_RG_VTCXO28_CAL_MASK,
	 PMIC_RG_VTCXO28_CAL_SHIFT},
	{PMIC_RG_VTCXO28_VOSEL, PMIC_RG_VTCXO28_VOSEL_ADDR,
	 PMIC_RG_VTCXO28_VOSEL_MASK, PMIC_RG_VTCXO28_VOSEL_SHIFT},
	{PMIC_RG_VTCXO28_NDIS_EN, PMIC_RG_VTCXO28_NDIS_EN_ADDR,
	 PMIC_RG_VTCXO28_NDIS_EN_MASK, PMIC_RG_VTCXO28_NDIS_EN_SHIFT},
	{PMIC_RG_VAUD28_CAL, PMIC_RG_VAUD28_CAL_ADDR, PMIC_RG_VAUD28_CAL_MASK,
	 PMIC_RG_VAUD28_CAL_SHIFT},
	{PMIC_RG_VAUD28_VOSEL, PMIC_RG_VAUD28_VOSEL_ADDR, PMIC_RG_VAUD28_VOSEL_MASK,
	 PMIC_RG_VAUD28_VOSEL_SHIFT},
	{PMIC_RG_VAUD28_NDIS_EN, PMIC_RG_VAUD28_NDIS_EN_ADDR,
	 PMIC_RG_VAUD28_NDIS_EN_MASK, PMIC_RG_VAUD28_NDIS_EN_SHIFT},
	{PMIC_RG_VCN28_CAL, PMIC_RG_VCN28_CAL_ADDR, PMIC_RG_VCN28_CAL_MASK,
	 PMIC_RG_VCN28_CAL_SHIFT},
	{PMIC_RG_VCN28_VOSEL, PMIC_RG_VCN28_VOSEL_ADDR, PMIC_RG_VCN28_VOSEL_MASK,
	 PMIC_RG_VCN28_VOSEL_SHIFT},
	{PMIC_RG_VCN28_NDIS_EN, PMIC_RG_VCN28_NDIS_EN_ADDR,
	 PMIC_RG_VCN28_NDIS_EN_MASK, PMIC_RG_VCN28_NDIS_EN_SHIFT},
	{PMIC_RG_VAUX18_CAL, PMIC_RG_VAUX18_CAL_ADDR, PMIC_RG_VAUX18_CAL_MASK,
	 PMIC_RG_VAUX18_CAL_SHIFT},
	{PMIC_RG_VAUX18_VOSEL, PMIC_RG_VAUX18_VOSEL_ADDR, PMIC_RG_VAUX18_VOSEL_MASK,
	 PMIC_RG_VAUX18_VOSEL_SHIFT},
	{PMIC_RG_VAUX18_NDIS_EN, PMIC_RG_VAUX18_NDIS_EN_ADDR,
	 PMIC_RG_VAUX18_NDIS_EN_MASK, PMIC_RG_VAUX18_NDIS_EN_SHIFT},
	{PMIC_RG_VCAMA_CAL, PMIC_RG_VCAMA_CAL_ADDR, PMIC_RG_VCAMA_CAL_MASK,
	 PMIC_RG_VCAMA_CAL_SHIFT},
	{PMIC_RG_VCAMA_VOSEL, PMIC_RG_VCAMA_VOSEL_ADDR, PMIC_RG_VCAMA_VOSEL_MASK,
	 PMIC_RG_VCAMA_VOSEL_SHIFT},
	{PMIC_RG_VCAMA_NDIS_EN, PMIC_RG_VCAMA_NDIS_EN_ADDR,
	 PMIC_RG_VCAMA_NDIS_EN_MASK, PMIC_RG_VCAMA_NDIS_EN_SHIFT},
	{PMIC_RG_ALDO_RSV_H, PMIC_RG_ALDO_RSV_H_ADDR, PMIC_RG_ALDO_RSV_H_MASK,
	 PMIC_RG_ALDO_RSV_H_SHIFT},
	{PMIC_RG_ALDO_RSV_L, PMIC_RG_ALDO_RSV_L_ADDR, PMIC_RG_ALDO_RSV_L_MASK,
	 PMIC_RG_ALDO_RSV_L_SHIFT},
	{PMIC_RG_VXO22_CAL, PMIC_RG_VXO22_CAL_ADDR, PMIC_RG_VXO22_CAL_MASK,
	 PMIC_RG_VXO22_CAL_SHIFT},
	{PMIC_RG_VXO22_VOSEL, PMIC_RG_VXO22_VOSEL_ADDR, PMIC_RG_VXO22_VOSEL_MASK,
	 PMIC_RG_VXO22_VOSEL_SHIFT},
	{PMIC_RG_VXO22_NDIS_EN, PMIC_RG_VXO22_NDIS_EN_ADDR,
	 PMIC_RG_VXO22_NDIS_EN_MASK, PMIC_RG_VXO22_NDIS_EN_SHIFT},
	{PMIC_RG_VTCXO24_CAL, PMIC_RG_VTCXO24_CAL_ADDR, PMIC_RG_VTCXO24_CAL_MASK,
	 PMIC_RG_VTCXO24_CAL_SHIFT},
	{PMIC_RG_VTCXO24_VOSEL, PMIC_RG_VTCXO24_VOSEL_ADDR,
	 PMIC_RG_VTCXO24_VOSEL_MASK, PMIC_RG_VTCXO24_VOSEL_SHIFT},
	{PMIC_RG_VTCXO24_NDIS_EN, PMIC_RG_VTCXO24_NDIS_EN_ADDR,
	 PMIC_RG_VTCXO24_NDIS_EN_MASK, PMIC_RG_VTCXO24_NDIS_EN_SHIFT},
	{PMIC_RG_VSIM1_CAL, PMIC_RG_VSIM1_CAL_ADDR, PMIC_RG_VSIM1_CAL_MASK,
	 PMIC_RG_VSIM1_CAL_SHIFT},
	{PMIC_RG_VSIM1_VOSEL, PMIC_RG_VSIM1_VOSEL_ADDR, PMIC_RG_VSIM1_VOSEL_MASK,
	 PMIC_RG_VSIM1_VOSEL_SHIFT},
	{PMIC_RG_VSIM1_NDIS_EN, PMIC_RG_VSIM1_NDIS_EN_ADDR,
	 PMIC_RG_VSIM1_NDIS_EN_MASK, PMIC_RG_VSIM1_NDIS_EN_SHIFT},
	{PMIC_RG_VSIM2_CAL, PMIC_RG_VSIM2_CAL_ADDR, PMIC_RG_VSIM2_CAL_MASK,
	 PMIC_RG_VSIM2_CAL_SHIFT},
	{PMIC_RG_VSIM2_VOSEL, PMIC_RG_VSIM2_VOSEL_ADDR, PMIC_RG_VSIM2_VOSEL_MASK,
	 PMIC_RG_VSIM2_VOSEL_SHIFT},
	{PMIC_RG_VSIM2_NDIS_EN, PMIC_RG_VSIM2_NDIS_EN_ADDR,
	 PMIC_RG_VSIM2_NDIS_EN_MASK, PMIC_RG_VSIM2_NDIS_EN_SHIFT},
	{PMIC_RG_VCN33_CAL, PMIC_RG_VCN33_CAL_ADDR, PMIC_RG_VCN33_CAL_MASK,
	 PMIC_RG_VCN33_CAL_SHIFT},
	{PMIC_RG_VCN33_VOSEL, PMIC_RG_VCN33_VOSEL_ADDR, PMIC_RG_VCN33_VOSEL_MASK,
	 PMIC_RG_VCN33_VOSEL_SHIFT},
	{PMIC_RG_VCN33_NDIS_EN, PMIC_RG_VCN33_NDIS_EN_ADDR,
	 PMIC_RG_VCN33_NDIS_EN_MASK, PMIC_RG_VCN33_NDIS_EN_SHIFT},
	{PMIC_RG_VUSB33_CAL, PMIC_RG_VUSB33_CAL_ADDR, PMIC_RG_VUSB33_CAL_MASK,
	 PMIC_RG_VUSB33_CAL_SHIFT},
	{PMIC_RG_VUSB33_NDIS_EN, PMIC_RG_VUSB33_NDIS_EN_ADDR,
	 PMIC_RG_VUSB33_NDIS_EN_MASK, PMIC_RG_VUSB33_NDIS_EN_SHIFT},
	{PMIC_RG_VMCH_CAL, PMIC_RG_VMCH_CAL_ADDR, PMIC_RG_VMCH_CAL_MASK,
	 PMIC_RG_VMCH_CAL_SHIFT},
	{PMIC_RG_VMCH_VOSEL, PMIC_RG_VMCH_VOSEL_ADDR, PMIC_RG_VMCH_VOSEL_MASK,
	 PMIC_RG_VMCH_VOSEL_SHIFT},
	{PMIC_RG_VMCH_NDIS_EN, PMIC_RG_VMCH_NDIS_EN_ADDR, PMIC_RG_VMCH_NDIS_EN_MASK,
	 PMIC_RG_VMCH_NDIS_EN_SHIFT},
	{PMIC_RG_VMCH_OC_TRIM, PMIC_RG_VMCH_OC_TRIM_ADDR, PMIC_RG_VMCH_OC_TRIM_MASK,
	 PMIC_RG_VMCH_OC_TRIM_SHIFT},
	{PMIC_RG_VMCH_DUMMY_LOAD, PMIC_RG_VMCH_DUMMY_LOAD_ADDR,
	 PMIC_RG_VMCH_DUMMY_LOAD_MASK, PMIC_RG_VMCH_DUMMY_LOAD_SHIFT},
	{PMIC_RG_VMCH_DL_EN, PMIC_RG_VMCH_DL_EN_ADDR, PMIC_RG_VMCH_DL_EN_MASK,
	 PMIC_RG_VMCH_DL_EN_SHIFT},
	{PMIC_RG_VMCH_CL_EN, PMIC_RG_VMCH_CL_EN_ADDR, PMIC_RG_VMCH_CL_EN_MASK,
	 PMIC_RG_VMCH_CL_EN_SHIFT},
	{PMIC_RG_VMCH_STB_SEL, PMIC_RG_VMCH_STB_SEL_ADDR, PMIC_RG_VMCH_STB_SEL_MASK,
	 PMIC_RG_VMCH_STB_SEL_SHIFT},
	{PMIC_RG_VEMC33_CAL, PMIC_RG_VEMC33_CAL_ADDR, PMIC_RG_VEMC33_CAL_MASK,
	 PMIC_RG_VEMC33_CAL_SHIFT},
	{PMIC_RG_VEMC33_VOSEL, PMIC_RG_VEMC33_VOSEL_ADDR, PMIC_RG_VEMC33_VOSEL_MASK,
	 PMIC_RG_VEMC33_VOSEL_SHIFT},
	{PMIC_RG_VEMC33_NDIS_EN, PMIC_RG_VEMC33_NDIS_EN_ADDR,
	 PMIC_RG_VEMC33_NDIS_EN_MASK, PMIC_RG_VEMC33_NDIS_EN_SHIFT},
	{PMIC_RG_VEMC33_OC_TRIM, PMIC_RG_VEMC33_OC_TRIM_ADDR,
	 PMIC_RG_VEMC33_OC_TRIM_MASK, PMIC_RG_VEMC33_OC_TRIM_SHIFT},
	{PMIC_RG_VEMC33_DUMMY_LOAD, PMIC_RG_VEMC33_DUMMY_LOAD_ADDR,
	 PMIC_RG_VEMC33_DUMMY_LOAD_MASK, PMIC_RG_VEMC33_DUMMY_LOAD_SHIFT},
	{PMIC_RG_VEMC33_DL_EN, PMIC_RG_VEMC33_DL_EN_ADDR, PMIC_RG_VEMC33_DL_EN_MASK,
	 PMIC_RG_VEMC33_DL_EN_SHIFT},
	{PMIC_RG_VEMC33_CL_EN, PMIC_RG_VEMC33_CL_EN_ADDR, PMIC_RG_VEMC33_CL_EN_MASK,
	 PMIC_RG_VEMC33_CL_EN_SHIFT},
	{PMIC_RG_VEMC33_STB_SEL, PMIC_RG_VEMC33_STB_SEL_ADDR,
	 PMIC_RG_VEMC33_STB_SEL_MASK, PMIC_RG_VEMC33_STB_SEL_SHIFT},
	{PMIC_RG_VIO28_CAL, PMIC_RG_VIO28_CAL_ADDR, PMIC_RG_VIO28_CAL_MASK,
	 PMIC_RG_VIO28_CAL_SHIFT},
	{PMIC_RG_VIO28_NDIS_EN, PMIC_RG_VIO28_NDIS_EN_ADDR,
	 PMIC_RG_VIO28_NDIS_EN_MASK, PMIC_RG_VIO28_NDIS_EN_SHIFT},
	{PMIC_RG_VIBR_CAL, PMIC_RG_VIBR_CAL_ADDR, PMIC_RG_VIBR_CAL_MASK,
	 PMIC_RG_VIBR_CAL_SHIFT},
	{PMIC_RG_VIBR_VOSEL, PMIC_RG_VIBR_VOSEL_ADDR, PMIC_RG_VIBR_VOSEL_MASK,
	 PMIC_RG_VIBR_VOSEL_SHIFT},
	{PMIC_RG_VIBR_NDIS_EN, PMIC_RG_VIBR_NDIS_EN_ADDR, PMIC_RG_VIBR_NDIS_EN_MASK,
	 PMIC_RG_VIBR_NDIS_EN_SHIFT},
	{PMIC_RG_VLDO28_CAL, PMIC_RG_VLDO28_CAL_ADDR, PMIC_RG_VLDO28_CAL_MASK,
	 PMIC_RG_VLDO28_CAL_SHIFT},
	{PMIC_RG_VLDO28_VOSEL, PMIC_RG_VLDO28_VOSEL_ADDR, PMIC_RG_VLDO28_VOSEL_MASK,
	 PMIC_RG_VLDO28_VOSEL_SHIFT},
	{PMIC_RG_VLDO28_NDIS_EN, PMIC_RG_VLDO28_NDIS_EN_ADDR,
	 PMIC_RG_VLDO28_NDIS_EN_MASK, PMIC_RG_VLDO28_NDIS_EN_SHIFT},
	{PMIC_RG_VLDO28_DUMMY_LOAD, PMIC_RG_VLDO28_DUMMY_LOAD_ADDR,
	 PMIC_RG_VLDO28_DUMMY_LOAD_MASK, PMIC_RG_VLDO28_DUMMY_LOAD_SHIFT},
	{PMIC_RG_VLDO28_DL_EN, PMIC_RG_VLDO28_DL_EN_ADDR, PMIC_RG_VLDO28_DL_EN_MASK,
	 PMIC_RG_VLDO28_DL_EN_SHIFT},
	{PMIC_RG_VLDO28_CL_EN, PMIC_RG_VLDO28_CL_EN_ADDR, PMIC_RG_VLDO28_CL_EN_MASK,
	 PMIC_RG_VLDO28_CL_EN_SHIFT},
	{PMIC_RG_VMC_CAL, PMIC_RG_VMC_CAL_ADDR, PMIC_RG_VMC_CAL_MASK,
	 PMIC_RG_VMC_CAL_SHIFT},
	{PMIC_RG_VMC_VOSEL, PMIC_RG_VMC_VOSEL_ADDR, PMIC_RG_VMC_VOSEL_MASK,
	 PMIC_RG_VMC_VOSEL_SHIFT},
	{PMIC_RG_VMC_NDIS_EN, PMIC_RG_VMC_NDIS_EN_ADDR, PMIC_RG_VMC_NDIS_EN_MASK,
	 PMIC_RG_VMC_NDIS_EN_SHIFT},
	{PMIC_RG_VMC_DUMMY_LOAD, PMIC_RG_VMC_DUMMY_LOAD_ADDR,
	 PMIC_RG_VMC_DUMMY_LOAD_MASK, PMIC_RG_VMC_DUMMY_LOAD_SHIFT},
	{PMIC_RG_VMC_DL_EN, PMIC_RG_VMC_DL_EN_ADDR, PMIC_RG_VMC_DL_EN_MASK,
	 PMIC_RG_VMC_DL_EN_SHIFT},
	{PMIC_RG_VMC_CL_EN, PMIC_RG_VMC_CL_EN_ADDR, PMIC_RG_VMC_CL_EN_MASK,
	 PMIC_RG_VMC_CL_EN_SHIFT},
	{PMIC_RG_DLDO_RSV_H, PMIC_RG_DLDO_RSV_H_ADDR, PMIC_RG_DLDO_RSV_H_MASK,
	 PMIC_RG_DLDO_RSV_H_SHIFT},
	{PMIC_RG_DLDO_RSV_L, PMIC_RG_DLDO_RSV_L_ADDR, PMIC_RG_DLDO_RSV_L_MASK,
	 PMIC_RG_DLDO_RSV_L_SHIFT},
	{PMIC_RG_VCAMD_CAL, PMIC_RG_VCAMD_CAL_ADDR, PMIC_RG_VCAMD_CAL_MASK,
	 PMIC_RG_VCAMD_CAL_SHIFT},
	{PMIC_RG_VCAMD_VOSEL, PMIC_RG_VCAMD_VOSEL_ADDR, PMIC_RG_VCAMD_VOSEL_MASK,
	 PMIC_RG_VCAMD_VOSEL_SHIFT},
	{PMIC_RG_VCAMD_NDIS_EN, PMIC_RG_VCAMD_NDIS_EN_ADDR,
	 PMIC_RG_VCAMD_NDIS_EN_MASK, PMIC_RG_VCAMD_NDIS_EN_SHIFT},
	{PMIC_RG_VRF18_CAL, PMIC_RG_VRF18_CAL_ADDR, PMIC_RG_VRF18_CAL_MASK,
	 PMIC_RG_VRF18_CAL_SHIFT},
	{PMIC_RG_VRF18_NDIS_EN, PMIC_RG_VRF18_NDIS_EN_ADDR,
	 PMIC_RG_VRF18_NDIS_EN_MASK, PMIC_RG_VRF18_NDIS_EN_SHIFT},
	{PMIC_RG_VRF12_CAL, PMIC_RG_VRF12_CAL_ADDR, PMIC_RG_VRF12_CAL_MASK,
	 PMIC_RG_VRF12_CAL_SHIFT},
	{PMIC_RG_VRF12_VOSEL, PMIC_RG_VRF12_VOSEL_ADDR, PMIC_RG_VRF12_VOSEL_MASK,
	 PMIC_RG_VRF12_VOSEL_SHIFT},
	{PMIC_RG_VRF12_NDIS_EN, PMIC_RG_VRF12_NDIS_EN_ADDR,
	 PMIC_RG_VRF12_NDIS_EN_MASK, PMIC_RG_VRF12_NDIS_EN_SHIFT},
	{PMIC_RG_VRF12_STB_SEL, PMIC_RG_VRF12_STB_SEL_ADDR,
	 PMIC_RG_VRF12_STB_SEL_MASK, PMIC_RG_VRF12_STB_SEL_SHIFT},
	{PMIC_RG_VRF12_DUMMY_LOAD, PMIC_RG_VRF12_DUMMY_LOAD_ADDR,
	 PMIC_RG_VRF12_DUMMY_LOAD_MASK, PMIC_RG_VRF12_DUMMY_LOAD_SHIFT},
	{PMIC_RG_VRF12_DL_EN, PMIC_RG_VRF12_DL_EN_ADDR, PMIC_RG_VRF12_DL_EN_MASK,
	 PMIC_RG_VRF12_DL_EN_SHIFT},
	{PMIC_RG_VRF12_CL_EN, PMIC_RG_VRF12_CL_EN_ADDR, PMIC_RG_VRF12_CL_EN_MASK,
	 PMIC_RG_VRF12_CL_EN_SHIFT},
	{PMIC_RG_VIO18_CAL, PMIC_RG_VIO18_CAL_ADDR, PMIC_RG_VIO18_CAL_MASK,
	 PMIC_RG_VIO18_CAL_SHIFT},
	{PMIC_RG_VIO18_NDIS_EN, PMIC_RG_VIO18_NDIS_EN_ADDR,
	 PMIC_RG_VIO18_NDIS_EN_MASK, PMIC_RG_VIO18_NDIS_EN_SHIFT},
	{PMIC_RG_VDRAM_CAL, PMIC_RG_VDRAM_CAL_ADDR, PMIC_RG_VDRAM_CAL_MASK,
	 PMIC_RG_VDRAM_CAL_SHIFT},
	{PMIC_RG_VDRAM_VOSEL, PMIC_RG_VDRAM_VOSEL_ADDR, PMIC_RG_VDRAM_VOSEL_MASK,
	 PMIC_RG_VDRAM_VOSEL_SHIFT},
	{PMIC_RG_VDRAM_NDIS_EN, PMIC_RG_VDRAM_NDIS_EN_ADDR,
	 PMIC_RG_VDRAM_NDIS_EN_MASK, PMIC_RG_VDRAM_NDIS_EN_SHIFT},
	{PMIC_RG_VDRAM_PCUR_CAL, PMIC_RG_VDRAM_PCUR_CAL_ADDR,
	 PMIC_RG_VDRAM_PCUR_CAL_MASK, PMIC_RG_VDRAM_PCUR_CAL_SHIFT},
	{PMIC_RG_VDRAM_DL_EN, PMIC_RG_VDRAM_DL_EN_ADDR, PMIC_RG_VDRAM_DL_EN_MASK,
	 PMIC_RG_VDRAM_DL_EN_SHIFT},
	{PMIC_RG_VDRAM_CL_EN, PMIC_RG_VDRAM_CL_EN_ADDR, PMIC_RG_VDRAM_CL_EN_MASK,
	 PMIC_RG_VDRAM_CL_EN_SHIFT},
	{PMIC_RG_VCAMIO_CAL, PMIC_RG_VCAMIO_CAL_ADDR, PMIC_RG_VCAMIO_CAL_MASK,
	 PMIC_RG_VCAMIO_CAL_SHIFT},
	{PMIC_RG_VCAMIO_VOSEL, PMIC_RG_VCAMIO_VOSEL_ADDR, PMIC_RG_VCAMIO_VOSEL_MASK,
	 PMIC_RG_VCAMIO_VOSEL_SHIFT},
	{PMIC_RG_VCAMIO_NDIS_EN, PMIC_RG_VCAMIO_NDIS_EN_ADDR,
	 PMIC_RG_VCAMIO_NDIS_EN_MASK, PMIC_RG_VCAMIO_NDIS_EN_SHIFT},
	{PMIC_RG_VCN18_CAL, PMIC_RG_VCN18_CAL_ADDR, PMIC_RG_VCN18_CAL_MASK,
	 PMIC_RG_VCN18_CAL_SHIFT},
	{PMIC_RG_VCN18_NDIS_EN, PMIC_RG_VCN18_NDIS_EN_ADDR,
	 PMIC_RG_VCN18_NDIS_EN_MASK, PMIC_RG_VCN18_NDIS_EN_SHIFT},
	{PMIC_RG_VSRAM_PROC_VOSEL, PMIC_RG_VSRAM_PROC_VOSEL_ADDR,
	 PMIC_RG_VSRAM_PROC_VOSEL_MASK, PMIC_RG_VSRAM_PROC_VOSEL_SHIFT},
	{PMIC_RG_VSRAM_PROC_NDIS_PLCUR, PMIC_RG_VSRAM_PROC_NDIS_PLCUR_ADDR,
	 PMIC_RG_VSRAM_PROC_NDIS_PLCUR_MASK, PMIC_RG_VSRAM_PROC_NDIS_PLCUR_SHIFT},
	{PMIC_RG_VSRAM_PROC_NDIS_EN, PMIC_RG_VSRAM_PROC_NDIS_EN_ADDR,
	 PMIC_RG_VSRAM_PROC_NDIS_EN_MASK, PMIC_RG_VSRAM_PROC_NDIS_EN_SHIFT},
	{PMIC_RG_VSRAM_PROC_PLCUR_EN, PMIC_RG_VSRAM_PROC_PLCUR_EN_ADDR,
	 PMIC_RG_VSRAM_PROC_PLCUR_EN_MASK, PMIC_RG_VSRAM_PROC_PLCUR_EN_SHIFT},
	{PMIC_RG_SLDO_RSV_H, PMIC_RG_SLDO_RSV_H_ADDR, PMIC_RG_SLDO_RSV_H_MASK,
	 PMIC_RG_SLDO_RSV_H_SHIFT},
	{PMIC_RG_SLDO_RSV_L, PMIC_RG_SLDO_RSV_L_ADDR, PMIC_RG_SLDO_RSV_L_MASK,
	 PMIC_RG_SLDO_RSV_L_SHIFT},
	{PMIC_RG_OTP_PA, PMIC_RG_OTP_PA_ADDR, PMIC_RG_OTP_PA_MASK,
	 PMIC_RG_OTP_PA_SHIFT},
	{PMIC_RG_OTP_PDIN, PMIC_RG_OTP_PDIN_ADDR, PMIC_RG_OTP_PDIN_MASK,
	 PMIC_RG_OTP_PDIN_SHIFT},
	{PMIC_RG_OTP_PTM, PMIC_RG_OTP_PTM_ADDR, PMIC_RG_OTP_PTM_MASK,
	 PMIC_RG_OTP_PTM_SHIFT},
	{PMIC_RG_OTP_PWE, PMIC_RG_OTP_PWE_ADDR, PMIC_RG_OTP_PWE_MASK,
	 PMIC_RG_OTP_PWE_SHIFT},
	{PMIC_RG_OTP_PPROG, PMIC_RG_OTP_PPROG_ADDR, PMIC_RG_OTP_PPROG_MASK,
	 PMIC_RG_OTP_PPROG_SHIFT},
	{PMIC_RG_OTP_PWE_SRC, PMIC_RG_OTP_PWE_SRC_ADDR, PMIC_RG_OTP_PWE_SRC_MASK,
	 PMIC_RG_OTP_PWE_SRC_SHIFT},
	{PMIC_RG_OTP_PROG_PKEY, PMIC_RG_OTP_PROG_PKEY_ADDR,
	 PMIC_RG_OTP_PROG_PKEY_MASK, PMIC_RG_OTP_PROG_PKEY_SHIFT},
	{PMIC_RG_OTP_RD_PKEY, PMIC_RG_OTP_RD_PKEY_ADDR, PMIC_RG_OTP_RD_PKEY_MASK,
	 PMIC_RG_OTP_RD_PKEY_SHIFT},
	{PMIC_RG_OTP_RD_TRIG, PMIC_RG_OTP_RD_TRIG_ADDR, PMIC_RG_OTP_RD_TRIG_MASK,
	 PMIC_RG_OTP_RD_TRIG_SHIFT},
	{PMIC_RG_RD_RDY_BYPASS, PMIC_RG_RD_RDY_BYPASS_ADDR,
	 PMIC_RG_RD_RDY_BYPASS_MASK, PMIC_RG_RD_RDY_BYPASS_SHIFT},
	{PMIC_RG_SKIP_OTP_OUT, PMIC_RG_SKIP_OTP_OUT_ADDR, PMIC_RG_SKIP_OTP_OUT_MASK,
	 PMIC_RG_SKIP_OTP_OUT_SHIFT},
	{PMIC_RG_OTP_RD_SW, PMIC_RG_OTP_RD_SW_ADDR, PMIC_RG_OTP_RD_SW_MASK,
	 PMIC_RG_OTP_RD_SW_SHIFT},
	{PMIC_RG_OTP_DOUT_SW, PMIC_RG_OTP_DOUT_SW_ADDR, PMIC_RG_OTP_DOUT_SW_MASK,
	 PMIC_RG_OTP_DOUT_SW_SHIFT},
	{PMIC_RG_OTP_RD_BUSY, PMIC_RG_OTP_RD_BUSY_ADDR, PMIC_RG_OTP_RD_BUSY_MASK,
	 PMIC_RG_OTP_RD_BUSY_SHIFT},
	{PMIC_RG_OTP_RD_ACK, PMIC_RG_OTP_RD_ACK_ADDR, PMIC_RG_OTP_RD_ACK_MASK,
	 PMIC_RG_OTP_RD_ACK_SHIFT},
	{PMIC_RG_OTP_PA_SW, PMIC_RG_OTP_PA_SW_ADDR, PMIC_RG_OTP_PA_SW_MASK,
	 PMIC_RG_OTP_PA_SW_SHIFT},
	{PMIC_RG_OTP_DOUT_0_15, PMIC_RG_OTP_DOUT_0_15_ADDR,
	 PMIC_RG_OTP_DOUT_0_15_MASK, PMIC_RG_OTP_DOUT_0_15_SHIFT},
	{PMIC_RG_OTP_DOUT_16_31, PMIC_RG_OTP_DOUT_16_31_ADDR,
	 PMIC_RG_OTP_DOUT_16_31_MASK, PMIC_RG_OTP_DOUT_16_31_SHIFT},
	{PMIC_RG_OTP_DOUT_32_47, PMIC_RG_OTP_DOUT_32_47_ADDR,
	 PMIC_RG_OTP_DOUT_32_47_MASK, PMIC_RG_OTP_DOUT_32_47_SHIFT},
	{PMIC_RG_OTP_DOUT_48_63, PMIC_RG_OTP_DOUT_48_63_ADDR,
	 PMIC_RG_OTP_DOUT_48_63_MASK, PMIC_RG_OTP_DOUT_48_63_SHIFT},
	{PMIC_RG_OTP_DOUT_64_79, PMIC_RG_OTP_DOUT_64_79_ADDR,
	 PMIC_RG_OTP_DOUT_64_79_MASK, PMIC_RG_OTP_DOUT_64_79_SHIFT},
	{PMIC_RG_OTP_DOUT_80_95, PMIC_RG_OTP_DOUT_80_95_ADDR,
	 PMIC_RG_OTP_DOUT_80_95_MASK, PMIC_RG_OTP_DOUT_80_95_SHIFT},
	{PMIC_RG_OTP_DOUT_96_111, PMIC_RG_OTP_DOUT_96_111_ADDR,
	 PMIC_RG_OTP_DOUT_96_111_MASK, PMIC_RG_OTP_DOUT_96_111_SHIFT},
	{PMIC_RG_OTP_DOUT_112_127, PMIC_RG_OTP_DOUT_112_127_ADDR,
	 PMIC_RG_OTP_DOUT_112_127_MASK, PMIC_RG_OTP_DOUT_112_127_SHIFT},
	{PMIC_RG_OTP_DOUT_128_143, PMIC_RG_OTP_DOUT_128_143_ADDR,
	 PMIC_RG_OTP_DOUT_128_143_MASK, PMIC_RG_OTP_DOUT_128_143_SHIFT},
	{PMIC_RG_OTP_DOUT_144_159, PMIC_RG_OTP_DOUT_144_159_ADDR,
	 PMIC_RG_OTP_DOUT_144_159_MASK, PMIC_RG_OTP_DOUT_144_159_SHIFT},
	{PMIC_RG_OTP_DOUT_160_175, PMIC_RG_OTP_DOUT_160_175_ADDR,
	 PMIC_RG_OTP_DOUT_160_175_MASK, PMIC_RG_OTP_DOUT_160_175_SHIFT},
	{PMIC_RG_OTP_DOUT_176_191, PMIC_RG_OTP_DOUT_176_191_ADDR,
	 PMIC_RG_OTP_DOUT_176_191_MASK, PMIC_RG_OTP_DOUT_176_191_SHIFT},
	{PMIC_RG_OTP_DOUT_192_207, PMIC_RG_OTP_DOUT_192_207_ADDR,
	 PMIC_RG_OTP_DOUT_192_207_MASK, PMIC_RG_OTP_DOUT_192_207_SHIFT},
	{PMIC_RG_OTP_DOUT_208_223, PMIC_RG_OTP_DOUT_208_223_ADDR,
	 PMIC_RG_OTP_DOUT_208_223_MASK, PMIC_RG_OTP_DOUT_208_223_SHIFT},
	{PMIC_RG_OTP_DOUT_224_239, PMIC_RG_OTP_DOUT_224_239_ADDR,
	 PMIC_RG_OTP_DOUT_224_239_MASK, PMIC_RG_OTP_DOUT_224_239_SHIFT},
	{PMIC_RG_OTP_DOUT_240_255, PMIC_RG_OTP_DOUT_240_255_ADDR,
	 PMIC_RG_OTP_DOUT_240_255_MASK, PMIC_RG_OTP_DOUT_240_255_SHIFT},
	{PMIC_RG_OTP_DOUT_256_271, PMIC_RG_OTP_DOUT_256_271_ADDR,
	 PMIC_RG_OTP_DOUT_256_271_MASK, PMIC_RG_OTP_DOUT_256_271_SHIFT},
	{PMIC_RG_OTP_DOUT_272_287, PMIC_RG_OTP_DOUT_272_287_ADDR,
	 PMIC_RG_OTP_DOUT_272_287_MASK, PMIC_RG_OTP_DOUT_272_287_SHIFT},
	{PMIC_RG_OTP_DOUT_288_303, PMIC_RG_OTP_DOUT_288_303_ADDR,
	 PMIC_RG_OTP_DOUT_288_303_MASK, PMIC_RG_OTP_DOUT_288_303_SHIFT},
	{PMIC_RG_OTP_DOUT_304_319, PMIC_RG_OTP_DOUT_304_319_ADDR,
	 PMIC_RG_OTP_DOUT_304_319_MASK, PMIC_RG_OTP_DOUT_304_319_SHIFT},
	{PMIC_RG_OTP_DOUT_320_335, PMIC_RG_OTP_DOUT_320_335_ADDR,
	 PMIC_RG_OTP_DOUT_320_335_MASK, PMIC_RG_OTP_DOUT_320_335_SHIFT},
	{PMIC_RG_OTP_DOUT_336_351, PMIC_RG_OTP_DOUT_336_351_ADDR,
	 PMIC_RG_OTP_DOUT_336_351_MASK, PMIC_RG_OTP_DOUT_336_351_SHIFT},
	{PMIC_RG_OTP_DOUT_352_367, PMIC_RG_OTP_DOUT_352_367_ADDR,
	 PMIC_RG_OTP_DOUT_352_367_MASK, PMIC_RG_OTP_DOUT_352_367_SHIFT},
	{PMIC_RG_OTP_DOUT_368_383, PMIC_RG_OTP_DOUT_368_383_ADDR,
	 PMIC_RG_OTP_DOUT_368_383_MASK, PMIC_RG_OTP_DOUT_368_383_SHIFT},
	{PMIC_RG_OTP_DOUT_384_399, PMIC_RG_OTP_DOUT_384_399_ADDR,
	 PMIC_RG_OTP_DOUT_384_399_MASK, PMIC_RG_OTP_DOUT_384_399_SHIFT},
	{PMIC_RG_OTP_DOUT_400_415, PMIC_RG_OTP_DOUT_400_415_ADDR,
	 PMIC_RG_OTP_DOUT_400_415_MASK, PMIC_RG_OTP_DOUT_400_415_SHIFT},
	{PMIC_RG_OTP_DOUT_416_431, PMIC_RG_OTP_DOUT_416_431_ADDR,
	 PMIC_RG_OTP_DOUT_416_431_MASK, PMIC_RG_OTP_DOUT_416_431_SHIFT},
	{PMIC_RG_OTP_DOUT_432_447, PMIC_RG_OTP_DOUT_432_447_ADDR,
	 PMIC_RG_OTP_DOUT_432_447_MASK, PMIC_RG_OTP_DOUT_432_447_SHIFT},
	{PMIC_RG_OTP_DOUT_448_463, PMIC_RG_OTP_DOUT_448_463_ADDR,
	 PMIC_RG_OTP_DOUT_448_463_MASK, PMIC_RG_OTP_DOUT_448_463_SHIFT},
	{PMIC_RG_OTP_DOUT_464_479, PMIC_RG_OTP_DOUT_464_479_ADDR,
	 PMIC_RG_OTP_DOUT_464_479_MASK, PMIC_RG_OTP_DOUT_464_479_SHIFT},
	{PMIC_RG_OTP_DOUT_480_495, PMIC_RG_OTP_DOUT_480_495_ADDR,
	 PMIC_RG_OTP_DOUT_480_495_MASK, PMIC_RG_OTP_DOUT_480_495_SHIFT},
	{PMIC_RG_OTP_DOUT_496_511, PMIC_RG_OTP_DOUT_496_511_ADDR,
	 PMIC_RG_OTP_DOUT_496_511_MASK, PMIC_RG_OTP_DOUT_496_511_SHIFT},
	{PMIC_RG_OTP_VAL_0_15, PMIC_RG_OTP_VAL_0_15_ADDR, PMIC_RG_OTP_VAL_0_15_MASK,
	 PMIC_RG_OTP_VAL_0_15_SHIFT},
	{PMIC_RG_OTP_VAL_16_31, PMIC_RG_OTP_VAL_16_31_ADDR,
	 PMIC_RG_OTP_VAL_16_31_MASK, PMIC_RG_OTP_VAL_16_31_SHIFT},
	{PMIC_RG_OTP_VAL_32_47, PMIC_RG_OTP_VAL_32_47_ADDR,
	 PMIC_RG_OTP_VAL_32_47_MASK, PMIC_RG_OTP_VAL_32_47_SHIFT},
	{PMIC_RG_OTP_VAL_48_63, PMIC_RG_OTP_VAL_48_63_ADDR,
	 PMIC_RG_OTP_VAL_48_63_MASK, PMIC_RG_OTP_VAL_48_63_SHIFT},
	{PMIC_RG_OTP_VAL_64_79, PMIC_RG_OTP_VAL_64_79_ADDR,
	 PMIC_RG_OTP_VAL_64_79_MASK, PMIC_RG_OTP_VAL_64_79_SHIFT},
	{PMIC_RG_OTP_VAL_80_95, PMIC_RG_OTP_VAL_80_95_ADDR,
	 PMIC_RG_OTP_VAL_80_95_MASK, PMIC_RG_OTP_VAL_80_95_SHIFT},
	{PMIC_RG_OTP_VAL_96_111, PMIC_RG_OTP_VAL_96_111_ADDR,
	 PMIC_RG_OTP_VAL_96_111_MASK, PMIC_RG_OTP_VAL_96_111_SHIFT},
	{PMIC_RG_OTP_VAL_112_127, PMIC_RG_OTP_VAL_112_127_ADDR,
	 PMIC_RG_OTP_VAL_112_127_MASK, PMIC_RG_OTP_VAL_112_127_SHIFT},
	{PMIC_RG_OTP_VAL_128_143, PMIC_RG_OTP_VAL_128_143_ADDR,
	 PMIC_RG_OTP_VAL_128_143_MASK, PMIC_RG_OTP_VAL_128_143_SHIFT},
	{PMIC_RG_OTP_VAL_144_159, PMIC_RG_OTP_VAL_144_159_ADDR,
	 PMIC_RG_OTP_VAL_144_159_MASK, PMIC_RG_OTP_VAL_144_159_SHIFT},
	{PMIC_RG_OTP_VAL_160_175, PMIC_RG_OTP_VAL_160_175_ADDR,
	 PMIC_RG_OTP_VAL_160_175_MASK, PMIC_RG_OTP_VAL_160_175_SHIFT},
	{PMIC_RG_OTP_VAL_176_191, PMIC_RG_OTP_VAL_176_191_ADDR,
	 PMIC_RG_OTP_VAL_176_191_MASK, PMIC_RG_OTP_VAL_176_191_SHIFT},
	{PMIC_RG_OTP_VAL_192_207, PMIC_RG_OTP_VAL_192_207_ADDR,
	 PMIC_RG_OTP_VAL_192_207_MASK, PMIC_RG_OTP_VAL_192_207_SHIFT},
	{PMIC_RG_OTP_VAL_208_223, PMIC_RG_OTP_VAL_208_223_ADDR,
	 PMIC_RG_OTP_VAL_208_223_MASK, PMIC_RG_OTP_VAL_208_223_SHIFT},
	{PMIC_RG_OTP_VAL_224_239, PMIC_RG_OTP_VAL_224_239_ADDR,
	 PMIC_RG_OTP_VAL_224_239_MASK, PMIC_RG_OTP_VAL_224_239_SHIFT},
	{PMIC_RG_OTP_VAL_240_255, PMIC_RG_OTP_VAL_240_255_ADDR,
	 PMIC_RG_OTP_VAL_240_255_MASK, PMIC_RG_OTP_VAL_240_255_SHIFT},
	{PMIC_RG_OTP_VAL_256_271, PMIC_RG_OTP_VAL_256_271_ADDR,
	 PMIC_RG_OTP_VAL_256_271_MASK, PMIC_RG_OTP_VAL_256_271_SHIFT},
	{PMIC_RG_OTP_VAL_272_287, PMIC_RG_OTP_VAL_272_287_ADDR,
	 PMIC_RG_OTP_VAL_272_287_MASK, PMIC_RG_OTP_VAL_272_287_SHIFT},
	{PMIC_RG_OTP_VAL_288_303, PMIC_RG_OTP_VAL_288_303_ADDR,
	 PMIC_RG_OTP_VAL_288_303_MASK, PMIC_RG_OTP_VAL_288_303_SHIFT},
	{PMIC_RG_OTP_VAL_304_319, PMIC_RG_OTP_VAL_304_319_ADDR,
	 PMIC_RG_OTP_VAL_304_319_MASK, PMIC_RG_OTP_VAL_304_319_SHIFT},
	{PMIC_RG_OTP_VAL_320_335, PMIC_RG_OTP_VAL_320_335_ADDR,
	 PMIC_RG_OTP_VAL_320_335_MASK, PMIC_RG_OTP_VAL_320_335_SHIFT},
	{PMIC_RG_OTP_VAL_336_351, PMIC_RG_OTP_VAL_336_351_ADDR,
	 PMIC_RG_OTP_VAL_336_351_MASK, PMIC_RG_OTP_VAL_336_351_SHIFT},
	{PMIC_RG_OTP_VAL_352_367, PMIC_RG_OTP_VAL_352_367_ADDR,
	 PMIC_RG_OTP_VAL_352_367_MASK, PMIC_RG_OTP_VAL_352_367_SHIFT},
	{PMIC_RG_OTP_VAL_368_383, PMIC_RG_OTP_VAL_368_383_ADDR,
	 PMIC_RG_OTP_VAL_368_383_MASK, PMIC_RG_OTP_VAL_368_383_SHIFT},
	{PMIC_RG_OTP_VAL_384_399, PMIC_RG_OTP_VAL_384_399_ADDR,
	 PMIC_RG_OTP_VAL_384_399_MASK, PMIC_RG_OTP_VAL_384_399_SHIFT},
	{PMIC_RG_OTP_VAL_400_415, PMIC_RG_OTP_VAL_400_415_ADDR,
	 PMIC_RG_OTP_VAL_400_415_MASK, PMIC_RG_OTP_VAL_400_415_SHIFT},
	{PMIC_RG_OTP_VAL_416_431, PMIC_RG_OTP_VAL_416_431_ADDR,
	 PMIC_RG_OTP_VAL_416_431_MASK, PMIC_RG_OTP_VAL_416_431_SHIFT},
	{PMIC_RG_OTP_VAL_432_447, PMIC_RG_OTP_VAL_432_447_ADDR,
	 PMIC_RG_OTP_VAL_432_447_MASK, PMIC_RG_OTP_VAL_432_447_SHIFT},
	{PMIC_RG_OTP_VAL_448_463, PMIC_RG_OTP_VAL_448_463_ADDR,
	 PMIC_RG_OTP_VAL_448_463_MASK, PMIC_RG_OTP_VAL_448_463_SHIFT},
	{PMIC_RG_OTP_VAL_464_479, PMIC_RG_OTP_VAL_464_479_ADDR,
	 PMIC_RG_OTP_VAL_464_479_MASK, PMIC_RG_OTP_VAL_464_479_SHIFT},
	{PMIC_RG_OTP_VAL_480_495, PMIC_RG_OTP_VAL_480_495_ADDR,
	 PMIC_RG_OTP_VAL_480_495_MASK, PMIC_RG_OTP_VAL_480_495_SHIFT},
	{PMIC_RG_OTP_VAL_496_511, PMIC_RG_OTP_VAL_496_511_ADDR,
	 PMIC_RG_OTP_VAL_496_511_MASK, PMIC_RG_OTP_VAL_496_511_SHIFT},
	{PMIC_MIX_EOSC32_STP_LPDTB, PMIC_MIX_EOSC32_STP_LPDTB_ADDR,
	 PMIC_MIX_EOSC32_STP_LPDTB_MASK, PMIC_MIX_EOSC32_STP_LPDTB_SHIFT},
	{PMIC_MIX_EOSC32_STP_LPDEN, PMIC_MIX_EOSC32_STP_LPDEN_ADDR,
	 PMIC_MIX_EOSC32_STP_LPDEN_MASK, PMIC_MIX_EOSC32_STP_LPDEN_SHIFT},
	{PMIC_MIX_XOSC32_STP_PWDB, PMIC_MIX_XOSC32_STP_PWDB_ADDR,
	 PMIC_MIX_XOSC32_STP_PWDB_MASK, PMIC_MIX_XOSC32_STP_PWDB_SHIFT},
	{PMIC_MIX_XOSC32_STP_LPDTB, PMIC_MIX_XOSC32_STP_LPDTB_ADDR,
	 PMIC_MIX_XOSC32_STP_LPDTB_MASK, PMIC_MIX_XOSC32_STP_LPDTB_SHIFT},
	{PMIC_MIX_XOSC32_STP_LPDEN, PMIC_MIX_XOSC32_STP_LPDEN_ADDR,
	 PMIC_MIX_XOSC32_STP_LPDEN_MASK, PMIC_MIX_XOSC32_STP_LPDEN_SHIFT},
	{PMIC_MIX_XOSC32_STP_LPDRST, PMIC_MIX_XOSC32_STP_LPDRST_ADDR,
	 PMIC_MIX_XOSC32_STP_LPDRST_MASK, PMIC_MIX_XOSC32_STP_LPDRST_SHIFT},
	{PMIC_MIX_XOSC32_STP_CALI, PMIC_MIX_XOSC32_STP_CALI_ADDR,
	 PMIC_MIX_XOSC32_STP_CALI_MASK, PMIC_MIX_XOSC32_STP_CALI_SHIFT},
	{PMIC_STMP_MODE, PMIC_STMP_MODE_ADDR, PMIC_STMP_MODE_MASK,
	 PMIC_STMP_MODE_SHIFT},
	{PMIC_MIX_EOSC32_STP_CHOP_EN, PMIC_MIX_EOSC32_STP_CHOP_EN_ADDR,
	 PMIC_MIX_EOSC32_STP_CHOP_EN_MASK, PMIC_MIX_EOSC32_STP_CHOP_EN_SHIFT},
	{PMIC_MIX_DCXO_STP_LVSH_EN, PMIC_MIX_DCXO_STP_LVSH_EN_ADDR,
	 PMIC_MIX_DCXO_STP_LVSH_EN_MASK, PMIC_MIX_DCXO_STP_LVSH_EN_SHIFT},
	{PMIC_MIX_PMU_STP_DDLO_VRTC, PMIC_MIX_PMU_STP_DDLO_VRTC_ADDR,
	 PMIC_MIX_PMU_STP_DDLO_VRTC_MASK, PMIC_MIX_PMU_STP_DDLO_VRTC_SHIFT},
	{PMIC_MIX_PMU_STP_DDLO_VRTC_EN, PMIC_MIX_PMU_STP_DDLO_VRTC_EN_ADDR,
	 PMIC_MIX_PMU_STP_DDLO_VRTC_EN_MASK, PMIC_MIX_PMU_STP_DDLO_VRTC_EN_SHIFT},
	{PMIC_MIX_RTC_STP_XOSC32_ENB, PMIC_MIX_RTC_STP_XOSC32_ENB_ADDR,
	 PMIC_MIX_RTC_STP_XOSC32_ENB_MASK, PMIC_MIX_RTC_STP_XOSC32_ENB_SHIFT},
	{PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE, PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_ADDR,
	 PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_MASK,
	 PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_SHIFT},
	{PMIC_MIX_EOSC32_STP_RSV, PMIC_MIX_EOSC32_STP_RSV_ADDR,
	 PMIC_MIX_EOSC32_STP_RSV_MASK, PMIC_MIX_EOSC32_STP_RSV_SHIFT},
	{PMIC_MIX_EOSC32_VCT_EN, PMIC_MIX_EOSC32_VCT_EN_ADDR,
	 PMIC_MIX_EOSC32_VCT_EN_MASK, PMIC_MIX_EOSC32_VCT_EN_SHIFT},
	{PMIC_MIX_EOSC32_OPT, PMIC_MIX_EOSC32_OPT_ADDR, PMIC_MIX_EOSC32_OPT_MASK,
	 PMIC_MIX_EOSC32_OPT_SHIFT},
	{PMIC_MIX_DCXO_STP_LVSH_EN_INT, PMIC_MIX_DCXO_STP_LVSH_EN_INT_ADDR,
	 PMIC_MIX_DCXO_STP_LVSH_EN_INT_MASK, PMIC_MIX_DCXO_STP_LVSH_EN_INT_SHIFT},
	{PMIC_MIX_RTC_GPIO_COREDETB, PMIC_MIX_RTC_GPIO_COREDETB_ADDR,
	 PMIC_MIX_RTC_GPIO_COREDETB_MASK, PMIC_MIX_RTC_GPIO_COREDETB_SHIFT},
	{PMIC_MIX_RTC_GPIO_F32KOB, PMIC_MIX_RTC_GPIO_F32KOB_ADDR,
	 PMIC_MIX_RTC_GPIO_F32KOB_MASK, PMIC_MIX_RTC_GPIO_F32KOB_SHIFT},
	{PMIC_MIX_RTC_GPIO_GPO, PMIC_MIX_RTC_GPIO_GPO_ADDR,
	 PMIC_MIX_RTC_GPIO_GPO_MASK, PMIC_MIX_RTC_GPIO_GPO_SHIFT},
	{PMIC_MIX_RTC_GPIO_OE, PMIC_MIX_RTC_GPIO_OE_ADDR, PMIC_MIX_RTC_GPIO_OE_MASK,
	 PMIC_MIX_RTC_GPIO_OE_SHIFT},
	{PMIC_MIX_RTC_STP_DEBUG_OUT, PMIC_MIX_RTC_STP_DEBUG_OUT_ADDR,
	 PMIC_MIX_RTC_STP_DEBUG_OUT_MASK, PMIC_MIX_RTC_STP_DEBUG_OUT_SHIFT},
	{PMIC_MIX_RTC_STP_DEBUG_SEL, PMIC_MIX_RTC_STP_DEBUG_SEL_ADDR,
	 PMIC_MIX_RTC_STP_DEBUG_SEL_MASK, PMIC_MIX_RTC_STP_DEBUG_SEL_SHIFT},
	{PMIC_MIX_RTC_STP_K_EOSC32_EN, PMIC_MIX_RTC_STP_K_EOSC32_EN_ADDR,
	 PMIC_MIX_RTC_STP_K_EOSC32_EN_MASK, PMIC_MIX_RTC_STP_K_EOSC32_EN_SHIFT},
	{PMIC_MIX_RTC_STP_EMBCK_SEL, PMIC_MIX_RTC_STP_EMBCK_SEL_ADDR,
	 PMIC_MIX_RTC_STP_EMBCK_SEL_MASK, PMIC_MIX_RTC_STP_EMBCK_SEL_SHIFT},
	{PMIC_MIX_STP_BBWAKEUP, PMIC_MIX_STP_BBWAKEUP_ADDR,
	 PMIC_MIX_STP_BBWAKEUP_MASK, PMIC_MIX_STP_BBWAKEUP_SHIFT},
	{PMIC_MIX_STP_RTC_DDLO, PMIC_MIX_STP_RTC_DDLO_ADDR,
	 PMIC_MIX_STP_RTC_DDLO_MASK, PMIC_MIX_STP_RTC_DDLO_SHIFT},
	{PMIC_MIX_RTC_XOSC32_ENB, PMIC_MIX_RTC_XOSC32_ENB_ADDR,
	 PMIC_MIX_RTC_XOSC32_ENB_MASK, PMIC_MIX_RTC_XOSC32_ENB_SHIFT},
	{PMIC_MIX_EFUSE_XOSC32_ENB_OPT, PMIC_MIX_EFUSE_XOSC32_ENB_OPT_ADDR,
	 PMIC_MIX_EFUSE_XOSC32_ENB_OPT_MASK, PMIC_MIX_EFUSE_XOSC32_ENB_OPT_SHIFT},
	{PMIC_FG_ON, PMIC_FG_ON_ADDR, PMIC_FG_ON_MASK, PMIC_FG_ON_SHIFT},
	{PMIC_FG_CAL, PMIC_FG_CAL_ADDR, PMIC_FG_CAL_MASK, PMIC_FG_CAL_SHIFT},
	{PMIC_FG_AUTOCALRATE, PMIC_FG_AUTOCALRATE_ADDR, PMIC_FG_AUTOCALRATE_MASK,
	 PMIC_FG_AUTOCALRATE_SHIFT},
	{PMIC_FG_SW_CR, PMIC_FG_SW_CR_ADDR, PMIC_FG_SW_CR_MASK,
	 PMIC_FG_SW_CR_SHIFT},
	{PMIC_FG_SW_READ_PRE, PMIC_FG_SW_READ_PRE_ADDR, PMIC_FG_SW_READ_PRE_MASK,
	 PMIC_FG_SW_READ_PRE_SHIFT},
	{PMIC_FG_LATCHDATA_ST, PMIC_FG_LATCHDATA_ST_ADDR, PMIC_FG_LATCHDATA_ST_MASK,
	 PMIC_FG_LATCHDATA_ST_SHIFT},
	{PMIC_FG_SW_CLEAR, PMIC_FG_SW_CLEAR_ADDR, PMIC_FG_SW_CLEAR_MASK,
	 PMIC_FG_SW_CLEAR_SHIFT},
	{PMIC_FG_OFFSET_RST, PMIC_FG_OFFSET_RST_ADDR, PMIC_FG_OFFSET_RST_MASK,
	 PMIC_FG_OFFSET_RST_SHIFT},
	{PMIC_FG_TIME_RST, PMIC_FG_TIME_RST_ADDR, PMIC_FG_TIME_RST_MASK,
	 PMIC_FG_TIME_RST_SHIFT},
	{PMIC_FG_CHARGE_RST, PMIC_FG_CHARGE_RST_ADDR, PMIC_FG_CHARGE_RST_MASK,
	 PMIC_FG_CHARGE_RST_SHIFT},
	{PMIC_FG_SW_RSTCLR, PMIC_FG_SW_RSTCLR_ADDR, PMIC_FG_SW_RSTCLR_MASK,
	 PMIC_FG_SW_RSTCLR_SHIFT},
	{PMIC_FG_CAR_34_19, PMIC_FG_CAR_34_19_ADDR, PMIC_FG_CAR_34_19_MASK,
	 PMIC_FG_CAR_34_19_SHIFT},
	{PMIC_FG_CAR_18_03, PMIC_FG_CAR_18_03_ADDR, PMIC_FG_CAR_18_03_MASK,
	 PMIC_FG_CAR_18_03_SHIFT},
	{PMIC_FG_CAR_02_00, PMIC_FG_CAR_02_00_ADDR, PMIC_FG_CAR_02_00_MASK,
	 PMIC_FG_CAR_02_00_SHIFT},
	{PMIC_FG_NTER_32_17, PMIC_FG_NTER_32_17_ADDR, PMIC_FG_NTER_32_17_MASK,
	 PMIC_FG_NTER_32_17_SHIFT},
	{PMIC_FG_NTER_16_01, PMIC_FG_NTER_16_01_ADDR, PMIC_FG_NTER_16_01_MASK,
	 PMIC_FG_NTER_16_01_SHIFT},
	{PMIC_FG_NTER_00, PMIC_FG_NTER_00_ADDR, PMIC_FG_NTER_00_MASK,
	 PMIC_FG_NTER_00_SHIFT},
	{PMIC_FG_BLTR_31_16, PMIC_FG_BLTR_31_16_ADDR, PMIC_FG_BLTR_31_16_MASK,
	 PMIC_FG_BLTR_31_16_SHIFT},
	{PMIC_FG_BLTR_15_00, PMIC_FG_BLTR_15_00_ADDR, PMIC_FG_BLTR_15_00_MASK,
	 PMIC_FG_BLTR_15_00_SHIFT},
	{PMIC_FG_BFTR_31_16, PMIC_FG_BFTR_31_16_ADDR, PMIC_FG_BFTR_31_16_MASK,
	 PMIC_FG_BFTR_31_16_SHIFT},
	{PMIC_FG_BFTR_15_00, PMIC_FG_BFTR_15_00_ADDR, PMIC_FG_BFTR_15_00_MASK,
	 PMIC_FG_BFTR_15_00_SHIFT},
	{PMIC_FG_CURRENT_OUT, PMIC_FG_CURRENT_OUT_ADDR, PMIC_FG_CURRENT_OUT_MASK,
	 PMIC_FG_CURRENT_OUT_SHIFT},
	{PMIC_FG_ADJUST_OFFSET_VALUE, PMIC_FG_ADJUST_OFFSET_VALUE_ADDR,
	 PMIC_FG_ADJUST_OFFSET_VALUE_MASK, PMIC_FG_ADJUST_OFFSET_VALUE_SHIFT},
	{PMIC_FG_OFFSET, PMIC_FG_OFFSET_ADDR, PMIC_FG_OFFSET_MASK,
	 PMIC_FG_OFFSET_SHIFT},
	{PMIC_RG_FGANALOGTEST, PMIC_RG_FGANALOGTEST_ADDR, PMIC_RG_FGANALOGTEST_MASK,
	 PMIC_RG_FGANALOGTEST_SHIFT},
	{PMIC_RG_FGINTMODE, PMIC_RG_FGINTMODE_ADDR, PMIC_RG_FGINTMODE_MASK,
	 PMIC_RG_FGINTMODE_SHIFT},
	{PMIC_RG_SPARE, PMIC_RG_SPARE_ADDR, PMIC_RG_SPARE_MASK,
	 PMIC_RG_SPARE_SHIFT},
	{PMIC_FG_OSR, PMIC_FG_OSR_ADDR, PMIC_FG_OSR_MASK, PMIC_FG_OSR_SHIFT},
	{PMIC_FG_ADJ_OFFSET_EN, PMIC_FG_ADJ_OFFSET_EN_ADDR,
	 PMIC_FG_ADJ_OFFSET_EN_MASK, PMIC_FG_ADJ_OFFSET_EN_SHIFT},
	{PMIC_FG_ADC_AUTORST, PMIC_FG_ADC_AUTORST_ADDR, PMIC_FG_ADC_AUTORST_MASK,
	 PMIC_FG_ADC_AUTORST_SHIFT},
	{PMIC_FG_FIR1BYPASS, PMIC_FG_FIR1BYPASS_ADDR, PMIC_FG_FIR1BYPASS_MASK,
	 PMIC_FG_FIR1BYPASS_SHIFT},
	{PMIC_FG_FIR2BYPASS, PMIC_FG_FIR2BYPASS_ADDR, PMIC_FG_FIR2BYPASS_MASK,
	 PMIC_FG_FIR2BYPASS_SHIFT},
	{PMIC_FG_L_CUR_INT_STS, PMIC_FG_L_CUR_INT_STS_ADDR,
	 PMIC_FG_L_CUR_INT_STS_MASK, PMIC_FG_L_CUR_INT_STS_SHIFT},
	{PMIC_FG_H_CUR_INT_STS, PMIC_FG_H_CUR_INT_STS_ADDR,
	 PMIC_FG_H_CUR_INT_STS_MASK, PMIC_FG_H_CUR_INT_STS_SHIFT},
	{PMIC_FG_L_INT_STS, PMIC_FG_L_INT_STS_ADDR, PMIC_FG_L_INT_STS_MASK,
	 PMIC_FG_L_INT_STS_SHIFT},
	{PMIC_FG_H_INT_STS, PMIC_FG_H_INT_STS_ADDR, PMIC_FG_H_INT_STS_MASK,
	 PMIC_FG_H_INT_STS_SHIFT},
	{PMIC_FG_ADC_RSTDETECT, PMIC_FG_ADC_RSTDETECT_ADDR,
	 PMIC_FG_ADC_RSTDETECT_MASK, PMIC_FG_ADC_RSTDETECT_SHIFT},
	{PMIC_FG_SLP_EN, PMIC_FG_SLP_EN_ADDR, PMIC_FG_SLP_EN_MASK,
	 PMIC_FG_SLP_EN_SHIFT},
	{PMIC_FG_ZCV_DET_EN, PMIC_FG_ZCV_DET_EN_ADDR, PMIC_FG_ZCV_DET_EN_MASK,
	 PMIC_FG_ZCV_DET_EN_SHIFT},
	{PMIC_RG_FG_AUXADC_R, PMIC_RG_FG_AUXADC_R_ADDR, PMIC_RG_FG_AUXADC_R_MASK,
	 PMIC_RG_FG_AUXADC_R_SHIFT},
	{PMIC_DA_FGADC_EN, PMIC_DA_FGADC_EN_ADDR, PMIC_DA_FGADC_EN_MASK,
	 PMIC_DA_FGADC_EN_SHIFT},
	{PMIC_DA_FGCAL_EN, PMIC_DA_FGCAL_EN_ADDR, PMIC_DA_FGCAL_EN_MASK,
	 PMIC_DA_FGCAL_EN_SHIFT},
	{PMIC_DA_FG_RST, PMIC_DA_FG_RST_ADDR, PMIC_DA_FG_RST_MASK,
	 PMIC_DA_FG_RST_SHIFT},
	{PMIC_FG_CIC2, PMIC_FG_CIC2_ADDR, PMIC_FG_CIC2_MASK,
	 PMIC_FG_CIC2_SHIFT},
	{PMIC_FG_SLP_CUR_TH, PMIC_FG_SLP_CUR_TH_ADDR, PMIC_FG_SLP_CUR_TH_MASK,
	 PMIC_FG_SLP_CUR_TH_SHIFT},
	{PMIC_FG_SLP_TIME, PMIC_FG_SLP_TIME_ADDR, PMIC_FG_SLP_TIME_MASK,
	 PMIC_FG_SLP_TIME_SHIFT},
	{PMIC_FG_SRCVOLTEN_FTIME, PMIC_FG_SRCVOLTEN_FTIME_ADDR,
	 PMIC_FG_SRCVOLTEN_FTIME_MASK, PMIC_FG_SRCVOLTEN_FTIME_SHIFT},
	{PMIC_FG_DET_TIME, PMIC_FG_DET_TIME_ADDR, PMIC_FG_DET_TIME_MASK,
	 PMIC_FG_DET_TIME_SHIFT},
	{PMIC_FG_ZCV_CAR_34_19, PMIC_FG_ZCV_CAR_34_19_ADDR,
	 PMIC_FG_ZCV_CAR_34_19_MASK, PMIC_FG_ZCV_CAR_34_19_SHIFT},
	{PMIC_FG_ZCV_CAR_18_03, PMIC_FG_ZCV_CAR_18_03_ADDR,
	 PMIC_FG_ZCV_CAR_18_03_MASK, PMIC_FG_ZCV_CAR_18_03_SHIFT},
	{PMIC_FG_ZCV_CAR_02_00, PMIC_FG_ZCV_CAR_02_00_ADDR,
	 PMIC_FG_ZCV_CAR_02_00_MASK, PMIC_FG_ZCV_CAR_02_00_SHIFT},
	{PMIC_FG_ZCV_CURR, PMIC_FG_ZCV_CURR_ADDR, PMIC_FG_ZCV_CURR_MASK,
	 PMIC_FG_ZCV_CURR_SHIFT},
	{PMIC_FG_R_CURR, PMIC_FG_R_CURR_ADDR, PMIC_FG_R_CURR_MASK,
	 PMIC_FG_R_CURR_SHIFT},
	{PMIC_FG_MODE, PMIC_FG_MODE_ADDR, PMIC_FG_MODE_MASK,
	 PMIC_FG_MODE_SHIFT},
	{PMIC_FG_RST_SW, PMIC_FG_RST_SW_ADDR, PMIC_FG_RST_SW_MASK,
	 PMIC_FG_RST_SW_SHIFT},
	{PMIC_FG_FGCAL_EN_SW, PMIC_FG_FGCAL_EN_SW_ADDR, PMIC_FG_FGCAL_EN_SW_MASK,
	 PMIC_FG_FGCAL_EN_SW_SHIFT},
	{PMIC_FG_FGADC_EN_SW, PMIC_FG_FGADC_EN_SW_ADDR, PMIC_FG_FGADC_EN_SW_MASK,
	 PMIC_FG_FGADC_EN_SW_SHIFT},
	{PMIC_FG_RSV1, PMIC_FG_RSV1_ADDR, PMIC_FG_RSV1_MASK,
	 PMIC_FG_RSV1_SHIFT},
	{PMIC_FG_TEST_MODE0, PMIC_FG_TEST_MODE0_ADDR, PMIC_FG_TEST_MODE0_MASK,
	 PMIC_FG_TEST_MODE0_SHIFT},
	{PMIC_FG_TEST_MODE1, PMIC_FG_TEST_MODE1_ADDR, PMIC_FG_TEST_MODE1_MASK,
	 PMIC_FG_TEST_MODE1_SHIFT},
	{PMIC_FG_GAIN, PMIC_FG_GAIN_ADDR, PMIC_FG_GAIN_MASK,
	 PMIC_FG_GAIN_SHIFT},
	{PMIC_FG_CUR_HTH, PMIC_FG_CUR_HTH_ADDR, PMIC_FG_CUR_HTH_MASK,
	 PMIC_FG_CUR_HTH_SHIFT},
	{PMIC_FG_CUR_LTH, PMIC_FG_CUR_LTH_ADDR, PMIC_FG_CUR_LTH_MASK,
	 PMIC_FG_CUR_LTH_SHIFT},
	{PMIC_FG_ZCV_DET_TIME, PMIC_FG_ZCV_DET_TIME_ADDR, PMIC_FG_ZCV_DET_TIME_MASK,
	 PMIC_FG_ZCV_DET_TIME_SHIFT},
	{PMIC_FG_ZCV_CAR_TH_33_19, PMIC_FG_ZCV_CAR_TH_33_19_ADDR,
	 PMIC_FG_ZCV_CAR_TH_33_19_MASK, PMIC_FG_ZCV_CAR_TH_33_19_SHIFT},
	{PMIC_FG_ZCV_CAR_TH_18_03, PMIC_FG_ZCV_CAR_TH_18_03_ADDR,
	 PMIC_FG_ZCV_CAR_TH_18_03_MASK, PMIC_FG_ZCV_CAR_TH_18_03_SHIFT},
	{PMIC_FG_ZCV_CAR_TH_02_00, PMIC_FG_ZCV_CAR_TH_02_00_ADDR,
	 PMIC_FG_ZCV_CAR_TH_02_00_MASK, PMIC_FG_ZCV_CAR_TH_02_00_SHIFT},
	{PMIC_SYSTEM_INFO_CON0, PMIC_SYSTEM_INFO_CON0_ADDR,
	 PMIC_SYSTEM_INFO_CON0_MASK, PMIC_SYSTEM_INFO_CON0_SHIFT},
	{PMIC_SYSTEM_INFO_CON1, PMIC_SYSTEM_INFO_CON1_ADDR,
	 PMIC_SYSTEM_INFO_CON1_MASK, PMIC_SYSTEM_INFO_CON1_SHIFT},
	{PMIC_SYSTEM_INFO_CON2, PMIC_SYSTEM_INFO_CON2_ADDR,
	 PMIC_SYSTEM_INFO_CON2_MASK, PMIC_SYSTEM_INFO_CON2_SHIFT},
	{PMIC_SYSTEM_INFO_CON3, PMIC_SYSTEM_INFO_CON3_ADDR,
	 PMIC_SYSTEM_INFO_CON3_MASK, PMIC_SYSTEM_INFO_CON3_SHIFT},
	{PMIC_SYSTEM_INFO_CON4, PMIC_SYSTEM_INFO_CON4_ADDR,
	 PMIC_SYSTEM_INFO_CON4_MASK, PMIC_SYSTEM_INFO_CON4_SHIFT},
	{PMIC_RG_AUDDACLPWRUP_VAUDP15, PMIC_RG_AUDDACLPWRUP_VAUDP15_ADDR,
	 PMIC_RG_AUDDACLPWRUP_VAUDP15_MASK, PMIC_RG_AUDDACLPWRUP_VAUDP15_SHIFT},
	{PMIC_RG_AUDDACRPWRUP_VAUDP15, PMIC_RG_AUDDACRPWRUP_VAUDP15_ADDR,
	 PMIC_RG_AUDDACRPWRUP_VAUDP15_MASK, PMIC_RG_AUDDACRPWRUP_VAUDP15_SHIFT},
	{PMIC_RG_AUD_DAC_PWR_UP_VA28, PMIC_RG_AUD_DAC_PWR_UP_VA28_ADDR,
	 PMIC_RG_AUD_DAC_PWR_UP_VA28_MASK, PMIC_RG_AUD_DAC_PWR_UP_VA28_SHIFT},
	{PMIC_RG_AUD_DAC_PWL_UP_VA28, PMIC_RG_AUD_DAC_PWL_UP_VA28_ADDR,
	 PMIC_RG_AUD_DAC_PWL_UP_VA28_MASK, PMIC_RG_AUD_DAC_PWL_UP_VA28_SHIFT},
	{PMIC_RG_AUDHSPWRUP_VAUDP15, PMIC_RG_AUDHSPWRUP_VAUDP15_ADDR,
	 PMIC_RG_AUDHSPWRUP_VAUDP15_MASK, PMIC_RG_AUDHSPWRUP_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPLPWRUP_VAUDP15, PMIC_RG_AUDHPLPWRUP_VAUDP15_ADDR,
	 PMIC_RG_AUDHPLPWRUP_VAUDP15_MASK, PMIC_RG_AUDHPLPWRUP_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPRPWRUP_VAUDP15, PMIC_RG_AUDHPRPWRUP_VAUDP15_ADDR,
	 PMIC_RG_AUDHPRPWRUP_VAUDP15_MASK, PMIC_RG_AUDHPRPWRUP_VAUDP15_SHIFT},
	{PMIC_RG_AUDHSMUXINPUTSEL_VAUDP15, PMIC_RG_AUDHSMUXINPUTSEL_VAUDP15_ADDR,
	 PMIC_RG_AUDHSMUXINPUTSEL_VAUDP15_MASK,
	 PMIC_RG_AUDHSMUXINPUTSEL_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPLMUXINPUTSEL_VAUDP15, PMIC_RG_AUDHPLMUXINPUTSEL_VAUDP15_ADDR,
	 PMIC_RG_AUDHPLMUXINPUTSEL_VAUDP15_MASK,
	 PMIC_RG_AUDHPLMUXINPUTSEL_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPRMUXINPUTSEL_VAUDP15, PMIC_RG_AUDHPRMUXINPUTSEL_VAUDP15_ADDR,
	 PMIC_RG_AUDHPRMUXINPUTSEL_VAUDP15_MASK,
	 PMIC_RG_AUDHPRMUXINPUTSEL_VAUDP15_SHIFT},
	{PMIC_RG_AUDHSSCDISABLE_VAUDP15, PMIC_RG_AUDHSSCDISABLE_VAUDP15_ADDR,
	 PMIC_RG_AUDHSSCDISABLE_VAUDP15_MASK, PMIC_RG_AUDHSSCDISABLE_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPLSCDISABLE_VAUDP15, PMIC_RG_AUDHPLSCDISABLE_VAUDP15_ADDR,
	 PMIC_RG_AUDHPLSCDISABLE_VAUDP15_MASK, PMIC_RG_AUDHPLSCDISABLE_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPRSCDISABLE_VAUDP15, PMIC_RG_AUDHPRSCDISABLE_VAUDP15_ADDR,
	 PMIC_RG_AUDHPRSCDISABLE_VAUDP15_MASK, PMIC_RG_AUDHPRSCDISABLE_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPLBSCCURRENT_VAUDP15, PMIC_RG_AUDHPLBSCCURRENT_VAUDP15_ADDR,
	 PMIC_RG_AUDHPLBSCCURRENT_VAUDP15_MASK,
	 PMIC_RG_AUDHPLBSCCURRENT_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPRBSCCURRENT_VAUDP15, PMIC_RG_AUDHPRBSCCURRENT_VAUDP15_ADDR,
	 PMIC_RG_AUDHPRBSCCURRENT_VAUDP15_MASK,
	 PMIC_RG_AUDHPRBSCCURRENT_VAUDP15_SHIFT},
	{PMIC_RG_AUDHSBSCCURRENT_VAUDP15, PMIC_RG_AUDHSBSCCURRENT_VAUDP15_ADDR,
	 PMIC_RG_AUDHSBSCCURRENT_VAUDP15_MASK, PMIC_RG_AUDHSBSCCURRENT_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPSTARTUP_VAUDP15, PMIC_RG_AUDHPSTARTUP_VAUDP15_ADDR,
	 PMIC_RG_AUDHPSTARTUP_VAUDP15_MASK, PMIC_RG_AUDHPSTARTUP_VAUDP15_SHIFT},
	{PMIC_RG_AUDHSSTARTUP_VAUDP15, PMIC_RG_AUDHSSTARTUP_VAUDP15_ADDR,
	 PMIC_RG_AUDHSSTARTUP_VAUDP15_MASK, PMIC_RG_AUDHSSTARTUP_VAUDP15_SHIFT},
	{PMIC_RG_PRECHARGEBUF_EN_VAUDP15, PMIC_RG_PRECHARGEBUF_EN_VAUDP15_ADDR,
	 PMIC_RG_PRECHARGEBUF_EN_VAUDP15_MASK, PMIC_RG_PRECHARGEBUF_EN_VAUDP15_SHIFT},
	{PMIC_RG_HPINPUTSTBENH_VAUDP15, PMIC_RG_HPINPUTSTBENH_VAUDP15_ADDR,
	 PMIC_RG_HPINPUTSTBENH_VAUDP15_MASK, PMIC_RG_HPINPUTSTBENH_VAUDP15_SHIFT},
	{PMIC_RG_HPOUTPUTSTBENH_VAUDP15, PMIC_RG_HPOUTPUTSTBENH_VAUDP15_ADDR,
	 PMIC_RG_HPOUTPUTSTBENH_VAUDP15_MASK, PMIC_RG_HPOUTPUTSTBENH_VAUDP15_SHIFT},
	{PMIC_RG_HPINPUTRESET0_VAUDP15, PMIC_RG_HPINPUTRESET0_VAUDP15_ADDR,
	 PMIC_RG_HPINPUTRESET0_VAUDP15_MASK, PMIC_RG_HPINPUTRESET0_VAUDP15_SHIFT},
	{PMIC_RG_HPOUTPUTRESET0_VAUDP15, PMIC_RG_HPOUTPUTRESET0_VAUDP15_ADDR,
	 PMIC_RG_HPOUTPUTRESET0_VAUDP15_MASK, PMIC_RG_HPOUTPUTRESET0_VAUDP15_SHIFT},
	{PMIC_RG_HPOUT_SHORTVCM_VAUDP15, PMIC_RG_HPOUT_SHORTVCM_VAUDP15_ADDR,
	 PMIC_RG_HPOUT_SHORTVCM_VAUDP15_MASK, PMIC_RG_HPOUT_SHORTVCM_VAUDP15_SHIFT},
	{PMIC_RG_HSINPUTSTBENH_VAUDP15, PMIC_RG_HSINPUTSTBENH_VAUDP15_ADDR,
	 PMIC_RG_HSINPUTSTBENH_VAUDP15_MASK, PMIC_RG_HSINPUTSTBENH_VAUDP15_SHIFT},
	{PMIC_RG_HSOUTPUTSTBENH_VAUDP15, PMIC_RG_HSOUTPUTSTBENH_VAUDP15_ADDR,
	 PMIC_RG_HSOUTPUTSTBENH_VAUDP15_MASK, PMIC_RG_HSOUTPUTSTBENH_VAUDP15_SHIFT},
	{PMIC_RG_HSINPUTRESET0_VAUDP15, PMIC_RG_HSINPUTRESET0_VAUDP15_ADDR,
	 PMIC_RG_HSINPUTRESET0_VAUDP15_MASK, PMIC_RG_HSINPUTRESET0_VAUDP15_SHIFT},
	{PMIC_RG_HSOUTPUTRESET0_VAUDP15, PMIC_RG_HSOUTPUTRESET0_VAUDP15_ADDR,
	 PMIC_RG_HSOUTPUTRESET0_VAUDP15_MASK, PMIC_RG_HSOUTPUTRESET0_VAUDP15_SHIFT},
	{PMIC_RG_HPOUTSTB_RSEL_VAUDP15, PMIC_RG_HPOUTSTB_RSEL_VAUDP15_ADDR,
	 PMIC_RG_HPOUTSTB_RSEL_VAUDP15_MASK, PMIC_RG_HPOUTSTB_RSEL_VAUDP15_SHIFT},
	{PMIC_RG_HSOUT_SHORTVCM_VAUDP15, PMIC_RG_HSOUT_SHORTVCM_VAUDP15_ADDR,
	 PMIC_RG_HSOUT_SHORTVCM_VAUDP15_MASK, PMIC_RG_HSOUT_SHORTVCM_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPLTRIM_VAUDP15, PMIC_RG_AUDHPLTRIM_VAUDP15_ADDR,
	 PMIC_RG_AUDHPLTRIM_VAUDP15_MASK, PMIC_RG_AUDHPLTRIM_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPRTRIM_VAUDP15, PMIC_RG_AUDHPRTRIM_VAUDP15_ADDR,
	 PMIC_RG_AUDHPRTRIM_VAUDP15_MASK, PMIC_RG_AUDHPRTRIM_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPTRIM_EN_VAUDP15, PMIC_RG_AUDHPTRIM_EN_VAUDP15_ADDR,
	 PMIC_RG_AUDHPTRIM_EN_VAUDP15_MASK, PMIC_RG_AUDHPTRIM_EN_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPLFINETRIM_VAUDP15, PMIC_RG_AUDHPLFINETRIM_VAUDP15_ADDR,
	 PMIC_RG_AUDHPLFINETRIM_VAUDP15_MASK, PMIC_RG_AUDHPLFINETRIM_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPRFINETRIM_VAUDP15, PMIC_RG_AUDHPRFINETRIM_VAUDP15_ADDR,
	 PMIC_RG_AUDHPRFINETRIM_VAUDP15_MASK, PMIC_RG_AUDHPRFINETRIM_VAUDP15_SHIFT},
	{PMIC_RG_AUDTRIMBUF_EN_VAUDP15, PMIC_RG_AUDTRIMBUF_EN_VAUDP15_ADDR,
	 PMIC_RG_AUDTRIMBUF_EN_VAUDP15_MASK, PMIC_RG_AUDTRIMBUF_EN_VAUDP15_SHIFT},
	{PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15, PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_ADDR,
	 PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK,
	 PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_SHIFT},
	{PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP15, PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP15_ADDR,
	 PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK,
	 PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPSPKDET_EN_VAUDP15, PMIC_RG_AUDHPSPKDET_EN_VAUDP15_ADDR,
	 PMIC_RG_AUDHPSPKDET_EN_VAUDP15_MASK, PMIC_RG_AUDHPSPKDET_EN_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15,
	 PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_ADDR,
	 PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK,
	 PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_SHIFT},
	{PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15,
	 PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_ADDR,
	 PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK,
	 PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_SHIFT},
	{PMIC_RG_ABIDEC_RESERVED_VA28, PMIC_RG_ABIDEC_RESERVED_VA28_ADDR,
	 PMIC_RG_ABIDEC_RESERVED_VA28_MASK, PMIC_RG_ABIDEC_RESERVED_VA28_SHIFT},
	{PMIC_RG_ABIDEC_RESERVED_VAUDP15, PMIC_RG_ABIDEC_RESERVED_VAUDP15_ADDR,
	 PMIC_RG_ABIDEC_RESERVED_VAUDP15_MASK, PMIC_RG_ABIDEC_RESERVED_VAUDP15_SHIFT},
	{PMIC_RG_AUDBIASADJ_0_VAUDP15, PMIC_RG_AUDBIASADJ_0_VAUDP15_ADDR,
	 PMIC_RG_AUDBIASADJ_0_VAUDP15_MASK, PMIC_RG_AUDBIASADJ_0_VAUDP15_SHIFT},
	{PMIC_RG_AUDBIASADJ_1_VAUDP15, PMIC_RG_AUDBIASADJ_1_VAUDP15_ADDR,
	 PMIC_RG_AUDBIASADJ_1_VAUDP15_MASK, PMIC_RG_AUDBIASADJ_1_VAUDP15_SHIFT},
	{PMIC_RG_AUDIBIASPWRDN_VAUDP15, PMIC_RG_AUDIBIASPWRDN_VAUDP15_ADDR,
	 PMIC_RG_AUDIBIASPWRDN_VAUDP15_MASK, PMIC_RG_AUDIBIASPWRDN_VAUDP15_SHIFT},
	{PMIC_RG_RSTB_DECODER_VA28, PMIC_RG_RSTB_DECODER_VA28_ADDR,
	 PMIC_RG_RSTB_DECODER_VA28_MASK, PMIC_RG_RSTB_DECODER_VA28_SHIFT},
	{PMIC_RG_RSTB_ENCODER_VA28, PMIC_RG_RSTB_ENCODER_VA28_ADDR,
	 PMIC_RG_RSTB_ENCODER_VA28_MASK, PMIC_RG_RSTB_ENCODER_VA28_SHIFT},
	{PMIC_RG_SEL_DECODER_96K_VA28, PMIC_RG_SEL_DECODER_96K_VA28_ADDR,
	 PMIC_RG_SEL_DECODER_96K_VA28_MASK, PMIC_RG_SEL_DECODER_96K_VA28_SHIFT},
	{PMIC_RG_SEL_ENCODER_96K_VA28, PMIC_RG_SEL_ENCODER_96K_VA28_ADDR,
	 PMIC_RG_SEL_ENCODER_96K_VA28_MASK, PMIC_RG_SEL_ENCODER_96K_VA28_SHIFT},
	{PMIC_RG_SEL_DELAY_VCORE, PMIC_RG_SEL_DELAY_VCORE_ADDR,
	 PMIC_RG_SEL_DELAY_VCORE_MASK, PMIC_RG_SEL_DELAY_VCORE_SHIFT},
	{PMIC_RG_HCLDO_EN_VA18, PMIC_RG_HCLDO_EN_VA18_ADDR,
	 PMIC_RG_HCLDO_EN_VA18_MASK, PMIC_RG_HCLDO_EN_VA18_SHIFT},
	{PMIC_RG_LCLDO_EN_VA18, PMIC_RG_LCLDO_EN_VA18_ADDR,
	 PMIC_RG_LCLDO_EN_VA18_MASK, PMIC_RG_LCLDO_EN_VA18_SHIFT},
	{PMIC_RG_LCLDO_ENC_EN_VA28, PMIC_RG_LCLDO_ENC_EN_VA28_ADDR,
	 PMIC_RG_LCLDO_ENC_EN_VA28_MASK, PMIC_RG_LCLDO_ENC_EN_VA28_SHIFT},
	{PMIC_RG_VA33REFGEN_EN_VA18, PMIC_RG_VA33REFGEN_EN_VA18_ADDR,
	 PMIC_RG_VA33REFGEN_EN_VA18_MASK, PMIC_RG_VA33REFGEN_EN_VA18_SHIFT},
	{PMIC_RG_HCLDO_PDDIS_EN_VA18, PMIC_RG_HCLDO_PDDIS_EN_VA18_ADDR,
	 PMIC_RG_HCLDO_PDDIS_EN_VA18_MASK, PMIC_RG_HCLDO_PDDIS_EN_VA18_SHIFT},
	{PMIC_RG_HCLDO_REMOTE_SENSE_VA18, PMIC_RG_HCLDO_REMOTE_SENSE_VA18_ADDR,
	 PMIC_RG_HCLDO_REMOTE_SENSE_VA18_MASK, PMIC_RG_HCLDO_REMOTE_SENSE_VA18_SHIFT},
	{PMIC_RG_LCLDO_PDDIS_EN_VA18, PMIC_RG_LCLDO_PDDIS_EN_VA18_ADDR,
	 PMIC_RG_LCLDO_PDDIS_EN_VA18_MASK, PMIC_RG_LCLDO_PDDIS_EN_VA18_SHIFT},
	{PMIC_RG_LCLDO_REMOTE_SENSE_VA18, PMIC_RG_LCLDO_REMOTE_SENSE_VA18_ADDR,
	 PMIC_RG_LCLDO_REMOTE_SENSE_VA18_MASK, PMIC_RG_LCLDO_REMOTE_SENSE_VA18_SHIFT},
	{PMIC_RG_LCLDO_VOSEL_VA18, PMIC_RG_LCLDO_VOSEL_VA18_ADDR,
	 PMIC_RG_LCLDO_VOSEL_VA18_MASK, PMIC_RG_LCLDO_VOSEL_VA18_SHIFT},
	{PMIC_RG_HCLDO_VOSEL_VA18, PMIC_RG_HCLDO_VOSEL_VA18_ADDR,
	 PMIC_RG_HCLDO_VOSEL_VA18_MASK, PMIC_RG_HCLDO_VOSEL_VA18_SHIFT},
	{PMIC_RG_LCLDO_ENC_PDDIS_EN_VA28, PMIC_RG_LCLDO_ENC_PDDIS_EN_VA28_ADDR,
	 PMIC_RG_LCLDO_ENC_PDDIS_EN_VA28_MASK, PMIC_RG_LCLDO_ENC_PDDIS_EN_VA28_SHIFT},
	{PMIC_RG_LCLDO_ENC_REMOTE_SENSE_VA28, PMIC_RG_LCLDO_ENC_REMOTE_SENSE_VA28_ADDR,
	 PMIC_RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK,
	 PMIC_RG_LCLDO_ENC_REMOTE_SENSE_VA28_SHIFT},
	{PMIC_RG_VA28REFGEN_EN_VA28, PMIC_RG_VA28REFGEN_EN_VA28_ADDR,
	 PMIC_RG_VA28REFGEN_EN_VA28_MASK, PMIC_RG_VA28REFGEN_EN_VA28_SHIFT},
	{PMIC_RG_AUDPMU_RESERVED_VA28, PMIC_RG_AUDPMU_RESERVED_VA28_ADDR,
	 PMIC_RG_AUDPMU_RESERVED_VA28_MASK, PMIC_RG_AUDPMU_RESERVED_VA28_SHIFT},
	{PMIC_RG_AUDPMU_RESERVED_VA18, PMIC_RG_AUDPMU_RESERVED_VA18_ADDR,
	 PMIC_RG_AUDPMU_RESERVED_VA18_MASK, PMIC_RG_AUDPMU_RESERVED_VA18_SHIFT},
	{PMIC_RG_AUDPMU_RESERVED_VAUDP15, PMIC_RG_AUDPMU_RESERVED_VAUDP15_ADDR,
	 PMIC_RG_AUDPMU_RESERVED_VAUDP15_MASK, PMIC_RG_AUDPMU_RESERVED_VAUDP15_SHIFT},
	{PMIC_RG_NVREG_EN_VAUDP15, PMIC_RG_NVREG_EN_VAUDP15_ADDR,
	 PMIC_RG_NVREG_EN_VAUDP15_MASK, PMIC_RG_NVREG_EN_VAUDP15_SHIFT},
	{PMIC_RG_NVREG_PULL0V_VAUDP15, PMIC_RG_NVREG_PULL0V_VAUDP15_ADDR,
	 PMIC_RG_NVREG_PULL0V_VAUDP15_MASK, PMIC_RG_NVREG_PULL0V_VAUDP15_SHIFT},
	{PMIC_RG_AUDGLB_PWRDN_VA28, PMIC_RG_AUDGLB_PWRDN_VA28_ADDR,
	 PMIC_RG_AUDGLB_PWRDN_VA28_MASK, PMIC_RG_AUDGLB_PWRDN_VA28_SHIFT},
	{PMIC_RG_AUDPREAMPLON, PMIC_RG_AUDPREAMPLON_ADDR, PMIC_RG_AUDPREAMPLON_MASK,
	 PMIC_RG_AUDPREAMPLON_SHIFT},
	{PMIC_RG_AUDPREAMPLDCCEN, PMIC_RG_AUDPREAMPLDCCEN_ADDR,
	 PMIC_RG_AUDPREAMPLDCCEN_MASK, PMIC_RG_AUDPREAMPLDCCEN_SHIFT},
	{PMIC_RG_AUDPREAMPLDCRPECHARGE, PMIC_RG_AUDPREAMPLDCRPECHARGE_ADDR,
	 PMIC_RG_AUDPREAMPLDCRPECHARGE_MASK, PMIC_RG_AUDPREAMPLDCRPECHARGE_SHIFT},
	{PMIC_RG_AUDPREAMPLPGATEST, PMIC_RG_AUDPREAMPLPGATEST_ADDR,
	 PMIC_RG_AUDPREAMPLPGATEST_MASK, PMIC_RG_AUDPREAMPLPGATEST_SHIFT},
	{PMIC_RG_AUDPREAMPLVSCALE, PMIC_RG_AUDPREAMPLVSCALE_ADDR,
	 PMIC_RG_AUDPREAMPLVSCALE_MASK, PMIC_RG_AUDPREAMPLVSCALE_SHIFT},
	{PMIC_RG_AUDPREAMPLINPUTSEL, PMIC_RG_AUDPREAMPLINPUTSEL_ADDR,
	 PMIC_RG_AUDPREAMPLINPUTSEL_MASK, PMIC_RG_AUDPREAMPLINPUTSEL_SHIFT},
	{PMIC_RG_AUDADCLPWRUP, PMIC_RG_AUDADCLPWRUP_ADDR, PMIC_RG_AUDADCLPWRUP_MASK,
	 PMIC_RG_AUDADCLPWRUP_SHIFT},
	{PMIC_RG_AUDADCLINPUTSEL, PMIC_RG_AUDADCLINPUTSEL_ADDR,
	 PMIC_RG_AUDADCLINPUTSEL_MASK, PMIC_RG_AUDADCLINPUTSEL_SHIFT},
	{PMIC_RG_AUDPREAMPRON, PMIC_RG_AUDPREAMPRON_ADDR, PMIC_RG_AUDPREAMPRON_MASK,
	 PMIC_RG_AUDPREAMPRON_SHIFT},
	{PMIC_RG_AUDPREAMPRDCCEN, PMIC_RG_AUDPREAMPRDCCEN_ADDR,
	 PMIC_RG_AUDPREAMPRDCCEN_MASK, PMIC_RG_AUDPREAMPRDCCEN_SHIFT},
	{PMIC_RG_AUDPREAMPRDCRPECHARGE, PMIC_RG_AUDPREAMPRDCRPECHARGE_ADDR,
	 PMIC_RG_AUDPREAMPRDCRPECHARGE_MASK, PMIC_RG_AUDPREAMPRDCRPECHARGE_SHIFT},
	{PMIC_RG_AUDPREAMPRPGATEST, PMIC_RG_AUDPREAMPRPGATEST_ADDR,
	 PMIC_RG_AUDPREAMPRPGATEST_MASK, PMIC_RG_AUDPREAMPRPGATEST_SHIFT},
	{PMIC_RG_AUDPREAMPRVSCALE, PMIC_RG_AUDPREAMPRVSCALE_ADDR,
	 PMIC_RG_AUDPREAMPRVSCALE_MASK, PMIC_RG_AUDPREAMPRVSCALE_SHIFT},
	{PMIC_RG_AUDPREAMPRINPUTSEL, PMIC_RG_AUDPREAMPRINPUTSEL_ADDR,
	 PMIC_RG_AUDPREAMPRINPUTSEL_MASK, PMIC_RG_AUDPREAMPRINPUTSEL_SHIFT},
	{PMIC_RG_AUDADCRPWRUP, PMIC_RG_AUDADCRPWRUP_ADDR, PMIC_RG_AUDADCRPWRUP_MASK,
	 PMIC_RG_AUDADCRPWRUP_SHIFT},
	{PMIC_RG_AUDADCRINPUTSEL, PMIC_RG_AUDADCRINPUTSEL_ADDR,
	 PMIC_RG_AUDADCRINPUTSEL_MASK, PMIC_RG_AUDADCRINPUTSEL_SHIFT},
	{PMIC_RG_AUDULHALFBIAS, PMIC_RG_AUDULHALFBIAS_ADDR,
	 PMIC_RG_AUDULHALFBIAS_MASK, PMIC_RG_AUDULHALFBIAS_SHIFT},
	{PMIC_RG_AUDGLBMADLPWEN, PMIC_RG_AUDGLBMADLPWEN_ADDR,
	 PMIC_RG_AUDGLBMADLPWEN_MASK, PMIC_RG_AUDGLBMADLPWEN_SHIFT},
	{PMIC_RG_AUDPREAMPLPEN, PMIC_RG_AUDPREAMPLPEN_ADDR,
	 PMIC_RG_AUDPREAMPLPEN_MASK, PMIC_RG_AUDPREAMPLPEN_SHIFT},
	{PMIC_RG_AUDADC1STSTAGELPEN, PMIC_RG_AUDADC1STSTAGELPEN_ADDR,
	 PMIC_RG_AUDADC1STSTAGELPEN_MASK, PMIC_RG_AUDADC1STSTAGELPEN_SHIFT},
	{PMIC_RG_AUDADC2NDSTAGELPEN, PMIC_RG_AUDADC2NDSTAGELPEN_ADDR,
	 PMIC_RG_AUDADC2NDSTAGELPEN_MASK, PMIC_RG_AUDADC2NDSTAGELPEN_SHIFT},
	{PMIC_RG_AUDADCFLASHLPEN, PMIC_RG_AUDADCFLASHLPEN_ADDR,
	 PMIC_RG_AUDADCFLASHLPEN_MASK, PMIC_RG_AUDADCFLASHLPEN_SHIFT},
	{PMIC_RG_AUDPREAMPIDDTEST, PMIC_RG_AUDPREAMPIDDTEST_ADDR,
	 PMIC_RG_AUDPREAMPIDDTEST_MASK, PMIC_RG_AUDPREAMPIDDTEST_SHIFT},
	{PMIC_RG_AUDADC1STSTAGEIDDTEST, PMIC_RG_AUDADC1STSTAGEIDDTEST_ADDR,
	 PMIC_RG_AUDADC1STSTAGEIDDTEST_MASK, PMIC_RG_AUDADC1STSTAGEIDDTEST_SHIFT},
	{PMIC_RG_AUDADC2NDSTAGEIDDTEST, PMIC_RG_AUDADC2NDSTAGEIDDTEST_ADDR,
	 PMIC_RG_AUDADC2NDSTAGEIDDTEST_MASK, PMIC_RG_AUDADC2NDSTAGEIDDTEST_SHIFT},
	{PMIC_RG_AUDADCREFBUFIDDTEST, PMIC_RG_AUDADCREFBUFIDDTEST_ADDR,
	 PMIC_RG_AUDADCREFBUFIDDTEST_MASK, PMIC_RG_AUDADCREFBUFIDDTEST_SHIFT},
	{PMIC_RG_AUDADCFLASHIDDTEST, PMIC_RG_AUDADCFLASHIDDTEST_ADDR,
	 PMIC_RG_AUDADCFLASHIDDTEST_MASK, PMIC_RG_AUDADCFLASHIDDTEST_SHIFT},
	{PMIC_RG_AUDADCDAC0P25FS, PMIC_RG_AUDADCDAC0P25FS_ADDR,
	 PMIC_RG_AUDADCDAC0P25FS_MASK, PMIC_RG_AUDADCDAC0P25FS_SHIFT},
	{PMIC_RG_AUDADCCLKSEL, PMIC_RG_AUDADCCLKSEL_ADDR, PMIC_RG_AUDADCCLKSEL_MASK,
	 PMIC_RG_AUDADCCLKSEL_SHIFT},
	{PMIC_RG_AUDADCCLKSOURCE, PMIC_RG_AUDADCCLKSOURCE_ADDR,
	 PMIC_RG_AUDADCCLKSOURCE_MASK, PMIC_RG_AUDADCCLKSOURCE_SHIFT},
	{PMIC_RG_AUDADCCLKGENMODE, PMIC_RG_AUDADCCLKGENMODE_ADDR,
	 PMIC_RG_AUDADCCLKGENMODE_MASK, PMIC_RG_AUDADCCLKGENMODE_SHIFT},
	{PMIC_RG_AUDPREAMPAAFEN, PMIC_RG_AUDPREAMPAAFEN_ADDR,
	 PMIC_RG_AUDPREAMPAAFEN_MASK, PMIC_RG_AUDPREAMPAAFEN_SHIFT},
	{PMIC_RG_DCCVCMBUFLPMODSEL, PMIC_RG_DCCVCMBUFLPMODSEL_ADDR,
	 PMIC_RG_DCCVCMBUFLPMODSEL_MASK, PMIC_RG_DCCVCMBUFLPMODSEL_SHIFT},
	{PMIC_RG_DCCVCMBUFLPSWEN, PMIC_RG_DCCVCMBUFLPSWEN_ADDR,
	 PMIC_RG_DCCVCMBUFLPSWEN_MASK, PMIC_RG_DCCVCMBUFLPSWEN_SHIFT},
	{PMIC_RG_AUDSPAREPGA, PMIC_RG_AUDSPAREPGA_ADDR, PMIC_RG_AUDSPAREPGA_MASK,
	 PMIC_RG_AUDSPAREPGA_SHIFT},
	{PMIC_RG_AUDADC1STSTAGESDENB, PMIC_RG_AUDADC1STSTAGESDENB_ADDR,
	 PMIC_RG_AUDADC1STSTAGESDENB_MASK, PMIC_RG_AUDADC1STSTAGESDENB_SHIFT},
	{PMIC_RG_AUDADC2NDSTAGERESET, PMIC_RG_AUDADC2NDSTAGERESET_ADDR,
	 PMIC_RG_AUDADC2NDSTAGERESET_MASK, PMIC_RG_AUDADC2NDSTAGERESET_SHIFT},
	{PMIC_RG_AUDADC3RDSTAGERESET, PMIC_RG_AUDADC3RDSTAGERESET_ADDR,
	 PMIC_RG_AUDADC3RDSTAGERESET_MASK, PMIC_RG_AUDADC3RDSTAGERESET_SHIFT},
	{PMIC_RG_AUDADCFSRESET, PMIC_RG_AUDADCFSRESET_ADDR,
	 PMIC_RG_AUDADCFSRESET_MASK, PMIC_RG_AUDADCFSRESET_SHIFT},
	{PMIC_RG_AUDADCWIDECM, PMIC_RG_AUDADCWIDECM_ADDR, PMIC_RG_AUDADCWIDECM_MASK,
	 PMIC_RG_AUDADCWIDECM_SHIFT},
	{PMIC_RG_AUDADCNOPATEST, PMIC_RG_AUDADCNOPATEST_ADDR,
	 PMIC_RG_AUDADCNOPATEST_MASK, PMIC_RG_AUDADCNOPATEST_SHIFT},
	{PMIC_RG_AUDADCBYPASS, PMIC_RG_AUDADCBYPASS_ADDR, PMIC_RG_AUDADCBYPASS_MASK,
	 PMIC_RG_AUDADCBYPASS_SHIFT},
	{PMIC_RG_AUDADCFFBYPASS, PMIC_RG_AUDADCFFBYPASS_ADDR,
	 PMIC_RG_AUDADCFFBYPASS_MASK, PMIC_RG_AUDADCFFBYPASS_SHIFT},
	{PMIC_RG_AUDADCDACFBCURRENT, PMIC_RG_AUDADCDACFBCURRENT_ADDR,
	 PMIC_RG_AUDADCDACFBCURRENT_MASK, PMIC_RG_AUDADCDACFBCURRENT_SHIFT},
	{PMIC_RG_AUDADCDACIDDTEST, PMIC_RG_AUDADCDACIDDTEST_ADDR,
	 PMIC_RG_AUDADCDACIDDTEST_MASK, PMIC_RG_AUDADCDACIDDTEST_SHIFT},
	{PMIC_RG_AUDADCDACNRZ, PMIC_RG_AUDADCDACNRZ_ADDR, PMIC_RG_AUDADCDACNRZ_MASK,
	 PMIC_RG_AUDADCDACNRZ_SHIFT},
	{PMIC_RG_AUDADCNODEM, PMIC_RG_AUDADCNODEM_ADDR, PMIC_RG_AUDADCNODEM_MASK,
	 PMIC_RG_AUDADCNODEM_SHIFT},
	{PMIC_RG_AUDADCDACTEST, PMIC_RG_AUDADCDACTEST_ADDR,
	 PMIC_RG_AUDADCDACTEST_MASK, PMIC_RG_AUDADCDACTEST_SHIFT},
	{PMIC_RG_AUDADCTESTDATA, PMIC_RG_AUDADCTESTDATA_ADDR,
	 PMIC_RG_AUDADCTESTDATA_MASK, PMIC_RG_AUDADCTESTDATA_SHIFT},
	{PMIC_RG_AUDRCTUNEL, PMIC_RG_AUDRCTUNEL_ADDR, PMIC_RG_AUDRCTUNEL_MASK,
	 PMIC_RG_AUDRCTUNEL_SHIFT},
	{PMIC_RG_AUDRCTUNELSEL, PMIC_RG_AUDRCTUNELSEL_ADDR,
	 PMIC_RG_AUDRCTUNELSEL_MASK, PMIC_RG_AUDRCTUNELSEL_SHIFT},
	{PMIC_RG_AUDRCTUNER, PMIC_RG_AUDRCTUNER_ADDR, PMIC_RG_AUDRCTUNER_MASK,
	 PMIC_RG_AUDRCTUNER_SHIFT},
	{PMIC_RG_AUDRCTUNERSEL, PMIC_RG_AUDRCTUNERSEL_ADDR,
	 PMIC_RG_AUDRCTUNERSEL_MASK, PMIC_RG_AUDRCTUNERSEL_SHIFT},
	{PMIC_RG_AUDSPAREVA28, PMIC_RG_AUDSPAREVA28_ADDR, PMIC_RG_AUDSPAREVA28_MASK,
	 PMIC_RG_AUDSPAREVA28_SHIFT},
	{PMIC_RG_AUDSPAREVA18, PMIC_RG_AUDSPAREVA18_ADDR, PMIC_RG_AUDSPAREVA18_MASK,
	 PMIC_RG_AUDSPAREVA18_SHIFT},
	{PMIC_RG_AUDENCSPAREVA28, PMIC_RG_AUDENCSPAREVA28_ADDR,
	 PMIC_RG_AUDENCSPAREVA28_MASK, PMIC_RG_AUDENCSPAREVA28_SHIFT},
	{PMIC_RG_AUDENCSPAREVA18, PMIC_RG_AUDENCSPAREVA18_ADDR,
	 PMIC_RG_AUDENCSPAREVA18_MASK, PMIC_RG_AUDENCSPAREVA18_SHIFT},
	{PMIC_RG_AUDDIGMICEN, PMIC_RG_AUDDIGMICEN_ADDR, PMIC_RG_AUDDIGMICEN_MASK,
	 PMIC_RG_AUDDIGMICEN_SHIFT},
	{PMIC_RG_AUDDIGMICBIAS, PMIC_RG_AUDDIGMICBIAS_ADDR,
	 PMIC_RG_AUDDIGMICBIAS_MASK, PMIC_RG_AUDDIGMICBIAS_SHIFT},
	{PMIC_RG_DMICHPCLKEN, PMIC_RG_DMICHPCLKEN_ADDR, PMIC_RG_DMICHPCLKEN_MASK,
	 PMIC_RG_DMICHPCLKEN_SHIFT},
	{PMIC_RG_AUDDIGMICPDUTY, PMIC_RG_AUDDIGMICPDUTY_ADDR,
	 PMIC_RG_AUDDIGMICPDUTY_MASK, PMIC_RG_AUDDIGMICPDUTY_SHIFT},
	{PMIC_RG_AUDDIGMICNDUTY, PMIC_RG_AUDDIGMICNDUTY_ADDR,
	 PMIC_RG_AUDDIGMICNDUTY_MASK, PMIC_RG_AUDDIGMICNDUTY_SHIFT},
	{PMIC_RG_DMICMONEN, PMIC_RG_DMICMONEN_ADDR, PMIC_RG_DMICMONEN_MASK,
	 PMIC_RG_DMICMONEN_SHIFT},
	{PMIC_RG_DMICMONSEL, PMIC_RG_DMICMONSEL_ADDR, PMIC_RG_DMICMONSEL_MASK,
	 PMIC_RG_DMICMONSEL_SHIFT},
	{PMIC_RG_AUDSPAREVMIC, PMIC_RG_AUDSPAREVMIC_ADDR, PMIC_RG_AUDSPAREVMIC_MASK,
	 PMIC_RG_AUDSPAREVMIC_SHIFT},
	{PMIC_RG_AUDPWDBMICBIAS0, PMIC_RG_AUDPWDBMICBIAS0_ADDR,
	 PMIC_RG_AUDPWDBMICBIAS0_MASK, PMIC_RG_AUDPWDBMICBIAS0_SHIFT},
	{PMIC_RG_AUDMICBIAS0DCSWPEN, PMIC_RG_AUDMICBIAS0DCSWPEN_ADDR,
	 PMIC_RG_AUDMICBIAS0DCSWPEN_MASK, PMIC_RG_AUDMICBIAS0DCSWPEN_SHIFT},
	{PMIC_RG_AUDMICBIAS0DCSWNEN, PMIC_RG_AUDMICBIAS0DCSWNEN_ADDR,
	 PMIC_RG_AUDMICBIAS0DCSWNEN_MASK, PMIC_RG_AUDMICBIAS0DCSWNEN_SHIFT},
	{PMIC_RG_AUDMICBIAS0BYPASSEN, PMIC_RG_AUDMICBIAS0BYPASSEN_ADDR,
	 PMIC_RG_AUDMICBIAS0BYPASSEN_MASK, PMIC_RG_AUDMICBIAS0BYPASSEN_SHIFT},
	{PMIC_RG_AUDPWDBMICBIAS1, PMIC_RG_AUDPWDBMICBIAS1_ADDR,
	 PMIC_RG_AUDPWDBMICBIAS1_MASK, PMIC_RG_AUDPWDBMICBIAS1_SHIFT},
	{PMIC_RG_AUDMICBIAS1DCSWPEN, PMIC_RG_AUDMICBIAS1DCSWPEN_ADDR,
	 PMIC_RG_AUDMICBIAS1DCSWPEN_MASK, PMIC_RG_AUDMICBIAS1DCSWPEN_SHIFT},
	{PMIC_RG_AUDMICBIAS1DCSWNEN, PMIC_RG_AUDMICBIAS1DCSWNEN_ADDR,
	 PMIC_RG_AUDMICBIAS1DCSWNEN_MASK, PMIC_RG_AUDMICBIAS1DCSWNEN_SHIFT},
	{PMIC_RG_AUDMICBIAS1BYPASSEN, PMIC_RG_AUDMICBIAS1BYPASSEN_ADDR,
	 PMIC_RG_AUDMICBIAS1BYPASSEN_MASK, PMIC_RG_AUDMICBIAS1BYPASSEN_SHIFT},
	{PMIC_RG_AUDMICBIASVREF, PMIC_RG_AUDMICBIASVREF_ADDR,
	 PMIC_RG_AUDMICBIASVREF_MASK, PMIC_RG_AUDMICBIASVREF_SHIFT},
	{PMIC_RG_AUDMICBIASLOWPEN, PMIC_RG_AUDMICBIASLOWPEN_ADDR,
	 PMIC_RG_AUDMICBIASLOWPEN_MASK, PMIC_RG_AUDMICBIASLOWPEN_SHIFT},
	{PMIC_RG_BANDGAPGEN, PMIC_RG_BANDGAPGEN_ADDR, PMIC_RG_BANDGAPGEN_MASK,
	 PMIC_RG_BANDGAPGEN_SHIFT},
	{PMIC_RG_AUDPREAMPLGAIN, PMIC_RG_AUDPREAMPLGAIN_ADDR,
	 PMIC_RG_AUDPREAMPLGAIN_MASK, PMIC_RG_AUDPREAMPLGAIN_SHIFT},
	{PMIC_RG_AUDPREAMPRGAIN, PMIC_RG_AUDPREAMPRGAIN_ADDR,
	 PMIC_RG_AUDPREAMPRGAIN_MASK, PMIC_RG_AUDPREAMPRGAIN_SHIFT},
	{PMIC_RG_DIVCKS_CHG, PMIC_RG_DIVCKS_CHG_ADDR, PMIC_RG_DIVCKS_CHG_MASK,
	 PMIC_RG_DIVCKS_CHG_SHIFT},
	{PMIC_RG_DIVCKS_ON, PMIC_RG_DIVCKS_ON_ADDR, PMIC_RG_DIVCKS_ON_MASK,
	 PMIC_RG_DIVCKS_ON_SHIFT},
	{PMIC_RG_DIVCKS_PRG, PMIC_RG_DIVCKS_PRG_ADDR, PMIC_RG_DIVCKS_PRG_MASK,
	 PMIC_RG_DIVCKS_PRG_SHIFT},
	{PMIC_RG_DIVCKS_PWD_NCP, PMIC_RG_DIVCKS_PWD_NCP_ADDR,
	 PMIC_RG_DIVCKS_PWD_NCP_MASK, PMIC_RG_DIVCKS_PWD_NCP_SHIFT},
	{PMIC_RG_DIVCKS_PWD_NCP_ST_SEL, PMIC_RG_DIVCKS_PWD_NCP_ST_SEL_ADDR,
	 PMIC_RG_DIVCKS_PWD_NCP_ST_SEL_MASK, PMIC_RG_DIVCKS_PWD_NCP_ST_SEL_SHIFT},
	{PMIC_XO_EXTBUF1_MODE, PMIC_XO_EXTBUF1_MODE_ADDR, PMIC_XO_EXTBUF1_MODE_MASK,
	 PMIC_XO_EXTBUF1_MODE_SHIFT},
	{PMIC_XO_EXTBUF1_EN_M, PMIC_XO_EXTBUF1_EN_M_ADDR, PMIC_XO_EXTBUF1_EN_M_MASK,
	 PMIC_XO_EXTBUF1_EN_M_SHIFT},
	{PMIC_XO_EXTBUF2_MODE, PMIC_XO_EXTBUF2_MODE_ADDR, PMIC_XO_EXTBUF2_MODE_MASK,
	 PMIC_XO_EXTBUF2_MODE_SHIFT},
	{PMIC_XO_EXTBUF2_EN_M, PMIC_XO_EXTBUF2_EN_M_ADDR, PMIC_XO_EXTBUF2_EN_M_MASK,
	 PMIC_XO_EXTBUF2_EN_M_SHIFT},
	{PMIC_XO_EXTBUF3_MODE, PMIC_XO_EXTBUF3_MODE_ADDR, PMIC_XO_EXTBUF3_MODE_MASK,
	 PMIC_XO_EXTBUF3_MODE_SHIFT},
	{PMIC_XO_EXTBUF3_EN_M, PMIC_XO_EXTBUF3_EN_M_ADDR, PMIC_XO_EXTBUF3_EN_M_MASK,
	 PMIC_XO_EXTBUF3_EN_M_SHIFT},
	{PMIC_XO_EXTBUF4_MODE, PMIC_XO_EXTBUF4_MODE_ADDR, PMIC_XO_EXTBUF4_MODE_MASK,
	 PMIC_XO_EXTBUF4_MODE_SHIFT},
	{PMIC_XO_EXTBUF4_EN_M, PMIC_XO_EXTBUF4_EN_M_ADDR, PMIC_XO_EXTBUF4_EN_M_MASK,
	 PMIC_XO_EXTBUF4_EN_M_SHIFT},
	{PMIC_XO_BB_LPM_EN, PMIC_XO_BB_LPM_EN_ADDR, PMIC_XO_BB_LPM_EN_MASK,
	 PMIC_XO_BB_LPM_EN_SHIFT},
	{PMIC_XO_ENBB_MAN, PMIC_XO_ENBB_MAN_ADDR, PMIC_XO_ENBB_MAN_MASK,
	 PMIC_XO_ENBB_MAN_SHIFT},
	{PMIC_XO_ENBB_EN_M, PMIC_XO_ENBB_EN_M_ADDR, PMIC_XO_ENBB_EN_M_MASK,
	 PMIC_XO_ENBB_EN_M_SHIFT},
	{PMIC_XO_CLKSEL_MAN, PMIC_XO_CLKSEL_MAN_ADDR, PMIC_XO_CLKSEL_MAN_MASK,
	 PMIC_XO_CLKSEL_MAN_SHIFT},
	{PMIC_DCXO_CW00_SET, PMIC_DCXO_CW00_SET_ADDR, PMIC_DCXO_CW00_SET_MASK,
	 PMIC_DCXO_CW00_SET_SHIFT},
	{PMIC_DCXO_CW00_CLR, PMIC_DCXO_CW00_CLR_ADDR, PMIC_DCXO_CW00_CLR_MASK,
	 PMIC_DCXO_CW00_CLR_SHIFT},
	{PMIC_XO_CLKSEL_EN_M, PMIC_XO_CLKSEL_EN_M_ADDR, PMIC_XO_CLKSEL_EN_M_MASK,
	 PMIC_XO_CLKSEL_EN_M_SHIFT},
	{PMIC_XO_EXTBUF1_CKG_MAN, PMIC_XO_EXTBUF1_CKG_MAN_ADDR,
	 PMIC_XO_EXTBUF1_CKG_MAN_MASK, PMIC_XO_EXTBUF1_CKG_MAN_SHIFT},
	{PMIC_XO_EXTBUF1_CKG_EN_M, PMIC_XO_EXTBUF1_CKG_EN_M_ADDR,
	 PMIC_XO_EXTBUF1_CKG_EN_M_MASK, PMIC_XO_EXTBUF1_CKG_EN_M_SHIFT},
	{PMIC_XO_EXTBUF2_CKG_MAN, PMIC_XO_EXTBUF2_CKG_MAN_ADDR,
	 PMIC_XO_EXTBUF2_CKG_MAN_MASK, PMIC_XO_EXTBUF2_CKG_MAN_SHIFT},
	{PMIC_XO_EXTBUF2_CKG_EN_M, PMIC_XO_EXTBUF2_CKG_EN_M_ADDR,
	 PMIC_XO_EXTBUF2_CKG_EN_M_MASK, PMIC_XO_EXTBUF2_CKG_EN_M_SHIFT},
	{PMIC_XO_EXTBUF3_CKG_MAN, PMIC_XO_EXTBUF3_CKG_MAN_ADDR,
	 PMIC_XO_EXTBUF3_CKG_MAN_MASK, PMIC_XO_EXTBUF3_CKG_MAN_SHIFT},
	{PMIC_XO_EXTBUF3_CKG_EN_M, PMIC_XO_EXTBUF3_CKG_EN_M_ADDR,
	 PMIC_XO_EXTBUF3_CKG_EN_M_MASK, PMIC_XO_EXTBUF3_CKG_EN_M_SHIFT},
	{PMIC_XO_EXTBUF4_CKG_MAN, PMIC_XO_EXTBUF4_CKG_MAN_ADDR,
	 PMIC_XO_EXTBUF4_CKG_MAN_MASK, PMIC_XO_EXTBUF4_CKG_MAN_SHIFT},
	{PMIC_XO_EXTBUF4_CKG_EN_M, PMIC_XO_EXTBUF4_CKG_EN_M_ADDR,
	 PMIC_XO_EXTBUF4_CKG_EN_M_MASK, PMIC_XO_EXTBUF4_CKG_EN_M_SHIFT},
	{PMIC_XO_INTBUF_MAN, PMIC_XO_INTBUF_MAN_ADDR, PMIC_XO_INTBUF_MAN_MASK,
	 PMIC_XO_INTBUF_MAN_SHIFT},
	{PMIC_XO_PBUF_EN_M, PMIC_XO_PBUF_EN_M_ADDR, PMIC_XO_PBUF_EN_M_MASK,
	 PMIC_XO_PBUF_EN_M_SHIFT},
	{PMIC_XO_IBUF_EN_M, PMIC_XO_IBUF_EN_M_ADDR, PMIC_XO_IBUF_EN_M_MASK,
	 PMIC_XO_IBUF_EN_M_SHIFT},
	{PMIC_XO_LPMBUF_MAN, PMIC_XO_LPMBUF_MAN_ADDR, PMIC_XO_LPMBUF_MAN_MASK,
	 PMIC_XO_LPMBUF_MAN_SHIFT},
	{PMIC_XO_LPM_PREBUF_EN_M, PMIC_XO_LPM_PREBUF_EN_M_ADDR,
	 PMIC_XO_LPM_PREBUF_EN_M_MASK, PMIC_XO_LPM_PREBUF_EN_M_SHIFT},
	{PMIC_XO_LPBUF_EN_M, PMIC_XO_LPBUF_EN_M_ADDR, PMIC_XO_LPBUF_EN_M_MASK,
	 PMIC_XO_LPBUF_EN_M_SHIFT},
	{PMIC_XO_AUDIO_EN_M, PMIC_XO_AUDIO_EN_M_ADDR, PMIC_XO_AUDIO_EN_M_MASK,
	 PMIC_XO_AUDIO_EN_M_SHIFT},
	{PMIC_XO_EN32K_MAN, PMIC_XO_EN32K_MAN_ADDR, PMIC_XO_EN32K_MAN_MASK,
	 PMIC_XO_EN32K_MAN_SHIFT},
	{PMIC_XO_EN32K_M, PMIC_XO_EN32K_M_ADDR, PMIC_XO_EN32K_M_MASK,
	 PMIC_XO_EN32K_M_SHIFT},
	{PMIC_XO_XMODE_MAN, PMIC_XO_XMODE_MAN_ADDR, PMIC_XO_XMODE_MAN_MASK,
	 PMIC_XO_XMODE_MAN_SHIFT},
	{PMIC_XO_XMODE_M, PMIC_XO_XMODE_M_ADDR, PMIC_XO_XMODE_M_MASK,
	 PMIC_XO_XMODE_M_SHIFT},
	{PMIC_XO_STRUP_MODE, PMIC_XO_STRUP_MODE_ADDR, PMIC_XO_STRUP_MODE_MASK,
	 PMIC_XO_STRUP_MODE_SHIFT},
	{PMIC_XO_AAC_FPM_TIME, PMIC_XO_AAC_FPM_TIME_ADDR, PMIC_XO_AAC_FPM_TIME_MASK,
	 PMIC_XO_AAC_FPM_TIME_SHIFT},
	{PMIC_XO_AAC_MODE_LPM, PMIC_XO_AAC_MODE_LPM_ADDR, PMIC_XO_AAC_MODE_LPM_MASK,
	 PMIC_XO_AAC_MODE_LPM_SHIFT},
	{PMIC_XO_AAC_MODE_FPM, PMIC_XO_AAC_MODE_FPM_ADDR, PMIC_XO_AAC_MODE_FPM_MASK,
	 PMIC_XO_AAC_MODE_FPM_SHIFT},
	{PMIC_XO_EN26M_OFFSQ_EN, PMIC_XO_EN26M_OFFSQ_EN_ADDR,
	 PMIC_XO_EN26M_OFFSQ_EN_MASK, PMIC_XO_EN26M_OFFSQ_EN_SHIFT},
	{PMIC_XO_LDOCAL_EN, PMIC_XO_LDOCAL_EN_ADDR, PMIC_XO_LDOCAL_EN_MASK,
	 PMIC_XO_LDOCAL_EN_SHIFT},
	{PMIC_XO_CBANK_SYNC_DYN, PMIC_XO_CBANK_SYNC_DYN_ADDR,
	 PMIC_XO_CBANK_SYNC_DYN_MASK, PMIC_XO_CBANK_SYNC_DYN_SHIFT},
	{PMIC_XO_26MLP_MAN_EN, PMIC_XO_26MLP_MAN_EN_ADDR, PMIC_XO_26MLP_MAN_EN_MASK,
	 PMIC_XO_26MLP_MAN_EN_SHIFT},
	{PMIC_XO_OPMODE_MAN, PMIC_XO_OPMODE_MAN_ADDR, PMIC_XO_OPMODE_MAN_MASK,
	 PMIC_XO_OPMODE_MAN_SHIFT},
	{PMIC_XO_BUFLDO13_VSET_M, PMIC_XO_BUFLDO13_VSET_M_ADDR,
	 PMIC_XO_BUFLDO13_VSET_M_MASK, PMIC_XO_BUFLDO13_VSET_M_SHIFT},
	{PMIC_XO_RESERVED0, PMIC_XO_RESERVED0_ADDR, PMIC_XO_RESERVED0_MASK,
	 PMIC_XO_RESERVED0_SHIFT},
	{PMIC_XO_LPM_ISEL_MAN, PMIC_XO_LPM_ISEL_MAN_ADDR, PMIC_XO_LPM_ISEL_MAN_MASK,
	 PMIC_XO_LPM_ISEL_MAN_SHIFT},
	{PMIC_XO_FPM_ISEL_MAN, PMIC_XO_FPM_ISEL_MAN_ADDR, PMIC_XO_FPM_ISEL_MAN_MASK,
	 PMIC_XO_FPM_ISEL_MAN_SHIFT},
	{PMIC_XO_CDAC_FPM, PMIC_XO_CDAC_FPM_ADDR, PMIC_XO_CDAC_FPM_MASK,
	 PMIC_XO_CDAC_FPM_SHIFT},
	{PMIC_XO_CDAC_LPM, PMIC_XO_CDAC_LPM_ADDR, PMIC_XO_CDAC_LPM_MASK,
	 PMIC_XO_CDAC_LPM_SHIFT},
	{PMIC_XO_32KDIV_NFRAC_FPM, PMIC_XO_32KDIV_NFRAC_FPM_ADDR,
	 PMIC_XO_32KDIV_NFRAC_FPM_MASK, PMIC_XO_32KDIV_NFRAC_FPM_SHIFT},
	{PMIC_XO_COFST_FPM, PMIC_XO_COFST_FPM_ADDR, PMIC_XO_COFST_FPM_MASK,
	 PMIC_XO_COFST_FPM_SHIFT},
	{PMIC_XO_32KDIV_NFRAC_LPM, PMIC_XO_32KDIV_NFRAC_LPM_ADDR,
	 PMIC_XO_32KDIV_NFRAC_LPM_MASK, PMIC_XO_32KDIV_NFRAC_LPM_SHIFT},
	{PMIC_XO_COFST_LPM, PMIC_XO_COFST_LPM_ADDR, PMIC_XO_COFST_LPM_MASK,
	 PMIC_XO_COFST_LPM_SHIFT},
	{PMIC_XO_CORE_MAN, PMIC_XO_CORE_MAN_ADDR, PMIC_XO_CORE_MAN_MASK,
	 PMIC_XO_CORE_MAN_SHIFT},
	{PMIC_XO_CORE_EN_M, PMIC_XO_CORE_EN_M_ADDR, PMIC_XO_CORE_EN_M_MASK,
	 PMIC_XO_CORE_EN_M_SHIFT},
	{PMIC_XO_CORE_TURBO_EN_M, PMIC_XO_CORE_TURBO_EN_M_ADDR,
	 PMIC_XO_CORE_TURBO_EN_M_MASK, PMIC_XO_CORE_TURBO_EN_M_SHIFT},
	{PMIC_XO_CORE_AAC_EN_M, PMIC_XO_CORE_AAC_EN_M_ADDR,
	 PMIC_XO_CORE_AAC_EN_M_MASK, PMIC_XO_CORE_AAC_EN_M_SHIFT},
	{PMIC_XO_STARTUP_EN_M, PMIC_XO_STARTUP_EN_M_ADDR, PMIC_XO_STARTUP_EN_M_MASK,
	 PMIC_XO_STARTUP_EN_M_SHIFT},
	{PMIC_XO_CORE_VBFPM_EN_M, PMIC_XO_CORE_VBFPM_EN_M_ADDR,
	 PMIC_XO_CORE_VBFPM_EN_M_MASK, PMIC_XO_CORE_VBFPM_EN_M_SHIFT},
	{PMIC_XO_CORE_VBLPM_EN_M, PMIC_XO_CORE_VBLPM_EN_M_ADDR,
	 PMIC_XO_CORE_VBLPM_EN_M_MASK, PMIC_XO_CORE_VBLPM_EN_M_SHIFT},
	{PMIC_XO_LPMBIAS_EN_M, PMIC_XO_LPMBIAS_EN_M_ADDR, PMIC_XO_LPMBIAS_EN_M_MASK,
	 PMIC_XO_LPMBIAS_EN_M_SHIFT},
	{PMIC_XO_VTCGEN_EN_M, PMIC_XO_VTCGEN_EN_M_ADDR, PMIC_XO_VTCGEN_EN_M_MASK,
	 PMIC_XO_VTCGEN_EN_M_SHIFT},
	{PMIC_XO_IAAC_COMP_EN_M, PMIC_XO_IAAC_COMP_EN_M_ADDR,
	 PMIC_XO_IAAC_COMP_EN_M_MASK, PMIC_XO_IAAC_COMP_EN_M_SHIFT},
	{PMIC_XO_IFPM_COMP_EN_M, PMIC_XO_IFPM_COMP_EN_M_ADDR,
	 PMIC_XO_IFPM_COMP_EN_M_MASK, PMIC_XO_IFPM_COMP_EN_M_SHIFT},
	{PMIC_XO_ILPM_COMP_EN_M, PMIC_XO_ILPM_COMP_EN_M_ADDR,
	 PMIC_XO_ILPM_COMP_EN_M_MASK, PMIC_XO_ILPM_COMP_EN_M_SHIFT},
	{PMIC_XO_CORE_BYPCAS_FPM, PMIC_XO_CORE_BYPCAS_FPM_ADDR,
	 PMIC_XO_CORE_BYPCAS_FPM_MASK, PMIC_XO_CORE_BYPCAS_FPM_SHIFT},
	{PMIC_XO_CORE_GMX2_FPM, PMIC_XO_CORE_GMX2_FPM_ADDR,
	 PMIC_XO_CORE_GMX2_FPM_MASK, PMIC_XO_CORE_GMX2_FPM_SHIFT},
	{PMIC_XO_CORE_IDAC_FPM, PMIC_XO_CORE_IDAC_FPM_ADDR,
	 PMIC_XO_CORE_IDAC_FPM_MASK, PMIC_XO_CORE_IDAC_FPM_SHIFT},
	{PMIC_XO_AAC_COMP_MAN, PMIC_XO_AAC_COMP_MAN_ADDR, PMIC_XO_AAC_COMP_MAN_MASK,
	 PMIC_XO_AAC_COMP_MAN_SHIFT},
	{PMIC_XO_AAC_EN_M, PMIC_XO_AAC_EN_M_ADDR, PMIC_XO_AAC_EN_M_MASK,
	 PMIC_XO_AAC_EN_M_SHIFT},
	{PMIC_XO_AAC_MONEN_M, PMIC_XO_AAC_MONEN_M_ADDR, PMIC_XO_AAC_MONEN_M_MASK,
	 PMIC_XO_AAC_MONEN_M_SHIFT},
	{PMIC_XO_COMP_EN_M, PMIC_XO_COMP_EN_M_ADDR, PMIC_XO_COMP_EN_M_MASK,
	 PMIC_XO_COMP_EN_M_SHIFT},
	{PMIC_XO_COMP_TSTEN_M, PMIC_XO_COMP_TSTEN_M_ADDR, PMIC_XO_COMP_TSTEN_M_MASK,
	 PMIC_XO_COMP_TSTEN_M_SHIFT},
	{PMIC_XO_AAC_HV_FPM, PMIC_XO_AAC_HV_FPM_ADDR, PMIC_XO_AAC_HV_FPM_MASK,
	 PMIC_XO_AAC_HV_FPM_SHIFT},
	{PMIC_XO_AAC_IBIAS_FPM, PMIC_XO_AAC_IBIAS_FPM_ADDR,
	 PMIC_XO_AAC_IBIAS_FPM_MASK, PMIC_XO_AAC_IBIAS_FPM_SHIFT},
	{PMIC_XO_AAC_VOFST_FPM, PMIC_XO_AAC_VOFST_FPM_ADDR,
	 PMIC_XO_AAC_VOFST_FPM_MASK, PMIC_XO_AAC_VOFST_FPM_SHIFT},
	{PMIC_XO_AAC_COMP_HV_FPM, PMIC_XO_AAC_COMP_HV_FPM_ADDR,
	 PMIC_XO_AAC_COMP_HV_FPM_MASK, PMIC_XO_AAC_COMP_HV_FPM_SHIFT},
	{PMIC_XO_AAC_VSEL_FPM, PMIC_XO_AAC_VSEL_FPM_ADDR, PMIC_XO_AAC_VSEL_FPM_MASK,
	 PMIC_XO_AAC_VSEL_FPM_SHIFT},
	{PMIC_XO_AAC_COMP_POL, PMIC_XO_AAC_COMP_POL_ADDR, PMIC_XO_AAC_COMP_POL_MASK,
	 PMIC_XO_AAC_COMP_POL_SHIFT},
	{PMIC_XO_CORE_BYPCAS_LPM, PMIC_XO_CORE_BYPCAS_LPM_ADDR,
	 PMIC_XO_CORE_BYPCAS_LPM_MASK, PMIC_XO_CORE_BYPCAS_LPM_SHIFT},
	{PMIC_XO_CORE_GMX2_LPM, PMIC_XO_CORE_GMX2_LPM_ADDR,
	 PMIC_XO_CORE_GMX2_LPM_MASK, PMIC_XO_CORE_GMX2_LPM_SHIFT},
	{PMIC_XO_CORE_IDAC_LPM, PMIC_XO_CORE_IDAC_LPM_ADDR,
	 PMIC_XO_CORE_IDAC_LPM_MASK, PMIC_XO_CORE_IDAC_LPM_SHIFT},
	{PMIC_XO_AAC_COMP_HV_LPM, PMIC_XO_AAC_COMP_HV_LPM_ADDR,
	 PMIC_XO_AAC_COMP_HV_LPM_MASK, PMIC_XO_AAC_COMP_HV_LPM_SHIFT},
	{PMIC_XO_AAC_VSEL_LPM, PMIC_XO_AAC_VSEL_LPM_ADDR, PMIC_XO_AAC_VSEL_LPM_MASK,
	 PMIC_XO_AAC_VSEL_LPM_SHIFT},
	{PMIC_XO_AAC_HV_LPM, PMIC_XO_AAC_HV_LPM_ADDR, PMIC_XO_AAC_HV_LPM_MASK,
	 PMIC_XO_AAC_HV_LPM_SHIFT},
	{PMIC_XO_AAC_IBIAS_LPM, PMIC_XO_AAC_IBIAS_LPM_ADDR,
	 PMIC_XO_AAC_IBIAS_LPM_MASK, PMIC_XO_AAC_IBIAS_LPM_SHIFT},
	{PMIC_XO_AAC_VOFST_LPM, PMIC_XO_AAC_VOFST_LPM_ADDR,
	 PMIC_XO_AAC_VOFST_LPM_MASK, PMIC_XO_AAC_VOFST_LPM_SHIFT},
	{PMIC_XO_AAC_FPM_SWEN, PMIC_XO_AAC_FPM_SWEN_ADDR, PMIC_XO_AAC_FPM_SWEN_MASK,
	 PMIC_XO_AAC_FPM_SWEN_SHIFT},
	{PMIC_XO_SWRST, PMIC_XO_SWRST_ADDR, PMIC_XO_SWRST_MASK,
	 PMIC_XO_SWRST_SHIFT},
	{PMIC_XO_32KDIV_SWRST, PMIC_XO_32KDIV_SWRST_ADDR, PMIC_XO_32KDIV_SWRST_MASK,
	 PMIC_XO_32KDIV_SWRST_SHIFT},
	{PMIC_XO_32KDIV_RATIO_MAN, PMIC_XO_32KDIV_RATIO_MAN_ADDR,
	 PMIC_XO_32KDIV_RATIO_MAN_MASK, PMIC_XO_32KDIV_RATIO_MAN_SHIFT},
	{PMIC_XO_32KDIV_TEST_EN, PMIC_XO_32KDIV_TEST_EN_ADDR,
	 PMIC_XO_32KDIV_TEST_EN_MASK, PMIC_XO_32KDIV_TEST_EN_SHIFT},
	{PMIC_XO_CBANK_SYNC_MAN, PMIC_XO_CBANK_SYNC_MAN_ADDR,
	 PMIC_XO_CBANK_SYNC_MAN_MASK, PMIC_XO_CBANK_SYNC_MAN_SHIFT},
	{PMIC_XO_CBANK_SYNC_EN_M, PMIC_XO_CBANK_SYNC_EN_M_ADDR,
	 PMIC_XO_CBANK_SYNC_EN_M_MASK, PMIC_XO_CBANK_SYNC_EN_M_SHIFT},
	{PMIC_XO_CTL_SYNC_MAN, PMIC_XO_CTL_SYNC_MAN_ADDR, PMIC_XO_CTL_SYNC_MAN_MASK,
	 PMIC_XO_CTL_SYNC_MAN_SHIFT},
	{PMIC_XO_CTL_SYNC_EN_M, PMIC_XO_CTL_SYNC_EN_M_ADDR,
	 PMIC_XO_CTL_SYNC_EN_M_MASK, PMIC_XO_CTL_SYNC_EN_M_SHIFT},
	{PMIC_XO_LDO_MAN, PMIC_XO_LDO_MAN_ADDR, PMIC_XO_LDO_MAN_MASK,
	 PMIC_XO_LDO_MAN_SHIFT},
	{PMIC_XO_LDOPBUF_EN_M, PMIC_XO_LDOPBUF_EN_M_ADDR, PMIC_XO_LDOPBUF_EN_M_MASK,
	 PMIC_XO_LDOPBUF_EN_M_SHIFT},
	{PMIC_XO_LDOPBUF_VSET_M, PMIC_XO_LDOPBUF_VSET_M_ADDR,
	 PMIC_XO_LDOPBUF_VSET_M_MASK, PMIC_XO_LDOPBUF_VSET_M_SHIFT},
	{PMIC_XO_LDOVTST_EN_M, PMIC_XO_LDOVTST_EN_M_ADDR, PMIC_XO_LDOVTST_EN_M_MASK,
	 PMIC_XO_LDOVTST_EN_M_SHIFT},
	{PMIC_XO_TEST_VCAL_EN_M, PMIC_XO_TEST_VCAL_EN_M_ADDR,
	 PMIC_XO_TEST_VCAL_EN_M_MASK, PMIC_XO_TEST_VCAL_EN_M_SHIFT},
	{PMIC_XO_VBIST_EN_M, PMIC_XO_VBIST_EN_M_ADDR, PMIC_XO_VBIST_EN_M_MASK,
	 PMIC_XO_VBIST_EN_M_SHIFT},
	{PMIC_XO_VTEST_SEL_MUX, PMIC_XO_VTEST_SEL_MUX_ADDR,
	 PMIC_XO_VTEST_SEL_MUX_MASK, PMIC_XO_VTEST_SEL_MUX_SHIFT},
	{PMIC_RG_XO_CORE_OSCTD, PMIC_RG_XO_CORE_OSCTD_ADDR,
	 PMIC_RG_XO_CORE_OSCTD_MASK, PMIC_RG_XO_CORE_OSCTD_SHIFT},
	{PMIC_RG_XO_THADC_EN, PMIC_RG_XO_THADC_EN_ADDR, PMIC_RG_XO_THADC_EN_MASK,
	 PMIC_RG_XO_THADC_EN_SHIFT},
	{PMIC_RG_XO_SYNC_CKPOL, PMIC_RG_XO_SYNC_CKPOL_ADDR,
	 PMIC_RG_XO_SYNC_CKPOL_MASK, PMIC_RG_XO_SYNC_CKPOL_SHIFT},
	{PMIC_RG_XO_CBANK_POL, PMIC_RG_XO_CBANK_POL_ADDR, PMIC_RG_XO_CBANK_POL_MASK,
	 PMIC_RG_XO_CBANK_POL_SHIFT},
	{PMIC_RG_XO_CBANK_SYNC_BYP, PMIC_RG_XO_CBANK_SYNC_BYP_ADDR,
	 PMIC_RG_XO_CBANK_SYNC_BYP_MASK, PMIC_RG_XO_CBANK_SYNC_BYP_SHIFT},
	{PMIC_RG_XO_CTL_POL, PMIC_RG_XO_CTL_POL_ADDR, PMIC_RG_XO_CTL_POL_MASK,
	 PMIC_RG_XO_CTL_POL_SHIFT},
	{PMIC_RG_XO_CTL_SYNC_BYP, PMIC_RG_XO_CTL_SYNC_BYP_ADDR,
	 PMIC_RG_XO_CTL_SYNC_BYP_MASK, PMIC_RG_XO_CTL_SYNC_BYP_SHIFT},
	{PMIC_RG_XO_LPBUF_INV, PMIC_RG_XO_LPBUF_INV_ADDR, PMIC_RG_XO_LPBUF_INV_MASK,
	 PMIC_RG_XO_LPBUF_INV_SHIFT},
	{PMIC_RG_XO_LDOPBUF_BYP, PMIC_RG_XO_LDOPBUF_BYP_ADDR,
	 PMIC_RG_XO_LDOPBUF_BYP_MASK, PMIC_RG_XO_LDOPBUF_BYP_SHIFT},
	{PMIC_RG_XO_LDOPBUF_ENCL, PMIC_RG_XO_LDOPBUF_ENCL_ADDR,
	 PMIC_RG_XO_LDOPBUF_ENCL_MASK, PMIC_RG_XO_LDOPBUF_ENCL_SHIFT},
	{PMIC_RG_XO_VGBIAS_VSET, PMIC_RG_XO_VGBIAS_VSET_ADDR,
	 PMIC_RG_XO_VGBIAS_VSET_MASK, PMIC_RG_XO_VGBIAS_VSET_SHIFT},
	{PMIC_RG_XO_PBUF_ISET, PMIC_RG_XO_PBUF_ISET_ADDR, PMIC_RG_XO_PBUF_ISET_MASK,
	 PMIC_RG_XO_PBUF_ISET_SHIFT},
	{PMIC_RG_XO_IBUF_ISET, PMIC_RG_XO_IBUF_ISET_ADDR, PMIC_RG_XO_IBUF_ISET_MASK,
	 PMIC_RG_XO_IBUF_ISET_SHIFT},
	{PMIC_RG_XO_BUFLDO13_ENCL, PMIC_RG_XO_BUFLDO13_ENCL_ADDR,
	 PMIC_RG_XO_BUFLDO13_ENCL_MASK, PMIC_RG_XO_BUFLDO13_ENCL_SHIFT},
	{PMIC_RG_XO_BUFLDO13_IBX2, PMIC_RG_XO_BUFLDO13_IBX2_ADDR,
	 PMIC_RG_XO_BUFLDO13_IBX2_MASK, PMIC_RG_XO_BUFLDO13_IBX2_SHIFT},
	{PMIC_RG_XO_BUFLDO13_IX2, PMIC_RG_XO_BUFLDO13_IX2_ADDR,
	 PMIC_RG_XO_BUFLDO13_IX2_MASK, PMIC_RG_XO_BUFLDO13_IX2_SHIFT},
	{PMIC_XO_RESERVED1, PMIC_XO_RESERVED1_ADDR, PMIC_XO_RESERVED1_MASK,
	 PMIC_XO_RESERVED1_SHIFT},
	{PMIC_RG_XO_BUFLDO24_ENCL, PMIC_RG_XO_BUFLDO24_ENCL_ADDR,
	 PMIC_RG_XO_BUFLDO24_ENCL_MASK, PMIC_RG_XO_BUFLDO24_ENCL_SHIFT},
	{PMIC_RG_XO_BUFLDO24_IBX2, PMIC_RG_XO_BUFLDO24_IBX2_ADDR,
	 PMIC_RG_XO_BUFLDO24_IBX2_MASK, PMIC_RG_XO_BUFLDO24_IBX2_SHIFT},
	{PMIC_XO_BUFLDO24_VSET_M, PMIC_XO_BUFLDO24_VSET_M_ADDR,
	 PMIC_XO_BUFLDO24_VSET_M_MASK, PMIC_XO_BUFLDO24_VSET_M_SHIFT},
	{PMIC_RG_XO_EXTBUF1_HD, PMIC_RG_XO_EXTBUF1_HD_ADDR,
	 PMIC_RG_XO_EXTBUF1_HD_MASK, PMIC_RG_XO_EXTBUF1_HD_SHIFT},
	{PMIC_RG_XO_EXTBUF1_ISET, PMIC_RG_XO_EXTBUF1_ISET_ADDR,
	 PMIC_RG_XO_EXTBUF1_ISET_MASK, PMIC_RG_XO_EXTBUF1_ISET_SHIFT},
	{PMIC_RG_XO_EXTBUF2_HD, PMIC_RG_XO_EXTBUF2_HD_ADDR,
	 PMIC_RG_XO_EXTBUF2_HD_MASK, PMIC_RG_XO_EXTBUF2_HD_SHIFT},
	{PMIC_RG_XO_EXTBUF2_ISET, PMIC_RG_XO_EXTBUF2_ISET_ADDR,
	 PMIC_RG_XO_EXTBUF2_ISET_MASK, PMIC_RG_XO_EXTBUF2_ISET_SHIFT},
	{PMIC_RG_XO_EXTBUF3_HD, PMIC_RG_XO_EXTBUF3_HD_ADDR,
	 PMIC_RG_XO_EXTBUF3_HD_MASK, PMIC_RG_XO_EXTBUF3_HD_SHIFT},
	{PMIC_RG_XO_EXTBUF3_ISET, PMIC_RG_XO_EXTBUF3_ISET_ADDR,
	 PMIC_RG_XO_EXTBUF3_ISET_MASK, PMIC_RG_XO_EXTBUF3_ISET_SHIFT},
	{PMIC_RG_XO_EXTBUF4_HD, PMIC_RG_XO_EXTBUF4_HD_ADDR,
	 PMIC_RG_XO_EXTBUF4_HD_MASK, PMIC_RG_XO_EXTBUF4_HD_SHIFT},
	{PMIC_RG_XO_EXTBUF4_ISET, PMIC_RG_XO_EXTBUF4_ISET_ADDR,
	 PMIC_RG_XO_EXTBUF4_ISET_MASK, PMIC_RG_XO_EXTBUF4_ISET_SHIFT},
	{PMIC_RG_XO_LPM_PREBUF_ISET, PMIC_RG_XO_LPM_PREBUF_ISET_ADDR,
	 PMIC_RG_XO_LPM_PREBUF_ISET_MASK, PMIC_RG_XO_LPM_PREBUF_ISET_SHIFT},
	{PMIC_RG_XO_AUDIO_ATTEN, PMIC_RG_XO_AUDIO_ATTEN_ADDR,
	 PMIC_RG_XO_AUDIO_ATTEN_MASK, PMIC_RG_XO_AUDIO_ATTEN_SHIFT},
	{PMIC_RG_XO_AUDIO_ISET, PMIC_RG_XO_AUDIO_ISET_ADDR,
	 PMIC_RG_XO_AUDIO_ISET_MASK, PMIC_RG_XO_AUDIO_ISET_SHIFT},
	{PMIC_XO_EXTBUF4_CLKSEL_MAN, PMIC_XO_EXTBUF4_CLKSEL_MAN_ADDR,
	 PMIC_XO_EXTBUF4_CLKSEL_MAN_MASK, PMIC_XO_EXTBUF4_CLKSEL_MAN_SHIFT},
	{PMIC_RG_XO_RESERVED0, PMIC_RG_XO_RESERVED0_ADDR, PMIC_RG_XO_RESERVED0_MASK,
	 PMIC_RG_XO_RESERVED0_SHIFT},
	{PMIC_XO_VIO18PG_BUFEN, PMIC_XO_VIO18PG_BUFEN_ADDR,
	 PMIC_XO_VIO18PG_BUFEN_MASK, PMIC_XO_VIO18PG_BUFEN_SHIFT},
	{PMIC_RG_XO_RESERVED1, PMIC_RG_XO_RESERVED1_ADDR, PMIC_RG_XO_RESERVED1_MASK,
	 PMIC_RG_XO_RESERVED1_SHIFT},
	{PMIC_XO_CAL_EN_MAN, PMIC_XO_CAL_EN_MAN_ADDR, PMIC_XO_CAL_EN_MAN_MASK,
	 PMIC_XO_CAL_EN_MAN_SHIFT},
	{PMIC_XO_CAL_EN_M, PMIC_XO_CAL_EN_M_ADDR, PMIC_XO_CAL_EN_M_MASK,
	 PMIC_XO_CAL_EN_M_SHIFT},
	{PMIC_XO_STATIC_AUXOUT_SEL, PMIC_XO_STATIC_AUXOUT_SEL_ADDR,
	 PMIC_XO_STATIC_AUXOUT_SEL_MASK, PMIC_XO_STATIC_AUXOUT_SEL_SHIFT},
	{PMIC_XO_AUXOUT_SEL, PMIC_XO_AUXOUT_SEL_ADDR, PMIC_XO_AUXOUT_SEL_MASK,
	 PMIC_XO_AUXOUT_SEL_SHIFT},
	{PMIC_XO_STATIC_AUXOUT, PMIC_XO_STATIC_AUXOUT_ADDR,
	 PMIC_XO_STATIC_AUXOUT_MASK, PMIC_XO_STATIC_AUXOUT_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH0, PMIC_AUXADC_ADC_OUT_CH0_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH0_MASK, PMIC_AUXADC_ADC_OUT_CH0_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH0, PMIC_AUXADC_ADC_RDY_CH0_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH0_MASK, PMIC_AUXADC_ADC_RDY_CH0_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH1, PMIC_AUXADC_ADC_OUT_CH1_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH1_MASK, PMIC_AUXADC_ADC_OUT_CH1_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH1, PMIC_AUXADC_ADC_RDY_CH1_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH1_MASK, PMIC_AUXADC_ADC_RDY_CH1_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH2, PMIC_AUXADC_ADC_OUT_CH2_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH2_MASK, PMIC_AUXADC_ADC_OUT_CH2_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH2, PMIC_AUXADC_ADC_RDY_CH2_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH2_MASK, PMIC_AUXADC_ADC_RDY_CH2_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH3, PMIC_AUXADC_ADC_OUT_CH3_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH3_MASK, PMIC_AUXADC_ADC_OUT_CH3_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH3, PMIC_AUXADC_ADC_RDY_CH3_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH3_MASK, PMIC_AUXADC_ADC_RDY_CH3_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH4, PMIC_AUXADC_ADC_OUT_CH4_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH4_MASK, PMIC_AUXADC_ADC_OUT_CH4_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH4, PMIC_AUXADC_ADC_RDY_CH4_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH4_MASK, PMIC_AUXADC_ADC_RDY_CH4_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH5, PMIC_AUXADC_ADC_OUT_CH5_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH5_MASK, PMIC_AUXADC_ADC_OUT_CH5_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH5, PMIC_AUXADC_ADC_RDY_CH5_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH5_MASK, PMIC_AUXADC_ADC_RDY_CH5_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH6, PMIC_AUXADC_ADC_OUT_CH6_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH6_MASK, PMIC_AUXADC_ADC_OUT_CH6_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH6, PMIC_AUXADC_ADC_RDY_CH6_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH6_MASK, PMIC_AUXADC_ADC_RDY_CH6_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH7, PMIC_AUXADC_ADC_OUT_CH7_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH7_MASK, PMIC_AUXADC_ADC_OUT_CH7_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH7, PMIC_AUXADC_ADC_RDY_CH7_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH7_MASK, PMIC_AUXADC_ADC_RDY_CH7_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH8, PMIC_AUXADC_ADC_OUT_CH8_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH8_MASK, PMIC_AUXADC_ADC_OUT_CH8_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH8, PMIC_AUXADC_ADC_RDY_CH8_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH8_MASK, PMIC_AUXADC_ADC_RDY_CH8_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH9, PMIC_AUXADC_ADC_OUT_CH9_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH9_MASK, PMIC_AUXADC_ADC_OUT_CH9_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH9, PMIC_AUXADC_ADC_RDY_CH9_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH9_MASK, PMIC_AUXADC_ADC_RDY_CH9_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH10, PMIC_AUXADC_ADC_OUT_CH10_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH10_MASK, PMIC_AUXADC_ADC_OUT_CH10_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH10, PMIC_AUXADC_ADC_RDY_CH10_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH10_MASK, PMIC_AUXADC_ADC_RDY_CH10_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH11, PMIC_AUXADC_ADC_OUT_CH11_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH11_MASK, PMIC_AUXADC_ADC_OUT_CH11_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH11, PMIC_AUXADC_ADC_RDY_CH11_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH11_MASK, PMIC_AUXADC_ADC_RDY_CH11_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH12_15, PMIC_AUXADC_ADC_OUT_CH12_15_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH12_15_MASK, PMIC_AUXADC_ADC_OUT_CH12_15_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH12_15, PMIC_AUXADC_ADC_RDY_CH12_15_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH12_15_MASK, PMIC_AUXADC_ADC_RDY_CH12_15_SHIFT},
	{PMIC_AUXADC_ADC_OUT_THR_HW, PMIC_AUXADC_ADC_OUT_THR_HW_ADDR,
	 PMIC_AUXADC_ADC_OUT_THR_HW_MASK, PMIC_AUXADC_ADC_OUT_THR_HW_SHIFT},
	{PMIC_AUXADC_ADC_RDY_THR_HW, PMIC_AUXADC_ADC_RDY_THR_HW_ADDR,
	 PMIC_AUXADC_ADC_RDY_THR_HW_MASK, PMIC_AUXADC_ADC_RDY_THR_HW_SHIFT},
	{PMIC_AUXADC_ADC_OUT_LBAT, PMIC_AUXADC_ADC_OUT_LBAT_ADDR,
	 PMIC_AUXADC_ADC_OUT_LBAT_MASK, PMIC_AUXADC_ADC_OUT_LBAT_SHIFT},
	{PMIC_AUXADC_ADC_RDY_LBAT, PMIC_AUXADC_ADC_RDY_LBAT_ADDR,
	 PMIC_AUXADC_ADC_RDY_LBAT_MASK, PMIC_AUXADC_ADC_RDY_LBAT_SHIFT},
	{PMIC_AUXADC_ADC_OUT_LBAT2, PMIC_AUXADC_ADC_OUT_LBAT2_ADDR,
	 PMIC_AUXADC_ADC_OUT_LBAT2_MASK, PMIC_AUXADC_ADC_OUT_LBAT2_SHIFT},
	{PMIC_AUXADC_ADC_RDY_LBAT2, PMIC_AUXADC_ADC_RDY_LBAT2_ADDR,
	 PMIC_AUXADC_ADC_RDY_LBAT2_MASK, PMIC_AUXADC_ADC_RDY_LBAT2_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH7_BY_GPS, PMIC_AUXADC_ADC_OUT_CH7_BY_GPS_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH7_BY_GPS_MASK, PMIC_AUXADC_ADC_OUT_CH7_BY_GPS_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH7_BY_GPS, PMIC_AUXADC_ADC_RDY_CH7_BY_GPS_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH7_BY_GPS_MASK, PMIC_AUXADC_ADC_RDY_CH7_BY_GPS_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH7_BY_MD, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH7_BY_MD, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH7_BY_AP, PMIC_AUXADC_ADC_OUT_CH7_BY_AP_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH7_BY_AP_MASK, PMIC_AUXADC_ADC_OUT_CH7_BY_AP_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH7_BY_AP, PMIC_AUXADC_ADC_RDY_CH7_BY_AP_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH7_BY_AP_MASK, PMIC_AUXADC_ADC_RDY_CH7_BY_AP_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH4_BY_MD, PMIC_AUXADC_ADC_OUT_CH4_BY_MD_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH4_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_CH4_BY_MD_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH4_BY_MD, PMIC_AUXADC_ADC_RDY_CH4_BY_MD_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH4_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_CH4_BY_MD_SHIFT},
	{PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR, PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR_ADDR,
	 PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR_MASK, PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR_SHIFT},
	{PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR, PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR_ADDR,
	 PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR_MASK, PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR_SHIFT},
	{PMIC_AUXADC_ADC_OUT_WAKEUP_SWCHR, PMIC_AUXADC_ADC_OUT_WAKEUP_SWCHR_ADDR,
	 PMIC_AUXADC_ADC_OUT_WAKEUP_SWCHR_MASK,
	 PMIC_AUXADC_ADC_OUT_WAKEUP_SWCHR_SHIFT},
	{PMIC_AUXADC_ADC_RDY_WAKEUP_SWCHR, PMIC_AUXADC_ADC_RDY_WAKEUP_SWCHR_ADDR,
	 PMIC_AUXADC_ADC_RDY_WAKEUP_SWCHR_MASK,
	 PMIC_AUXADC_ADC_RDY_WAKEUP_SWCHR_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH0_BY_MD, PMIC_AUXADC_ADC_OUT_CH0_BY_MD_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH0_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_CH0_BY_MD_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH0_BY_MD, PMIC_AUXADC_ADC_RDY_CH0_BY_MD_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH0_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_CH0_BY_MD_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH0_BY_AP, PMIC_AUXADC_ADC_OUT_CH0_BY_AP_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH0_BY_AP_MASK, PMIC_AUXADC_ADC_OUT_CH0_BY_AP_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH0_BY_AP, PMIC_AUXADC_ADC_RDY_CH0_BY_AP_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH0_BY_AP_MASK, PMIC_AUXADC_ADC_RDY_CH0_BY_AP_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH1_BY_MD, PMIC_AUXADC_ADC_OUT_CH1_BY_MD_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH1_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_CH1_BY_MD_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH1_BY_MD, PMIC_AUXADC_ADC_RDY_CH1_BY_MD_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH1_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_CH1_BY_MD_SHIFT},
	{PMIC_AUXADC_ADC_OUT_CH1_BY_AP, PMIC_AUXADC_ADC_OUT_CH1_BY_AP_ADDR,
	 PMIC_AUXADC_ADC_OUT_CH1_BY_AP_MASK, PMIC_AUXADC_ADC_OUT_CH1_BY_AP_SHIFT},
	{PMIC_AUXADC_ADC_RDY_CH1_BY_AP, PMIC_AUXADC_ADC_RDY_CH1_BY_AP_ADDR,
	 PMIC_AUXADC_ADC_RDY_CH1_BY_AP_MASK, PMIC_AUXADC_ADC_RDY_CH1_BY_AP_SHIFT},
	{PMIC_AUXADC_ADC_OUT_VISMPS0, PMIC_AUXADC_ADC_OUT_VISMPS0_ADDR,
	 PMIC_AUXADC_ADC_OUT_VISMPS0_MASK, PMIC_AUXADC_ADC_OUT_VISMPS0_SHIFT},
	{PMIC_AUXADC_ADC_RDY_VISMPS0, PMIC_AUXADC_ADC_RDY_VISMPS0_ADDR,
	 PMIC_AUXADC_ADC_RDY_VISMPS0_MASK, PMIC_AUXADC_ADC_RDY_VISMPS0_SHIFT},
	{PMIC_AUXADC_ADC_OUT_FGADC1, PMIC_AUXADC_ADC_OUT_FGADC1_ADDR,
	 PMIC_AUXADC_ADC_OUT_FGADC1_MASK, PMIC_AUXADC_ADC_OUT_FGADC1_SHIFT},
	{PMIC_AUXADC_ADC_RDY_FGADC1, PMIC_AUXADC_ADC_RDY_FGADC1_ADDR,
	 PMIC_AUXADC_ADC_RDY_FGADC1_MASK, PMIC_AUXADC_ADC_RDY_FGADC1_SHIFT},
	{PMIC_AUXADC_ADC_OUT_FGADC2, PMIC_AUXADC_ADC_OUT_FGADC2_ADDR,
	 PMIC_AUXADC_ADC_OUT_FGADC2_MASK, PMIC_AUXADC_ADC_OUT_FGADC2_SHIFT},
	{PMIC_AUXADC_ADC_RDY_FGADC2, PMIC_AUXADC_ADC_RDY_FGADC2_ADDR,
	 PMIC_AUXADC_ADC_RDY_FGADC2_MASK, PMIC_AUXADC_ADC_RDY_FGADC2_SHIFT},
	{PMIC_AUXADC_ADC_OUT_IMP, PMIC_AUXADC_ADC_OUT_IMP_ADDR,
	 PMIC_AUXADC_ADC_OUT_IMP_MASK, PMIC_AUXADC_ADC_OUT_IMP_SHIFT},
	{PMIC_AUXADC_ADC_RDY_IMP, PMIC_AUXADC_ADC_RDY_IMP_ADDR,
	 PMIC_AUXADC_ADC_RDY_IMP_MASK, PMIC_AUXADC_ADC_RDY_IMP_SHIFT},
	{PMIC_AUXADC_ADC_OUT_IMP_AVG, PMIC_AUXADC_ADC_OUT_IMP_AVG_ADDR,
	 PMIC_AUXADC_ADC_OUT_IMP_AVG_MASK, PMIC_AUXADC_ADC_OUT_IMP_AVG_SHIFT},
	{PMIC_AUXADC_ADC_RDY_IMP_AVG, PMIC_AUXADC_ADC_RDY_IMP_AVG_ADDR,
	 PMIC_AUXADC_ADC_RDY_IMP_AVG_MASK, PMIC_AUXADC_ADC_RDY_IMP_AVG_SHIFT},
	{PMIC_AUXADC_ADC_OUT_RAW, PMIC_AUXADC_ADC_OUT_RAW_ADDR,
	 PMIC_AUXADC_ADC_OUT_RAW_MASK, PMIC_AUXADC_ADC_OUT_RAW_SHIFT},
	{PMIC_AUXADC_ADC_OUT_MDRT, PMIC_AUXADC_ADC_OUT_MDRT_ADDR,
	 PMIC_AUXADC_ADC_OUT_MDRT_MASK, PMIC_AUXADC_ADC_OUT_MDRT_SHIFT},
	{PMIC_AUXADC_ADC_RDY_MDRT, PMIC_AUXADC_ADC_RDY_MDRT_ADDR,
	 PMIC_AUXADC_ADC_RDY_MDRT_MASK, PMIC_AUXADC_ADC_RDY_MDRT_SHIFT},
	{PMIC_AUXADC_ADC_OUT_MDBG, PMIC_AUXADC_ADC_OUT_MDBG_ADDR,
	 PMIC_AUXADC_ADC_OUT_MDBG_MASK, PMIC_AUXADC_ADC_OUT_MDBG_SHIFT},
	{PMIC_AUXADC_ADC_RDY_MDBG, PMIC_AUXADC_ADC_RDY_MDBG_ADDR,
	 PMIC_AUXADC_ADC_RDY_MDBG_MASK, PMIC_AUXADC_ADC_RDY_MDBG_SHIFT},
	{PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS, PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS_ADDR,
	 PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS_MASK, PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS_SHIFT},
	{PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS, PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS_ADDR,
	 PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS_MASK, PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS_SHIFT},
	{PMIC_AUXADC_ADC_OUT_DCXO_BY_MD, PMIC_AUXADC_ADC_OUT_DCXO_BY_MD_ADDR,
	 PMIC_AUXADC_ADC_OUT_DCXO_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_DCXO_BY_MD_SHIFT},
	{PMIC_AUXADC_ADC_RDY_DCXO_BY_MD, PMIC_AUXADC_ADC_RDY_DCXO_BY_MD_ADDR,
	 PMIC_AUXADC_ADC_RDY_DCXO_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_DCXO_BY_MD_SHIFT},
	{PMIC_AUXADC_ADC_OUT_DCXO_BY_AP, PMIC_AUXADC_ADC_OUT_DCXO_BY_AP_ADDR,
	 PMIC_AUXADC_ADC_OUT_DCXO_BY_AP_MASK, PMIC_AUXADC_ADC_OUT_DCXO_BY_AP_SHIFT},
	{PMIC_AUXADC_ADC_RDY_DCXO_BY_AP, PMIC_AUXADC_ADC_RDY_DCXO_BY_AP_ADDR,
	 PMIC_AUXADC_ADC_RDY_DCXO_BY_AP_MASK, PMIC_AUXADC_ADC_RDY_DCXO_BY_AP_SHIFT},
	{PMIC_AUXADC_ADC_OUT_DCXO_MDRT, PMIC_AUXADC_ADC_OUT_DCXO_MDRT_ADDR,
	 PMIC_AUXADC_ADC_OUT_DCXO_MDRT_MASK, PMIC_AUXADC_ADC_OUT_DCXO_MDRT_SHIFT},
	{PMIC_AUXADC_ADC_RDY_DCXO_MDRT, PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR,
	 PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MASK, PMIC_AUXADC_ADC_RDY_DCXO_MDRT_SHIFT},
	{PMIC_AUXADC_ADC_OUT_NAG, PMIC_AUXADC_ADC_OUT_NAG_ADDR,
	 PMIC_AUXADC_ADC_OUT_NAG_MASK, PMIC_AUXADC_ADC_OUT_NAG_SHIFT},
	{PMIC_AUXADC_ADC_RDY_NAG, PMIC_AUXADC_ADC_RDY_NAG_ADDR,
	 PMIC_AUXADC_ADC_RDY_NAG_MASK, PMIC_AUXADC_ADC_RDY_NAG_SHIFT},
	{PMIC_AUXADC_ADC_OUT_TYPEC_H, PMIC_AUXADC_ADC_OUT_TYPEC_H_ADDR,
	 PMIC_AUXADC_ADC_OUT_TYPEC_H_MASK, PMIC_AUXADC_ADC_OUT_TYPEC_H_SHIFT},
	{PMIC_AUXADC_ADC_RDY_TYPEC_H, PMIC_AUXADC_ADC_RDY_TYPEC_H_ADDR,
	 PMIC_AUXADC_ADC_RDY_TYPEC_H_MASK, PMIC_AUXADC_ADC_RDY_TYPEC_H_SHIFT},
	{PMIC_AUXADC_ADC_OUT_TYPEC_L, PMIC_AUXADC_ADC_OUT_TYPEC_L_ADDR,
	 PMIC_AUXADC_ADC_OUT_TYPEC_L_MASK, PMIC_AUXADC_ADC_OUT_TYPEC_L_SHIFT},
	{PMIC_AUXADC_ADC_RDY_TYPEC_L, PMIC_AUXADC_ADC_RDY_TYPEC_L_ADDR,
	 PMIC_AUXADC_ADC_RDY_TYPEC_L_MASK, PMIC_AUXADC_ADC_RDY_TYPEC_L_SHIFT},
	{PMIC_AUXADC_BUF_OUT_00, PMIC_AUXADC_BUF_OUT_00_ADDR,
	 PMIC_AUXADC_BUF_OUT_00_MASK, PMIC_AUXADC_BUF_OUT_00_SHIFT},
	{PMIC_AUXADC_BUF_RDY_00, PMIC_AUXADC_BUF_RDY_00_ADDR,
	 PMIC_AUXADC_BUF_RDY_00_MASK, PMIC_AUXADC_BUF_RDY_00_SHIFT},
	{PMIC_AUXADC_BUF_OUT_01, PMIC_AUXADC_BUF_OUT_01_ADDR,
	 PMIC_AUXADC_BUF_OUT_01_MASK, PMIC_AUXADC_BUF_OUT_01_SHIFT},
	{PMIC_AUXADC_BUF_RDY_01, PMIC_AUXADC_BUF_RDY_01_ADDR,
	 PMIC_AUXADC_BUF_RDY_01_MASK, PMIC_AUXADC_BUF_RDY_01_SHIFT},
	{PMIC_AUXADC_BUF_OUT_02, PMIC_AUXADC_BUF_OUT_02_ADDR,
	 PMIC_AUXADC_BUF_OUT_02_MASK, PMIC_AUXADC_BUF_OUT_02_SHIFT},
	{PMIC_AUXADC_BUF_RDY_02, PMIC_AUXADC_BUF_RDY_02_ADDR,
	 PMIC_AUXADC_BUF_RDY_02_MASK, PMIC_AUXADC_BUF_RDY_02_SHIFT},
	{PMIC_AUXADC_BUF_OUT_03, PMIC_AUXADC_BUF_OUT_03_ADDR,
	 PMIC_AUXADC_BUF_OUT_03_MASK, PMIC_AUXADC_BUF_OUT_03_SHIFT},
	{PMIC_AUXADC_BUF_RDY_03, PMIC_AUXADC_BUF_RDY_03_ADDR,
	 PMIC_AUXADC_BUF_RDY_03_MASK, PMIC_AUXADC_BUF_RDY_03_SHIFT},
	{PMIC_AUXADC_BUF_OUT_04, PMIC_AUXADC_BUF_OUT_04_ADDR,
	 PMIC_AUXADC_BUF_OUT_04_MASK, PMIC_AUXADC_BUF_OUT_04_SHIFT},
	{PMIC_AUXADC_BUF_RDY_04, PMIC_AUXADC_BUF_RDY_04_ADDR,
	 PMIC_AUXADC_BUF_RDY_04_MASK, PMIC_AUXADC_BUF_RDY_04_SHIFT},
	{PMIC_AUXADC_BUF_OUT_05, PMIC_AUXADC_BUF_OUT_05_ADDR,
	 PMIC_AUXADC_BUF_OUT_05_MASK, PMIC_AUXADC_BUF_OUT_05_SHIFT},
	{PMIC_AUXADC_BUF_RDY_05, PMIC_AUXADC_BUF_RDY_05_ADDR,
	 PMIC_AUXADC_BUF_RDY_05_MASK, PMIC_AUXADC_BUF_RDY_05_SHIFT},
	{PMIC_AUXADC_BUF_OUT_06, PMIC_AUXADC_BUF_OUT_06_ADDR,
	 PMIC_AUXADC_BUF_OUT_06_MASK, PMIC_AUXADC_BUF_OUT_06_SHIFT},
	{PMIC_AUXADC_BUF_RDY_06, PMIC_AUXADC_BUF_RDY_06_ADDR,
	 PMIC_AUXADC_BUF_RDY_06_MASK, PMIC_AUXADC_BUF_RDY_06_SHIFT},
	{PMIC_AUXADC_BUF_OUT_07, PMIC_AUXADC_BUF_OUT_07_ADDR,
	 PMIC_AUXADC_BUF_OUT_07_MASK, PMIC_AUXADC_BUF_OUT_07_SHIFT},
	{PMIC_AUXADC_BUF_RDY_07, PMIC_AUXADC_BUF_RDY_07_ADDR,
	 PMIC_AUXADC_BUF_RDY_07_MASK, PMIC_AUXADC_BUF_RDY_07_SHIFT},
	{PMIC_AUXADC_BUF_OUT_08, PMIC_AUXADC_BUF_OUT_08_ADDR,
	 PMIC_AUXADC_BUF_OUT_08_MASK, PMIC_AUXADC_BUF_OUT_08_SHIFT},
	{PMIC_AUXADC_BUF_RDY_08, PMIC_AUXADC_BUF_RDY_08_ADDR,
	 PMIC_AUXADC_BUF_RDY_08_MASK, PMIC_AUXADC_BUF_RDY_08_SHIFT},
	{PMIC_AUXADC_BUF_OUT_09, PMIC_AUXADC_BUF_OUT_09_ADDR,
	 PMIC_AUXADC_BUF_OUT_09_MASK, PMIC_AUXADC_BUF_OUT_09_SHIFT},
	{PMIC_AUXADC_BUF_RDY_09, PMIC_AUXADC_BUF_RDY_09_ADDR,
	 PMIC_AUXADC_BUF_RDY_09_MASK, PMIC_AUXADC_BUF_RDY_09_SHIFT},
	{PMIC_AUXADC_BUF_OUT_10, PMIC_AUXADC_BUF_OUT_10_ADDR,
	 PMIC_AUXADC_BUF_OUT_10_MASK, PMIC_AUXADC_BUF_OUT_10_SHIFT},
	{PMIC_AUXADC_BUF_RDY_10, PMIC_AUXADC_BUF_RDY_10_ADDR,
	 PMIC_AUXADC_BUF_RDY_10_MASK, PMIC_AUXADC_BUF_RDY_10_SHIFT},
	{PMIC_AUXADC_BUF_OUT_11, PMIC_AUXADC_BUF_OUT_11_ADDR,
	 PMIC_AUXADC_BUF_OUT_11_MASK, PMIC_AUXADC_BUF_OUT_11_SHIFT},
	{PMIC_AUXADC_BUF_RDY_11, PMIC_AUXADC_BUF_RDY_11_ADDR,
	 PMIC_AUXADC_BUF_RDY_11_MASK, PMIC_AUXADC_BUF_RDY_11_SHIFT},
	{PMIC_AUXADC_BUF_OUT_12, PMIC_AUXADC_BUF_OUT_12_ADDR,
	 PMIC_AUXADC_BUF_OUT_12_MASK, PMIC_AUXADC_BUF_OUT_12_SHIFT},
	{PMIC_AUXADC_BUF_RDY_12, PMIC_AUXADC_BUF_RDY_12_ADDR,
	 PMIC_AUXADC_BUF_RDY_12_MASK, PMIC_AUXADC_BUF_RDY_12_SHIFT},
	{PMIC_AUXADC_BUF_OUT_13, PMIC_AUXADC_BUF_OUT_13_ADDR,
	 PMIC_AUXADC_BUF_OUT_13_MASK, PMIC_AUXADC_BUF_OUT_13_SHIFT},
	{PMIC_AUXADC_BUF_RDY_13, PMIC_AUXADC_BUF_RDY_13_ADDR,
	 PMIC_AUXADC_BUF_RDY_13_MASK, PMIC_AUXADC_BUF_RDY_13_SHIFT},
	{PMIC_AUXADC_BUF_OUT_14, PMIC_AUXADC_BUF_OUT_14_ADDR,
	 PMIC_AUXADC_BUF_OUT_14_MASK, PMIC_AUXADC_BUF_OUT_14_SHIFT},
	{PMIC_AUXADC_BUF_RDY_14, PMIC_AUXADC_BUF_RDY_14_ADDR,
	 PMIC_AUXADC_BUF_RDY_14_MASK, PMIC_AUXADC_BUF_RDY_14_SHIFT},
	{PMIC_AUXADC_BUF_OUT_15, PMIC_AUXADC_BUF_OUT_15_ADDR,
	 PMIC_AUXADC_BUF_OUT_15_MASK, PMIC_AUXADC_BUF_OUT_15_SHIFT},
	{PMIC_AUXADC_BUF_RDY_15, PMIC_AUXADC_BUF_RDY_15_ADDR,
	 PMIC_AUXADC_BUF_RDY_15_MASK, PMIC_AUXADC_BUF_RDY_15_SHIFT},
	{PMIC_AUXADC_BUF_OUT_16, PMIC_AUXADC_BUF_OUT_16_ADDR,
	 PMIC_AUXADC_BUF_OUT_16_MASK, PMIC_AUXADC_BUF_OUT_16_SHIFT},
	{PMIC_AUXADC_BUF_RDY_16, PMIC_AUXADC_BUF_RDY_16_ADDR,
	 PMIC_AUXADC_BUF_RDY_16_MASK, PMIC_AUXADC_BUF_RDY_16_SHIFT},
	{PMIC_AUXADC_BUF_OUT_17, PMIC_AUXADC_BUF_OUT_17_ADDR,
	 PMIC_AUXADC_BUF_OUT_17_MASK, PMIC_AUXADC_BUF_OUT_17_SHIFT},
	{PMIC_AUXADC_BUF_RDY_17, PMIC_AUXADC_BUF_RDY_17_ADDR,
	 PMIC_AUXADC_BUF_RDY_17_MASK, PMIC_AUXADC_BUF_RDY_17_SHIFT},
	{PMIC_AUXADC_BUF_OUT_18, PMIC_AUXADC_BUF_OUT_18_ADDR,
	 PMIC_AUXADC_BUF_OUT_18_MASK, PMIC_AUXADC_BUF_OUT_18_SHIFT},
	{PMIC_AUXADC_BUF_RDY_18, PMIC_AUXADC_BUF_RDY_18_ADDR,
	 PMIC_AUXADC_BUF_RDY_18_MASK, PMIC_AUXADC_BUF_RDY_18_SHIFT},
	{PMIC_AUXADC_BUF_OUT_19, PMIC_AUXADC_BUF_OUT_19_ADDR,
	 PMIC_AUXADC_BUF_OUT_19_MASK, PMIC_AUXADC_BUF_OUT_19_SHIFT},
	{PMIC_AUXADC_BUF_RDY_19, PMIC_AUXADC_BUF_RDY_19_ADDR,
	 PMIC_AUXADC_BUF_RDY_19_MASK, PMIC_AUXADC_BUF_RDY_19_SHIFT},
	{PMIC_AUXADC_BUF_OUT_20, PMIC_AUXADC_BUF_OUT_20_ADDR,
	 PMIC_AUXADC_BUF_OUT_20_MASK, PMIC_AUXADC_BUF_OUT_20_SHIFT},
	{PMIC_AUXADC_BUF_RDY_20, PMIC_AUXADC_BUF_RDY_20_ADDR,
	 PMIC_AUXADC_BUF_RDY_20_MASK, PMIC_AUXADC_BUF_RDY_20_SHIFT},
	{PMIC_AUXADC_BUF_OUT_21, PMIC_AUXADC_BUF_OUT_21_ADDR,
	 PMIC_AUXADC_BUF_OUT_21_MASK, PMIC_AUXADC_BUF_OUT_21_SHIFT},
	{PMIC_AUXADC_BUF_RDY_21, PMIC_AUXADC_BUF_RDY_21_ADDR,
	 PMIC_AUXADC_BUF_RDY_21_MASK, PMIC_AUXADC_BUF_RDY_21_SHIFT},
	{PMIC_AUXADC_BUF_OUT_22, PMIC_AUXADC_BUF_OUT_22_ADDR,
	 PMIC_AUXADC_BUF_OUT_22_MASK, PMIC_AUXADC_BUF_OUT_22_SHIFT},
	{PMIC_AUXADC_BUF_RDY_22, PMIC_AUXADC_BUF_RDY_22_ADDR,
	 PMIC_AUXADC_BUF_RDY_22_MASK, PMIC_AUXADC_BUF_RDY_22_SHIFT},
	{PMIC_AUXADC_BUF_OUT_23, PMIC_AUXADC_BUF_OUT_23_ADDR,
	 PMIC_AUXADC_BUF_OUT_23_MASK, PMIC_AUXADC_BUF_OUT_23_SHIFT},
	{PMIC_AUXADC_BUF_RDY_23, PMIC_AUXADC_BUF_RDY_23_ADDR,
	 PMIC_AUXADC_BUF_RDY_23_MASK, PMIC_AUXADC_BUF_RDY_23_SHIFT},
	{PMIC_AUXADC_BUF_OUT_24, PMIC_AUXADC_BUF_OUT_24_ADDR,
	 PMIC_AUXADC_BUF_OUT_24_MASK, PMIC_AUXADC_BUF_OUT_24_SHIFT},
	{PMIC_AUXADC_BUF_RDY_24, PMIC_AUXADC_BUF_RDY_24_ADDR,
	 PMIC_AUXADC_BUF_RDY_24_MASK, PMIC_AUXADC_BUF_RDY_24_SHIFT},
	{PMIC_AUXADC_BUF_OUT_25, PMIC_AUXADC_BUF_OUT_25_ADDR,
	 PMIC_AUXADC_BUF_OUT_25_MASK, PMIC_AUXADC_BUF_OUT_25_SHIFT},
	{PMIC_AUXADC_BUF_RDY_25, PMIC_AUXADC_BUF_RDY_25_ADDR,
	 PMIC_AUXADC_BUF_RDY_25_MASK, PMIC_AUXADC_BUF_RDY_25_SHIFT},
	{PMIC_AUXADC_BUF_OUT_26, PMIC_AUXADC_BUF_OUT_26_ADDR,
	 PMIC_AUXADC_BUF_OUT_26_MASK, PMIC_AUXADC_BUF_OUT_26_SHIFT},
	{PMIC_AUXADC_BUF_RDY_26, PMIC_AUXADC_BUF_RDY_26_ADDR,
	 PMIC_AUXADC_BUF_RDY_26_MASK, PMIC_AUXADC_BUF_RDY_26_SHIFT},
	{PMIC_AUXADC_BUF_OUT_27, PMIC_AUXADC_BUF_OUT_27_ADDR,
	 PMIC_AUXADC_BUF_OUT_27_MASK, PMIC_AUXADC_BUF_OUT_27_SHIFT},
	{PMIC_AUXADC_BUF_RDY_27, PMIC_AUXADC_BUF_RDY_27_ADDR,
	 PMIC_AUXADC_BUF_RDY_27_MASK, PMIC_AUXADC_BUF_RDY_27_SHIFT},
	{PMIC_AUXADC_BUF_OUT_28, PMIC_AUXADC_BUF_OUT_28_ADDR,
	 PMIC_AUXADC_BUF_OUT_28_MASK, PMIC_AUXADC_BUF_OUT_28_SHIFT},
	{PMIC_AUXADC_BUF_RDY_28, PMIC_AUXADC_BUF_RDY_28_ADDR,
	 PMIC_AUXADC_BUF_RDY_28_MASK, PMIC_AUXADC_BUF_RDY_28_SHIFT},
	{PMIC_AUXADC_BUF_OUT_29, PMIC_AUXADC_BUF_OUT_29_ADDR,
	 PMIC_AUXADC_BUF_OUT_29_MASK, PMIC_AUXADC_BUF_OUT_29_SHIFT},
	{PMIC_AUXADC_BUF_RDY_29, PMIC_AUXADC_BUF_RDY_29_ADDR,
	 PMIC_AUXADC_BUF_RDY_29_MASK, PMIC_AUXADC_BUF_RDY_29_SHIFT},
	{PMIC_AUXADC_BUF_OUT_30, PMIC_AUXADC_BUF_OUT_30_ADDR,
	 PMIC_AUXADC_BUF_OUT_30_MASK, PMIC_AUXADC_BUF_OUT_30_SHIFT},
	{PMIC_AUXADC_BUF_RDY_30, PMIC_AUXADC_BUF_RDY_30_ADDR,
	 PMIC_AUXADC_BUF_RDY_30_MASK, PMIC_AUXADC_BUF_RDY_30_SHIFT},
	{PMIC_AUXADC_BUF_OUT_31, PMIC_AUXADC_BUF_OUT_31_ADDR,
	 PMIC_AUXADC_BUF_OUT_31_MASK, PMIC_AUXADC_BUF_OUT_31_SHIFT},
	{PMIC_AUXADC_BUF_RDY_31, PMIC_AUXADC_BUF_RDY_31_ADDR,
	 PMIC_AUXADC_BUF_RDY_31_MASK, PMIC_AUXADC_BUF_RDY_31_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN, PMIC_AUXADC_ADC_BUSY_IN_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_MASK, PMIC_AUXADC_ADC_BUSY_IN_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_LBAT, PMIC_AUXADC_ADC_BUSY_IN_LBAT_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_LBAT_MASK, PMIC_AUXADC_ADC_BUSY_IN_LBAT_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_LBAT2, PMIC_AUXADC_ADC_BUSY_IN_LBAT2_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_LBAT2_MASK, PMIC_AUXADC_ADC_BUSY_IN_LBAT2_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_VISMPS0, PMIC_AUXADC_ADC_BUSY_IN_VISMPS0_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_VISMPS0_MASK, PMIC_AUXADC_ADC_BUSY_IN_VISMPS0_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_WAKEUP, PMIC_AUXADC_ADC_BUSY_IN_WAKEUP_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_WAKEUP_MASK, PMIC_AUXADC_ADC_BUSY_IN_WAKEUP_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT, PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_MASK,
	 PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP, PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP_MASK,
	 PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD, PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD_MASK,
	 PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS, PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MASK,
	 PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_MDRT, PMIC_AUXADC_ADC_BUSY_IN_MDRT_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_MDRT_MASK, PMIC_AUXADC_ADC_BUSY_IN_MDRT_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_MDBG, PMIC_AUXADC_ADC_BUSY_IN_MDBG_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_MDBG_MASK, PMIC_AUXADC_ADC_BUSY_IN_MDBG_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_SHARE, PMIC_AUXADC_ADC_BUSY_IN_SHARE_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_SHARE_MASK, PMIC_AUXADC_ADC_BUSY_IN_SHARE_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_IMP, PMIC_AUXADC_ADC_BUSY_IN_IMP_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_IMP_MASK, PMIC_AUXADC_ADC_BUSY_IN_IMP_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_FGADC1, PMIC_AUXADC_ADC_BUSY_IN_FGADC1_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_FGADC1_MASK, PMIC_AUXADC_ADC_BUSY_IN_FGADC1_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_FGADC2, PMIC_AUXADC_ADC_BUSY_IN_FGADC2_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_FGADC2_MASK, PMIC_AUXADC_ADC_BUSY_IN_FGADC2_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_GPS_AP, PMIC_AUXADC_ADC_BUSY_IN_GPS_AP_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_GPS_AP_MASK, PMIC_AUXADC_ADC_BUSY_IN_GPS_AP_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_GPS_MD, PMIC_AUXADC_ADC_BUSY_IN_GPS_MD_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_GPS_MD_MASK, PMIC_AUXADC_ADC_BUSY_IN_GPS_MD_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_GPS, PMIC_AUXADC_ADC_BUSY_IN_GPS_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_GPS_MASK, PMIC_AUXADC_ADC_BUSY_IN_GPS_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_THR_HW, PMIC_AUXADC_ADC_BUSY_IN_THR_HW_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_THR_HW_MASK, PMIC_AUXADC_ADC_BUSY_IN_THR_HW_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_THR_MD, PMIC_AUXADC_ADC_BUSY_IN_THR_MD_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_THR_MD_MASK, PMIC_AUXADC_ADC_BUSY_IN_THR_MD_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_TYPEC_H, PMIC_AUXADC_ADC_BUSY_IN_TYPEC_H_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_TYPEC_H_MASK, PMIC_AUXADC_ADC_BUSY_IN_TYPEC_H_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_TYPEC_L, PMIC_AUXADC_ADC_BUSY_IN_TYPEC_L_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_TYPEC_L_MASK, PMIC_AUXADC_ADC_BUSY_IN_TYPEC_L_SHIFT},
	{PMIC_AUXADC_ADC_BUSY_IN_NAG, PMIC_AUXADC_ADC_BUSY_IN_NAG_ADDR,
	 PMIC_AUXADC_ADC_BUSY_IN_NAG_MASK, PMIC_AUXADC_ADC_BUSY_IN_NAG_SHIFT},
	{PMIC_AUXADC_RQST_CH0, PMIC_AUXADC_RQST_CH0_ADDR, PMIC_AUXADC_RQST_CH0_MASK,
	 PMIC_AUXADC_RQST_CH0_SHIFT},
	{PMIC_AUXADC_RQST_CH1, PMIC_AUXADC_RQST_CH1_ADDR, PMIC_AUXADC_RQST_CH1_MASK,
	 PMIC_AUXADC_RQST_CH1_SHIFT},
	{PMIC_AUXADC_RQST_CH2, PMIC_AUXADC_RQST_CH2_ADDR, PMIC_AUXADC_RQST_CH2_MASK,
	 PMIC_AUXADC_RQST_CH2_SHIFT},
	{PMIC_AUXADC_RQST_CH3, PMIC_AUXADC_RQST_CH3_ADDR, PMIC_AUXADC_RQST_CH3_MASK,
	 PMIC_AUXADC_RQST_CH3_SHIFT},
	{PMIC_AUXADC_RQST_CH4, PMIC_AUXADC_RQST_CH4_ADDR, PMIC_AUXADC_RQST_CH4_MASK,
	 PMIC_AUXADC_RQST_CH4_SHIFT},
	{PMIC_AUXADC_RQST_CH5, PMIC_AUXADC_RQST_CH5_ADDR, PMIC_AUXADC_RQST_CH5_MASK,
	 PMIC_AUXADC_RQST_CH5_SHIFT},
	{PMIC_AUXADC_RQST_CH6, PMIC_AUXADC_RQST_CH6_ADDR, PMIC_AUXADC_RQST_CH6_MASK,
	 PMIC_AUXADC_RQST_CH6_SHIFT},
	{PMIC_AUXADC_RQST_CH7, PMIC_AUXADC_RQST_CH7_ADDR, PMIC_AUXADC_RQST_CH7_MASK,
	 PMIC_AUXADC_RQST_CH7_SHIFT},
	{PMIC_AUXADC_RQST_CH8, PMIC_AUXADC_RQST_CH8_ADDR, PMIC_AUXADC_RQST_CH8_MASK,
	 PMIC_AUXADC_RQST_CH8_SHIFT},
	{PMIC_AUXADC_RQST_CH9, PMIC_AUXADC_RQST_CH9_ADDR, PMIC_AUXADC_RQST_CH9_MASK,
	 PMIC_AUXADC_RQST_CH9_SHIFT},
	{PMIC_AUXADC_RQST_CH10, PMIC_AUXADC_RQST_CH10_ADDR,
	 PMIC_AUXADC_RQST_CH10_MASK, PMIC_AUXADC_RQST_CH10_SHIFT},
	{PMIC_AUXADC_RQST_CH11, PMIC_AUXADC_RQST_CH11_ADDR,
	 PMIC_AUXADC_RQST_CH11_MASK, PMIC_AUXADC_RQST_CH11_SHIFT},
	{PMIC_AUXADC_RQST_CH12, PMIC_AUXADC_RQST_CH12_ADDR,
	 PMIC_AUXADC_RQST_CH12_MASK, PMIC_AUXADC_RQST_CH12_SHIFT},
	{PMIC_AUXADC_RQST_CH13, PMIC_AUXADC_RQST_CH13_ADDR,
	 PMIC_AUXADC_RQST_CH13_MASK, PMIC_AUXADC_RQST_CH13_SHIFT},
	{PMIC_AUXADC_RQST_CH14, PMIC_AUXADC_RQST_CH14_ADDR,
	 PMIC_AUXADC_RQST_CH14_MASK, PMIC_AUXADC_RQST_CH14_SHIFT},
	{PMIC_AUXADC_RQST_CH15, PMIC_AUXADC_RQST_CH15_ADDR,
	 PMIC_AUXADC_RQST_CH15_MASK, PMIC_AUXADC_RQST_CH15_SHIFT},
	{PMIC_AUXADC_RQST0_SET, PMIC_AUXADC_RQST0_SET_ADDR,
	 PMIC_AUXADC_RQST0_SET_MASK, PMIC_AUXADC_RQST0_SET_SHIFT},
	{PMIC_AUXADC_RQST0_CLR, PMIC_AUXADC_RQST0_CLR_ADDR,
	 PMIC_AUXADC_RQST0_CLR_MASK, PMIC_AUXADC_RQST0_CLR_SHIFT},
	{PMIC_AUXADC_RQST_CH0_BY_MD, PMIC_AUXADC_RQST_CH0_BY_MD_ADDR,
	 PMIC_AUXADC_RQST_CH0_BY_MD_MASK, PMIC_AUXADC_RQST_CH0_BY_MD_SHIFT},
	{PMIC_AUXADC_RQST_CH1_BY_MD, PMIC_AUXADC_RQST_CH1_BY_MD_ADDR,
	 PMIC_AUXADC_RQST_CH1_BY_MD_MASK, PMIC_AUXADC_RQST_CH1_BY_MD_SHIFT},
	{PMIC_AUXADC_RQST_RSV0, PMIC_AUXADC_RQST_RSV0_ADDR,
	 PMIC_AUXADC_RQST_RSV0_MASK, PMIC_AUXADC_RQST_RSV0_SHIFT},
	{PMIC_AUXADC_RQST_CH4_BY_MD, PMIC_AUXADC_RQST_CH4_BY_MD_ADDR,
	 PMIC_AUXADC_RQST_CH4_BY_MD_MASK, PMIC_AUXADC_RQST_CH4_BY_MD_SHIFT},
	{PMIC_AUXADC_RQST_CH7_BY_MD, PMIC_AUXADC_RQST_CH7_BY_MD_ADDR,
	 PMIC_AUXADC_RQST_CH7_BY_MD_MASK, PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT},
	{PMIC_AUXADC_RQST_CH7_BY_GPS, PMIC_AUXADC_RQST_CH7_BY_GPS_ADDR,
	 PMIC_AUXADC_RQST_CH7_BY_GPS_MASK, PMIC_AUXADC_RQST_CH7_BY_GPS_SHIFT},
	{PMIC_AUXADC_RQST_DCXO_BY_MD, PMIC_AUXADC_RQST_DCXO_BY_MD_ADDR,
	 PMIC_AUXADC_RQST_DCXO_BY_MD_MASK, PMIC_AUXADC_RQST_DCXO_BY_MD_SHIFT},
	{PMIC_AUXADC_RQST_DCXO_BY_GPS, PMIC_AUXADC_RQST_DCXO_BY_GPS_ADDR,
	 PMIC_AUXADC_RQST_DCXO_BY_GPS_MASK, PMIC_AUXADC_RQST_DCXO_BY_GPS_SHIFT},
	{PMIC_AUXADC_RQST_RSV1, PMIC_AUXADC_RQST_RSV1_ADDR,
	 PMIC_AUXADC_RQST_RSV1_MASK, PMIC_AUXADC_RQST_RSV1_SHIFT},
	{PMIC_AUXADC_RQST1_SET, PMIC_AUXADC_RQST1_SET_ADDR,
	 PMIC_AUXADC_RQST1_SET_MASK, PMIC_AUXADC_RQST1_SET_SHIFT},
	{PMIC_AUXADC_RQST1_CLR, PMIC_AUXADC_RQST1_CLR_ADDR,
	 PMIC_AUXADC_RQST1_CLR_MASK, PMIC_AUXADC_RQST1_CLR_SHIFT},
	{PMIC_AUXADC_CK_ON_EXTD, PMIC_AUXADC_CK_ON_EXTD_ADDR,
	 PMIC_AUXADC_CK_ON_EXTD_MASK, PMIC_AUXADC_CK_ON_EXTD_SHIFT},
	{PMIC_AUXADC_SRCLKEN_SRC_SEL, PMIC_AUXADC_SRCLKEN_SRC_SEL_ADDR,
	 PMIC_AUXADC_SRCLKEN_SRC_SEL_MASK, PMIC_AUXADC_SRCLKEN_SRC_SEL_SHIFT},
	{PMIC_AUXADC_ADC_PWDB, PMIC_AUXADC_ADC_PWDB_ADDR, PMIC_AUXADC_ADC_PWDB_MASK,
	 PMIC_AUXADC_ADC_PWDB_SHIFT},
	{PMIC_AUXADC_ADC_PWDB_SWCTRL, PMIC_AUXADC_ADC_PWDB_SWCTRL_ADDR,
	 PMIC_AUXADC_ADC_PWDB_SWCTRL_MASK, PMIC_AUXADC_ADC_PWDB_SWCTRL_SHIFT},
	{PMIC_AUXADC_STRUP_CK_ON_ENB, PMIC_AUXADC_STRUP_CK_ON_ENB_ADDR,
	 PMIC_AUXADC_STRUP_CK_ON_ENB_MASK, PMIC_AUXADC_STRUP_CK_ON_ENB_SHIFT},
	{PMIC_AUXADC_ADC_RDY_WAKEUP_CLR, PMIC_AUXADC_ADC_RDY_WAKEUP_CLR_ADDR,
	 PMIC_AUXADC_ADC_RDY_WAKEUP_CLR_MASK, PMIC_AUXADC_ADC_RDY_WAKEUP_CLR_SHIFT},
	{PMIC_AUXADC_SRCLKEN_CK_EN, PMIC_AUXADC_SRCLKEN_CK_EN_ADDR,
	 PMIC_AUXADC_SRCLKEN_CK_EN_MASK, PMIC_AUXADC_SRCLKEN_CK_EN_SHIFT},
	{PMIC_AUXADC_CK_AON_GPS, PMIC_AUXADC_CK_AON_GPS_ADDR,
	 PMIC_AUXADC_CK_AON_GPS_MASK, PMIC_AUXADC_CK_AON_GPS_SHIFT},
	{PMIC_AUXADC_CK_AON_MD, PMIC_AUXADC_CK_AON_MD_ADDR,
	 PMIC_AUXADC_CK_AON_MD_MASK, PMIC_AUXADC_CK_AON_MD_SHIFT},
	{PMIC_AUXADC_CK_AON, PMIC_AUXADC_CK_AON_ADDR, PMIC_AUXADC_CK_AON_MASK,
	 PMIC_AUXADC_CK_AON_SHIFT},
	{PMIC_AUXADC_CON0_SET, PMIC_AUXADC_CON0_SET_ADDR, PMIC_AUXADC_CON0_SET_MASK,
	 PMIC_AUXADC_CON0_SET_SHIFT},
	{PMIC_AUXADC_CON0_CLR, PMIC_AUXADC_CON0_CLR_ADDR, PMIC_AUXADC_CON0_CLR_MASK,
	 PMIC_AUXADC_CON0_CLR_SHIFT},
	{PMIC_AUXADC_AVG_NUM_SMALL, PMIC_AUXADC_AVG_NUM_SMALL_ADDR,
	 PMIC_AUXADC_AVG_NUM_SMALL_MASK, PMIC_AUXADC_AVG_NUM_SMALL_SHIFT},
	{PMIC_AUXADC_AVG_NUM_LARGE, PMIC_AUXADC_AVG_NUM_LARGE_ADDR,
	 PMIC_AUXADC_AVG_NUM_LARGE_MASK, PMIC_AUXADC_AVG_NUM_LARGE_SHIFT},
	{PMIC_AUXADC_SPL_NUM, PMIC_AUXADC_SPL_NUM_ADDR, PMIC_AUXADC_SPL_NUM_MASK,
	 PMIC_AUXADC_SPL_NUM_SHIFT},
	{PMIC_AUXADC_AVG_NUM_SEL, PMIC_AUXADC_AVG_NUM_SEL_ADDR,
	 PMIC_AUXADC_AVG_NUM_SEL_MASK, PMIC_AUXADC_AVG_NUM_SEL_SHIFT},
	{PMIC_AUXADC_AVG_NUM_SEL_SHARE, PMIC_AUXADC_AVG_NUM_SEL_SHARE_ADDR,
	 PMIC_AUXADC_AVG_NUM_SEL_SHARE_MASK, PMIC_AUXADC_AVG_NUM_SEL_SHARE_SHIFT},
	{PMIC_AUXADC_AVG_NUM_SEL_LBAT, PMIC_AUXADC_AVG_NUM_SEL_LBAT_ADDR,
	 PMIC_AUXADC_AVG_NUM_SEL_LBAT_MASK, PMIC_AUXADC_AVG_NUM_SEL_LBAT_SHIFT},
	{PMIC_AUXADC_AVG_NUM_SEL_VISMPS, PMIC_AUXADC_AVG_NUM_SEL_VISMPS_ADDR,
	 PMIC_AUXADC_AVG_NUM_SEL_VISMPS_MASK, PMIC_AUXADC_AVG_NUM_SEL_VISMPS_SHIFT},
	{PMIC_AUXADC_AVG_NUM_SEL_WAKEUP, PMIC_AUXADC_AVG_NUM_SEL_WAKEUP_ADDR,
	 PMIC_AUXADC_AVG_NUM_SEL_WAKEUP_MASK, PMIC_AUXADC_AVG_NUM_SEL_WAKEUP_SHIFT},
	{PMIC_AUXADC_SPL_NUM_LARGE, PMIC_AUXADC_SPL_NUM_LARGE_ADDR,
	 PMIC_AUXADC_SPL_NUM_LARGE_MASK, PMIC_AUXADC_SPL_NUM_LARGE_SHIFT},
	{PMIC_AUXADC_SPL_NUM_SLEEP, PMIC_AUXADC_SPL_NUM_SLEEP_ADDR,
	 PMIC_AUXADC_SPL_NUM_SLEEP_MASK, PMIC_AUXADC_SPL_NUM_SLEEP_SHIFT},
	{PMIC_AUXADC_SPL_NUM_SLEEP_SEL, PMIC_AUXADC_SPL_NUM_SLEEP_SEL_ADDR,
	 PMIC_AUXADC_SPL_NUM_SLEEP_SEL_MASK, PMIC_AUXADC_SPL_NUM_SLEEP_SEL_SHIFT},
	{PMIC_AUXADC_SPL_NUM_SEL, PMIC_AUXADC_SPL_NUM_SEL_ADDR,
	 PMIC_AUXADC_SPL_NUM_SEL_MASK, PMIC_AUXADC_SPL_NUM_SEL_SHIFT},
	{PMIC_AUXADC_SPL_NUM_SEL_SHARE, PMIC_AUXADC_SPL_NUM_SEL_SHARE_ADDR,
	 PMIC_AUXADC_SPL_NUM_SEL_SHARE_MASK, PMIC_AUXADC_SPL_NUM_SEL_SHARE_SHIFT},
	{PMIC_AUXADC_SPL_NUM_SEL_LBAT, PMIC_AUXADC_SPL_NUM_SEL_LBAT_ADDR,
	 PMIC_AUXADC_SPL_NUM_SEL_LBAT_MASK, PMIC_AUXADC_SPL_NUM_SEL_LBAT_SHIFT},
	{PMIC_AUXADC_SPL_NUM_SEL_VISMPS, PMIC_AUXADC_SPL_NUM_SEL_VISMPS_ADDR,
	 PMIC_AUXADC_SPL_NUM_SEL_VISMPS_MASK, PMIC_AUXADC_SPL_NUM_SEL_VISMPS_SHIFT},
	{PMIC_AUXADC_SPL_NUM_SEL_WAKEUP, PMIC_AUXADC_SPL_NUM_SEL_WAKEUP_ADDR,
	 PMIC_AUXADC_SPL_NUM_SEL_WAKEUP_MASK, PMIC_AUXADC_SPL_NUM_SEL_WAKEUP_SHIFT},
	{PMIC_AUXADC_TRIM_CH0_SEL, PMIC_AUXADC_TRIM_CH0_SEL_ADDR,
	 PMIC_AUXADC_TRIM_CH0_SEL_MASK, PMIC_AUXADC_TRIM_CH0_SEL_SHIFT},
	{PMIC_AUXADC_TRIM_CH1_SEL, PMIC_AUXADC_TRIM_CH1_SEL_ADDR,
	 PMIC_AUXADC_TRIM_CH1_SEL_MASK, PMIC_AUXADC_TRIM_CH1_SEL_SHIFT},
	{PMIC_AUXADC_TRIM_CH2_SEL, PMIC_AUXADC_TRIM_CH2_SEL_ADDR,
	 PMIC_AUXADC_TRIM_CH2_SEL_MASK, PMIC_AUXADC_TRIM_CH2_SEL_SHIFT},
	{PMIC_AUXADC_TRIM_CH3_SEL, PMIC_AUXADC_TRIM_CH3_SEL_ADDR,
	 PMIC_AUXADC_TRIM_CH3_SEL_MASK, PMIC_AUXADC_TRIM_CH3_SEL_SHIFT},
	{PMIC_AUXADC_TRIM_CH4_SEL, PMIC_AUXADC_TRIM_CH4_SEL_ADDR,
	 PMIC_AUXADC_TRIM_CH4_SEL_MASK, PMIC_AUXADC_TRIM_CH4_SEL_SHIFT},
	{PMIC_AUXADC_TRIM_CH5_SEL, PMIC_AUXADC_TRIM_CH5_SEL_ADDR,
	 PMIC_AUXADC_TRIM_CH5_SEL_MASK, PMIC_AUXADC_TRIM_CH5_SEL_SHIFT},
	{PMIC_AUXADC_TRIM_CH6_SEL, PMIC_AUXADC_TRIM_CH6_SEL_ADDR,
	 PMIC_AUXADC_TRIM_CH6_SEL_MASK, PMIC_AUXADC_TRIM_CH6_SEL_SHIFT},
	{PMIC_AUXADC_TRIM_CH7_SEL, PMIC_AUXADC_TRIM_CH7_SEL_ADDR,
	 PMIC_AUXADC_TRIM_CH7_SEL_MASK, PMIC_AUXADC_TRIM_CH7_SEL_SHIFT},
	{PMIC_AUXADC_TRIM_CH8_SEL, PMIC_AUXADC_TRIM_CH8_SEL_ADDR,
	 PMIC_AUXADC_TRIM_CH8_SEL_MASK, PMIC_AUXADC_TRIM_CH8_SEL_SHIFT},
	{PMIC_AUXADC_TRIM_CH9_SEL, PMIC_AUXADC_TRIM_CH9_SEL_ADDR,
	 PMIC_AUXADC_TRIM_CH9_SEL_MASK, PMIC_AUXADC_TRIM_CH9_SEL_SHIFT},
	{PMIC_AUXADC_TRIM_CH10_SEL, PMIC_AUXADC_TRIM_CH10_SEL_ADDR,
	 PMIC_AUXADC_TRIM_CH10_SEL_MASK, PMIC_AUXADC_TRIM_CH10_SEL_SHIFT},
	{PMIC_AUXADC_TRIM_CH11_SEL, PMIC_AUXADC_TRIM_CH11_SEL_ADDR,
	 PMIC_AUXADC_TRIM_CH11_SEL_MASK, PMIC_AUXADC_TRIM_CH11_SEL_SHIFT},
	{PMIC_AUXADC_ADC_2S_COMP_ENB, PMIC_AUXADC_ADC_2S_COMP_ENB_ADDR,
	 PMIC_AUXADC_ADC_2S_COMP_ENB_MASK, PMIC_AUXADC_ADC_2S_COMP_ENB_SHIFT},
	{PMIC_AUXADC_ADC_TRIM_COMP, PMIC_AUXADC_ADC_TRIM_COMP_ADDR,
	 PMIC_AUXADC_ADC_TRIM_COMP_MASK, PMIC_AUXADC_ADC_TRIM_COMP_SHIFT},
	{PMIC_AUXADC_SW_GAIN_TRIM, PMIC_AUXADC_SW_GAIN_TRIM_ADDR,
	 PMIC_AUXADC_SW_GAIN_TRIM_MASK, PMIC_AUXADC_SW_GAIN_TRIM_SHIFT},
	{PMIC_AUXADC_SW_OFFSET_TRIM, PMIC_AUXADC_SW_OFFSET_TRIM_ADDR,
	 PMIC_AUXADC_SW_OFFSET_TRIM_MASK, PMIC_AUXADC_SW_OFFSET_TRIM_SHIFT},
	{PMIC_AUXADC_RNG_EN, PMIC_AUXADC_RNG_EN_ADDR, PMIC_AUXADC_RNG_EN_MASK,
	 PMIC_AUXADC_RNG_EN_SHIFT},
	{PMIC_AUXADC_DATA_REUSE_SEL, PMIC_AUXADC_DATA_REUSE_SEL_ADDR,
	 PMIC_AUXADC_DATA_REUSE_SEL_MASK, PMIC_AUXADC_DATA_REUSE_SEL_SHIFT},
	{PMIC_AUXADC_TEST_MODE, PMIC_AUXADC_TEST_MODE_ADDR,
	 PMIC_AUXADC_TEST_MODE_MASK, PMIC_AUXADC_TEST_MODE_SHIFT},
	{PMIC_AUXADC_BIT_SEL, PMIC_AUXADC_BIT_SEL_ADDR, PMIC_AUXADC_BIT_SEL_MASK,
	 PMIC_AUXADC_BIT_SEL_SHIFT},
	{PMIC_AUXADC_START_SW, PMIC_AUXADC_START_SW_ADDR, PMIC_AUXADC_START_SW_MASK,
	 PMIC_AUXADC_START_SW_SHIFT},
	{PMIC_AUXADC_START_SWCTRL, PMIC_AUXADC_START_SWCTRL_ADDR,
	 PMIC_AUXADC_START_SWCTRL_MASK, PMIC_AUXADC_START_SWCTRL_SHIFT},
	{PMIC_AUXADC_TS_VBE_SEL, PMIC_AUXADC_TS_VBE_SEL_ADDR,
	 PMIC_AUXADC_TS_VBE_SEL_MASK, PMIC_AUXADC_TS_VBE_SEL_SHIFT},
	{PMIC_AUXADC_TS_VBE_SEL_SWCTRL, PMIC_AUXADC_TS_VBE_SEL_SWCTRL_ADDR,
	 PMIC_AUXADC_TS_VBE_SEL_SWCTRL_MASK, PMIC_AUXADC_TS_VBE_SEL_SWCTRL_SHIFT},
	{PMIC_AUXADC_VBUF_EN, PMIC_AUXADC_VBUF_EN_ADDR, PMIC_AUXADC_VBUF_EN_MASK,
	 PMIC_AUXADC_VBUF_EN_SHIFT},
	{PMIC_AUXADC_VBUF_EN_SWCTRL, PMIC_AUXADC_VBUF_EN_SWCTRL_ADDR,
	 PMIC_AUXADC_VBUF_EN_SWCTRL_MASK, PMIC_AUXADC_VBUF_EN_SWCTRL_SHIFT},
	{PMIC_AUXADC_OUT_SEL, PMIC_AUXADC_OUT_SEL_ADDR, PMIC_AUXADC_OUT_SEL_MASK,
	 PMIC_AUXADC_OUT_SEL_SHIFT},
	{PMIC_AUXADC_DA_DAC, PMIC_AUXADC_DA_DAC_ADDR, PMIC_AUXADC_DA_DAC_MASK,
	 PMIC_AUXADC_DA_DAC_SHIFT},
	{PMIC_AUXADC_DA_DAC_SWCTRL, PMIC_AUXADC_DA_DAC_SWCTRL_ADDR,
	 PMIC_AUXADC_DA_DAC_SWCTRL_MASK, PMIC_AUXADC_DA_DAC_SWCTRL_SHIFT},
	{PMIC_AD_AUXADC_COMP, PMIC_AD_AUXADC_COMP_ADDR, PMIC_AD_AUXADC_COMP_MASK,
	 PMIC_AD_AUXADC_COMP_SHIFT},
	{PMIC_RG_VBUF_EXTEN, PMIC_RG_VBUF_EXTEN_ADDR, PMIC_RG_VBUF_EXTEN_MASK,
	 PMIC_RG_VBUF_EXTEN_SHIFT},
	{PMIC_RG_VBUF_CALEN, PMIC_RG_VBUF_CALEN_ADDR, PMIC_RG_VBUF_CALEN_MASK,
	 PMIC_RG_VBUF_CALEN_SHIFT},
	{PMIC_RG_VBUF_BYP, PMIC_RG_VBUF_BYP_ADDR, PMIC_RG_VBUF_BYP_MASK,
	 PMIC_RG_VBUF_BYP_SHIFT},
	{PMIC_RG_AUX_RSV, PMIC_RG_AUX_RSV_ADDR, PMIC_RG_AUX_RSV_MASK,
	 PMIC_RG_AUX_RSV_SHIFT},
	{PMIC_RG_AUXADC_CALI, PMIC_RG_AUXADC_CALI_ADDR, PMIC_RG_AUXADC_CALI_MASK,
	 PMIC_RG_AUXADC_CALI_SHIFT},
	{PMIC_RG_VBUF_EN, PMIC_RG_VBUF_EN_ADDR, PMIC_RG_VBUF_EN_MASK,
	 PMIC_RG_VBUF_EN_SHIFT},
	{PMIC_RG_VBE_SEL, PMIC_RG_VBE_SEL_ADDR, PMIC_RG_VBE_SEL_MASK,
	 PMIC_RG_VBE_SEL_SHIFT},
	{PMIC_AUXADC_ADCIN_VSEN_EN, PMIC_AUXADC_ADCIN_VSEN_EN_ADDR,
	 PMIC_AUXADC_ADCIN_VSEN_EN_MASK, PMIC_AUXADC_ADCIN_VSEN_EN_SHIFT},
	{PMIC_AUXADC_ADCIN_VBAT_EN, PMIC_AUXADC_ADCIN_VBAT_EN_ADDR,
	 PMIC_AUXADC_ADCIN_VBAT_EN_MASK, PMIC_AUXADC_ADCIN_VBAT_EN_SHIFT},
	{PMIC_AUXADC_ADCIN_VSEN_MUX_EN, PMIC_AUXADC_ADCIN_VSEN_MUX_EN_ADDR,
	 PMIC_AUXADC_ADCIN_VSEN_MUX_EN_MASK, PMIC_AUXADC_ADCIN_VSEN_MUX_EN_SHIFT},
	{PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN, PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN_ADDR,
	 PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN_MASK,
	 PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN_SHIFT},
	{PMIC_AUXADC_ADCIN_CHR_EN, PMIC_AUXADC_ADCIN_CHR_EN_ADDR,
	 PMIC_AUXADC_ADCIN_CHR_EN_MASK, PMIC_AUXADC_ADCIN_CHR_EN_SHIFT},
	{PMIC_AUXADC_ADCIN_BATON_TDET_EN, PMIC_AUXADC_ADCIN_BATON_TDET_EN_ADDR,
	 PMIC_AUXADC_ADCIN_BATON_TDET_EN_MASK, PMIC_AUXADC_ADCIN_BATON_TDET_EN_SHIFT},
	{PMIC_AUXADC_ACCDET_ANASWCTRL_EN, PMIC_AUXADC_ACCDET_ANASWCTRL_EN_ADDR,
	 PMIC_AUXADC_ACCDET_ANASWCTRL_EN_MASK, PMIC_AUXADC_ACCDET_ANASWCTRL_EN_SHIFT},
	{PMIC_AUXADC_DIG0_RSV0, PMIC_AUXADC_DIG0_RSV0_ADDR,
	 PMIC_AUXADC_DIG0_RSV0_MASK, PMIC_AUXADC_DIG0_RSV0_SHIFT},
	{PMIC_AUXADC_CHSEL, PMIC_AUXADC_CHSEL_ADDR, PMIC_AUXADC_CHSEL_MASK,
	 PMIC_AUXADC_CHSEL_SHIFT},
	{PMIC_AUXADC_SWCTRL_EN, PMIC_AUXADC_SWCTRL_EN_ADDR,
	 PMIC_AUXADC_SWCTRL_EN_MASK, PMIC_AUXADC_SWCTRL_EN_SHIFT},
	{PMIC_AUXADC_SOURCE_LBAT_SEL, PMIC_AUXADC_SOURCE_LBAT_SEL_ADDR,
	 PMIC_AUXADC_SOURCE_LBAT_SEL_MASK, PMIC_AUXADC_SOURCE_LBAT_SEL_SHIFT},
	{PMIC_AUXADC_SOURCE_LBAT2_SEL, PMIC_AUXADC_SOURCE_LBAT2_SEL_ADDR,
	 PMIC_AUXADC_SOURCE_LBAT2_SEL_MASK, PMIC_AUXADC_SOURCE_LBAT2_SEL_SHIFT},
	{PMIC_AUXADC_DIG0_RSV2, PMIC_AUXADC_DIG0_RSV2_ADDR,
	 PMIC_AUXADC_DIG0_RSV2_MASK, PMIC_AUXADC_DIG0_RSV2_SHIFT},
	{PMIC_AUXADC_DIG1_RSV2, PMIC_AUXADC_DIG1_RSV2_ADDR,
	 PMIC_AUXADC_DIG1_RSV2_MASK, PMIC_AUXADC_DIG1_RSV2_SHIFT},
	{PMIC_AUXADC_DAC_EXTD, PMIC_AUXADC_DAC_EXTD_ADDR, PMIC_AUXADC_DAC_EXTD_MASK,
	 PMIC_AUXADC_DAC_EXTD_SHIFT},
	{PMIC_AUXADC_DAC_EXTD_EN, PMIC_AUXADC_DAC_EXTD_EN_ADDR,
	 PMIC_AUXADC_DAC_EXTD_EN_MASK, PMIC_AUXADC_DAC_EXTD_EN_SHIFT},
	{PMIC_AUXADC_PMU_THR_PDN_SW, PMIC_AUXADC_PMU_THR_PDN_SW_ADDR,
	 PMIC_AUXADC_PMU_THR_PDN_SW_MASK, PMIC_AUXADC_PMU_THR_PDN_SW_SHIFT},
	{PMIC_AUXADC_PMU_THR_PDN_SEL, PMIC_AUXADC_PMU_THR_PDN_SEL_ADDR,
	 PMIC_AUXADC_PMU_THR_PDN_SEL_MASK, PMIC_AUXADC_PMU_THR_PDN_SEL_SHIFT},
	{PMIC_AUXADC_PMU_THR_PDN_STATUS, PMIC_AUXADC_PMU_THR_PDN_STATUS_ADDR,
	 PMIC_AUXADC_PMU_THR_PDN_STATUS_MASK, PMIC_AUXADC_PMU_THR_PDN_STATUS_SHIFT},
	{PMIC_AUXADC_DIG0_RSV1, PMIC_AUXADC_DIG0_RSV1_ADDR,
	 PMIC_AUXADC_DIG0_RSV1_MASK, PMIC_AUXADC_DIG0_RSV1_SHIFT},
	{PMIC_AUXADC_START_SHADE_NUM, PMIC_AUXADC_START_SHADE_NUM_ADDR,
	 PMIC_AUXADC_START_SHADE_NUM_MASK, PMIC_AUXADC_START_SHADE_NUM_SHIFT},
	{PMIC_AUXADC_START_SHADE_EN, PMIC_AUXADC_START_SHADE_EN_ADDR,
	 PMIC_AUXADC_START_SHADE_EN_MASK, PMIC_AUXADC_START_SHADE_EN_SHIFT},
	{PMIC_AUXADC_START_SHADE_SEL, PMIC_AUXADC_START_SHADE_SEL_ADDR,
	 PMIC_AUXADC_START_SHADE_SEL_MASK, PMIC_AUXADC_START_SHADE_SEL_SHIFT},
	{PMIC_AUXADC_AUTORPT_PRD, PMIC_AUXADC_AUTORPT_PRD_ADDR,
	 PMIC_AUXADC_AUTORPT_PRD_MASK, PMIC_AUXADC_AUTORPT_PRD_SHIFT},
	{PMIC_AUXADC_AUTORPT_EN, PMIC_AUXADC_AUTORPT_EN_ADDR,
	 PMIC_AUXADC_AUTORPT_EN_MASK, PMIC_AUXADC_AUTORPT_EN_SHIFT},
	{PMIC_AUXADC_LBAT_DEBT_MAX, PMIC_AUXADC_LBAT_DEBT_MAX_ADDR,
	 PMIC_AUXADC_LBAT_DEBT_MAX_MASK, PMIC_AUXADC_LBAT_DEBT_MAX_SHIFT},
	{PMIC_AUXADC_LBAT_DEBT_MIN, PMIC_AUXADC_LBAT_DEBT_MIN_ADDR,
	 PMIC_AUXADC_LBAT_DEBT_MIN_MASK, PMIC_AUXADC_LBAT_DEBT_MIN_SHIFT},
	{PMIC_AUXADC_LBAT_DET_PRD_15_0, PMIC_AUXADC_LBAT_DET_PRD_15_0_ADDR,
	 PMIC_AUXADC_LBAT_DET_PRD_15_0_MASK, PMIC_AUXADC_LBAT_DET_PRD_15_0_SHIFT},
	{PMIC_AUXADC_LBAT_DET_PRD_19_16, PMIC_AUXADC_LBAT_DET_PRD_19_16_ADDR,
	 PMIC_AUXADC_LBAT_DET_PRD_19_16_MASK, PMIC_AUXADC_LBAT_DET_PRD_19_16_SHIFT},
	{PMIC_AUXADC_LBAT_VOLT_MAX, PMIC_AUXADC_LBAT_VOLT_MAX_ADDR,
	 PMIC_AUXADC_LBAT_VOLT_MAX_MASK, PMIC_AUXADC_LBAT_VOLT_MAX_SHIFT},
	{PMIC_AUXADC_LBAT_IRQ_EN_MAX, PMIC_AUXADC_LBAT_IRQ_EN_MAX_ADDR,
	 PMIC_AUXADC_LBAT_IRQ_EN_MAX_MASK, PMIC_AUXADC_LBAT_IRQ_EN_MAX_SHIFT},
	{PMIC_AUXADC_LBAT_EN_MAX, PMIC_AUXADC_LBAT_EN_MAX_ADDR,
	 PMIC_AUXADC_LBAT_EN_MAX_MASK, PMIC_AUXADC_LBAT_EN_MAX_SHIFT},
	{PMIC_AUXADC_LBAT_MAX_IRQ_B, PMIC_AUXADC_LBAT_MAX_IRQ_B_ADDR,
	 PMIC_AUXADC_LBAT_MAX_IRQ_B_MASK, PMIC_AUXADC_LBAT_MAX_IRQ_B_SHIFT},
	{PMIC_AUXADC_LBAT_VOLT_MIN, PMIC_AUXADC_LBAT_VOLT_MIN_ADDR,
	 PMIC_AUXADC_LBAT_VOLT_MIN_MASK, PMIC_AUXADC_LBAT_VOLT_MIN_SHIFT},
	{PMIC_AUXADC_LBAT_IRQ_EN_MIN, PMIC_AUXADC_LBAT_IRQ_EN_MIN_ADDR,
	 PMIC_AUXADC_LBAT_IRQ_EN_MIN_MASK, PMIC_AUXADC_LBAT_IRQ_EN_MIN_SHIFT},
	{PMIC_AUXADC_LBAT_EN_MIN, PMIC_AUXADC_LBAT_EN_MIN_ADDR,
	 PMIC_AUXADC_LBAT_EN_MIN_MASK, PMIC_AUXADC_LBAT_EN_MIN_SHIFT},
	{PMIC_AUXADC_LBAT_MIN_IRQ_B, PMIC_AUXADC_LBAT_MIN_IRQ_B_ADDR,
	 PMIC_AUXADC_LBAT_MIN_IRQ_B_MASK, PMIC_AUXADC_LBAT_MIN_IRQ_B_SHIFT},
	{PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX, PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX_ADDR,
	 PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX_MASK,
	 PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX_SHIFT},
	{PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN, PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN_ADDR,
	 PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN_MASK,
	 PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN_SHIFT},
	{PMIC_AUXADC_ACCDET_AUTO_SPL, PMIC_AUXADC_ACCDET_AUTO_SPL_ADDR,
	 PMIC_AUXADC_ACCDET_AUTO_SPL_MASK, PMIC_AUXADC_ACCDET_AUTO_SPL_SHIFT},
	{PMIC_AUXADC_ACCDET_AUTO_RQST_CLR, PMIC_AUXADC_ACCDET_AUTO_RQST_CLR_ADDR,
	 PMIC_AUXADC_ACCDET_AUTO_RQST_CLR_MASK,
	 PMIC_AUXADC_ACCDET_AUTO_RQST_CLR_SHIFT},
	{PMIC_AUXADC_ACCDET_DIG1_RSV0, PMIC_AUXADC_ACCDET_DIG1_RSV0_ADDR,
	 PMIC_AUXADC_ACCDET_DIG1_RSV0_MASK, PMIC_AUXADC_ACCDET_DIG1_RSV0_SHIFT},
	{PMIC_AUXADC_ACCDET_DIG0_RSV0, PMIC_AUXADC_ACCDET_DIG0_RSV0_ADDR,
	 PMIC_AUXADC_ACCDET_DIG0_RSV0_MASK, PMIC_AUXADC_ACCDET_DIG0_RSV0_SHIFT},
	{PMIC_AUXADC_THR_DEBT_MAX, PMIC_AUXADC_THR_DEBT_MAX_ADDR,
	 PMIC_AUXADC_THR_DEBT_MAX_MASK, PMIC_AUXADC_THR_DEBT_MAX_SHIFT},
	{PMIC_AUXADC_THR_DEBT_MIN, PMIC_AUXADC_THR_DEBT_MIN_ADDR,
	 PMIC_AUXADC_THR_DEBT_MIN_MASK, PMIC_AUXADC_THR_DEBT_MIN_SHIFT},
	{PMIC_AUXADC_THR_DET_PRD_15_0, PMIC_AUXADC_THR_DET_PRD_15_0_ADDR,
	 PMIC_AUXADC_THR_DET_PRD_15_0_MASK, PMIC_AUXADC_THR_DET_PRD_15_0_SHIFT},
	{PMIC_AUXADC_THR_DET_PRD_19_16, PMIC_AUXADC_THR_DET_PRD_19_16_ADDR,
	 PMIC_AUXADC_THR_DET_PRD_19_16_MASK, PMIC_AUXADC_THR_DET_PRD_19_16_SHIFT},
	{PMIC_AUXADC_THR_VOLT_MAX, PMIC_AUXADC_THR_VOLT_MAX_ADDR,
	 PMIC_AUXADC_THR_VOLT_MAX_MASK, PMIC_AUXADC_THR_VOLT_MAX_SHIFT},
	{PMIC_AUXADC_THR_IRQ_EN_MAX, PMIC_AUXADC_THR_IRQ_EN_MAX_ADDR,
	 PMIC_AUXADC_THR_IRQ_EN_MAX_MASK, PMIC_AUXADC_THR_IRQ_EN_MAX_SHIFT},
	{PMIC_AUXADC_THR_EN_MAX, PMIC_AUXADC_THR_EN_MAX_ADDR,
	 PMIC_AUXADC_THR_EN_MAX_MASK, PMIC_AUXADC_THR_EN_MAX_SHIFT},
	{PMIC_AUXADC_THR_MAX_IRQ_B, PMIC_AUXADC_THR_MAX_IRQ_B_ADDR,
	 PMIC_AUXADC_THR_MAX_IRQ_B_MASK, PMIC_AUXADC_THR_MAX_IRQ_B_SHIFT},
	{PMIC_AUXADC_THR_VOLT_MIN, PMIC_AUXADC_THR_VOLT_MIN_ADDR,
	 PMIC_AUXADC_THR_VOLT_MIN_MASK, PMIC_AUXADC_THR_VOLT_MIN_SHIFT},
	{PMIC_AUXADC_THR_IRQ_EN_MIN, PMIC_AUXADC_THR_IRQ_EN_MIN_ADDR,
	 PMIC_AUXADC_THR_IRQ_EN_MIN_MASK, PMIC_AUXADC_THR_IRQ_EN_MIN_SHIFT},
	{PMIC_AUXADC_THR_EN_MIN, PMIC_AUXADC_THR_EN_MIN_ADDR,
	 PMIC_AUXADC_THR_EN_MIN_MASK, PMIC_AUXADC_THR_EN_MIN_SHIFT},
	{PMIC_AUXADC_THR_MIN_IRQ_B, PMIC_AUXADC_THR_MIN_IRQ_B_ADDR,
	 PMIC_AUXADC_THR_MIN_IRQ_B_MASK, PMIC_AUXADC_THR_MIN_IRQ_B_SHIFT},
	{PMIC_AUXADC_THR_DEBOUNCE_COUNT_MAX, PMIC_AUXADC_THR_DEBOUNCE_COUNT_MAX_ADDR,
	 PMIC_AUXADC_THR_DEBOUNCE_COUNT_MAX_MASK,
	 PMIC_AUXADC_THR_DEBOUNCE_COUNT_MAX_SHIFT},
	{PMIC_AUXADC_THR_DEBOUNCE_COUNT_MIN, PMIC_AUXADC_THR_DEBOUNCE_COUNT_MIN_ADDR,
	 PMIC_AUXADC_THR_DEBOUNCE_COUNT_MIN_MASK,
	 PMIC_AUXADC_THR_DEBOUNCE_COUNT_MIN_SHIFT},
	{PMIC_EFUSE_GAIN_CH4_TRIM, PMIC_EFUSE_GAIN_CH4_TRIM_ADDR,
	 PMIC_EFUSE_GAIN_CH4_TRIM_MASK, PMIC_EFUSE_GAIN_CH4_TRIM_SHIFT},
	{PMIC_EFUSE_OFFSET_CH4_TRIM, PMIC_EFUSE_OFFSET_CH4_TRIM_ADDR,
	 PMIC_EFUSE_OFFSET_CH4_TRIM_MASK, PMIC_EFUSE_OFFSET_CH4_TRIM_SHIFT},
	{PMIC_EFUSE_GAIN_CH0_TRIM, PMIC_EFUSE_GAIN_CH0_TRIM_ADDR,
	 PMIC_EFUSE_GAIN_CH0_TRIM_MASK, PMIC_EFUSE_GAIN_CH0_TRIM_SHIFT},
	{PMIC_EFUSE_OFFSET_CH0_TRIM, PMIC_EFUSE_OFFSET_CH0_TRIM_ADDR,
	 PMIC_EFUSE_OFFSET_CH0_TRIM_MASK, PMIC_EFUSE_OFFSET_CH0_TRIM_SHIFT},
	{PMIC_EFUSE_GAIN_CH7_TRIM, PMIC_EFUSE_GAIN_CH7_TRIM_ADDR,
	 PMIC_EFUSE_GAIN_CH7_TRIM_MASK, PMIC_EFUSE_GAIN_CH7_TRIM_SHIFT},
	{PMIC_EFUSE_OFFSET_CH7_TRIM, PMIC_EFUSE_OFFSET_CH7_TRIM_ADDR,
	 PMIC_EFUSE_OFFSET_CH7_TRIM_MASK, PMIC_EFUSE_OFFSET_CH7_TRIM_SHIFT},
	{PMIC_AUXADC_FGADC_START_SW, PMIC_AUXADC_FGADC_START_SW_ADDR,
	 PMIC_AUXADC_FGADC_START_SW_MASK, PMIC_AUXADC_FGADC_START_SW_SHIFT},
	{PMIC_AUXADC_FGADC_START_SEL, PMIC_AUXADC_FGADC_START_SEL_ADDR,
	 PMIC_AUXADC_FGADC_START_SEL_MASK, PMIC_AUXADC_FGADC_START_SEL_SHIFT},
	{PMIC_AUXADC_FGADC_R_SW, PMIC_AUXADC_FGADC_R_SW_ADDR,
	 PMIC_AUXADC_FGADC_R_SW_MASK, PMIC_AUXADC_FGADC_R_SW_SHIFT},
	{PMIC_AUXADC_FGADC_R_SEL, PMIC_AUXADC_FGADC_R_SEL_ADDR,
	 PMIC_AUXADC_FGADC_R_SEL_MASK, PMIC_AUXADC_FGADC_R_SEL_SHIFT},
	{PMIC_AUXADC_DBG_DIG0_RSV2, PMIC_AUXADC_DBG_DIG0_RSV2_ADDR,
	 PMIC_AUXADC_DBG_DIG0_RSV2_MASK, PMIC_AUXADC_DBG_DIG0_RSV2_SHIFT},
	{PMIC_AUXADC_DBG_DIG1_RSV2, PMIC_AUXADC_DBG_DIG1_RSV2_ADDR,
	 PMIC_AUXADC_DBG_DIG1_RSV2_MASK, PMIC_AUXADC_DBG_DIG1_RSV2_SHIFT},
	{PMIC_AUXADC_IMPEDANCE_CNT, PMIC_AUXADC_IMPEDANCE_CNT_ADDR,
	 PMIC_AUXADC_IMPEDANCE_CNT_MASK, PMIC_AUXADC_IMPEDANCE_CNT_SHIFT},
	{PMIC_AUXADC_IMPEDANCE_CHSEL, PMIC_AUXADC_IMPEDANCE_CHSEL_ADDR,
	 PMIC_AUXADC_IMPEDANCE_CHSEL_MASK, PMIC_AUXADC_IMPEDANCE_CHSEL_SHIFT},
	{PMIC_AUXADC_IMPEDANCE_IRQ_CLR, PMIC_AUXADC_IMPEDANCE_IRQ_CLR_ADDR,
	 PMIC_AUXADC_IMPEDANCE_IRQ_CLR_MASK, PMIC_AUXADC_IMPEDANCE_IRQ_CLR_SHIFT},
	{PMIC_AUXADC_IMPEDANCE_IRQ_STATUS, PMIC_AUXADC_IMPEDANCE_IRQ_STATUS_ADDR,
	 PMIC_AUXADC_IMPEDANCE_IRQ_STATUS_MASK,
	 PMIC_AUXADC_IMPEDANCE_IRQ_STATUS_SHIFT},
	{PMIC_AUXADC_CLR_IMP_CNT_STOP, PMIC_AUXADC_CLR_IMP_CNT_STOP_ADDR,
	 PMIC_AUXADC_CLR_IMP_CNT_STOP_MASK, PMIC_AUXADC_CLR_IMP_CNT_STOP_SHIFT},
	{PMIC_AUXADC_IMPEDANCE_MODE, PMIC_AUXADC_IMPEDANCE_MODE_ADDR,
	 PMIC_AUXADC_IMPEDANCE_MODE_MASK, PMIC_AUXADC_IMPEDANCE_MODE_SHIFT},
	{PMIC_AUXADC_IMP_AUTORPT_PRD, PMIC_AUXADC_IMP_AUTORPT_PRD_ADDR,
	 PMIC_AUXADC_IMP_AUTORPT_PRD_MASK, PMIC_AUXADC_IMP_AUTORPT_PRD_SHIFT},
	{PMIC_AUXADC_IMP_AUTORPT_EN, PMIC_AUXADC_IMP_AUTORPT_EN_ADDR,
	 PMIC_AUXADC_IMP_AUTORPT_EN_MASK, PMIC_AUXADC_IMP_AUTORPT_EN_SHIFT},
	{PMIC_AUXADC_VISMPS0_DEBT_MAX, PMIC_AUXADC_VISMPS0_DEBT_MAX_ADDR,
	 PMIC_AUXADC_VISMPS0_DEBT_MAX_MASK, PMIC_AUXADC_VISMPS0_DEBT_MAX_SHIFT},
	{PMIC_AUXADC_VISMPS0_DEBT_MIN, PMIC_AUXADC_VISMPS0_DEBT_MIN_ADDR,
	 PMIC_AUXADC_VISMPS0_DEBT_MIN_MASK, PMIC_AUXADC_VISMPS0_DEBT_MIN_SHIFT},
	{PMIC_AUXADC_VISMPS0_DET_PRD_15_0, PMIC_AUXADC_VISMPS0_DET_PRD_15_0_ADDR,
	 PMIC_AUXADC_VISMPS0_DET_PRD_15_0_MASK,
	 PMIC_AUXADC_VISMPS0_DET_PRD_15_0_SHIFT},
	{PMIC_AUXADC_VISMPS0_DET_PRD_19_16, PMIC_AUXADC_VISMPS0_DET_PRD_19_16_ADDR,
	 PMIC_AUXADC_VISMPS0_DET_PRD_19_16_MASK,
	 PMIC_AUXADC_VISMPS0_DET_PRD_19_16_SHIFT},
	{PMIC_AUXADC_VISMPS0_VOLT_MAX, PMIC_AUXADC_VISMPS0_VOLT_MAX_ADDR,
	 PMIC_AUXADC_VISMPS0_VOLT_MAX_MASK, PMIC_AUXADC_VISMPS0_VOLT_MAX_SHIFT},
	{PMIC_AUXADC_VISMPS0_IRQ_EN_MAX, PMIC_AUXADC_VISMPS0_IRQ_EN_MAX_ADDR,
	 PMIC_AUXADC_VISMPS0_IRQ_EN_MAX_MASK, PMIC_AUXADC_VISMPS0_IRQ_EN_MAX_SHIFT},
	{PMIC_AUXADC_VISMPS0_EN_MAX, PMIC_AUXADC_VISMPS0_EN_MAX_ADDR,
	 PMIC_AUXADC_VISMPS0_EN_MAX_MASK, PMIC_AUXADC_VISMPS0_EN_MAX_SHIFT},
	{PMIC_AUXADC_VISMPS0_MAX_IRQ_B, PMIC_AUXADC_VISMPS0_MAX_IRQ_B_ADDR,
	 PMIC_AUXADC_VISMPS0_MAX_IRQ_B_MASK, PMIC_AUXADC_VISMPS0_MAX_IRQ_B_SHIFT},
	{PMIC_AUXADC_VISMPS0_VOLT_MIN, PMIC_AUXADC_VISMPS0_VOLT_MIN_ADDR,
	 PMIC_AUXADC_VISMPS0_VOLT_MIN_MASK, PMIC_AUXADC_VISMPS0_VOLT_MIN_SHIFT},
	{PMIC_AUXADC_VISMPS0_IRQ_EN_MIN, PMIC_AUXADC_VISMPS0_IRQ_EN_MIN_ADDR,
	 PMIC_AUXADC_VISMPS0_IRQ_EN_MIN_MASK, PMIC_AUXADC_VISMPS0_IRQ_EN_MIN_SHIFT},
	{PMIC_AUXADC_VISMPS0_EN_MIN, PMIC_AUXADC_VISMPS0_EN_MIN_ADDR,
	 PMIC_AUXADC_VISMPS0_EN_MIN_MASK, PMIC_AUXADC_VISMPS0_EN_MIN_SHIFT},
	{PMIC_AUXADC_VISMPS0_MIN_IRQ_B, PMIC_AUXADC_VISMPS0_MIN_IRQ_B_ADDR,
	 PMIC_AUXADC_VISMPS0_MIN_IRQ_B_MASK, PMIC_AUXADC_VISMPS0_MIN_IRQ_B_SHIFT},
	{PMIC_AUXADC_VISMPS0_DEBOUNCE_COUNT_MAX, PMIC_AUXADC_VISMPS0_DEBOUNCE_COUNT_MAX_ADDR,
	 PMIC_AUXADC_VISMPS0_DEBOUNCE_COUNT_MAX_MASK,
	 PMIC_AUXADC_VISMPS0_DEBOUNCE_COUNT_MAX_SHIFT},
	{PMIC_AUXADC_VISMPS0_DEBOUNCE_COUNT_MIN, PMIC_AUXADC_VISMPS0_DEBOUNCE_COUNT_MIN_ADDR,
	 PMIC_AUXADC_VISMPS0_DEBOUNCE_COUNT_MIN_MASK,
	 PMIC_AUXADC_VISMPS0_DEBOUNCE_COUNT_MIN_SHIFT},
	{PMIC_AUXADC_LBAT2_DEBT_MAX, PMIC_AUXADC_LBAT2_DEBT_MAX_ADDR,
	 PMIC_AUXADC_LBAT2_DEBT_MAX_MASK, PMIC_AUXADC_LBAT2_DEBT_MAX_SHIFT},
	{PMIC_AUXADC_LBAT2_DEBT_MIN, PMIC_AUXADC_LBAT2_DEBT_MIN_ADDR,
	 PMIC_AUXADC_LBAT2_DEBT_MIN_MASK, PMIC_AUXADC_LBAT2_DEBT_MIN_SHIFT},
	{PMIC_AUXADC_LBAT2_DET_PRD_15_0, PMIC_AUXADC_LBAT2_DET_PRD_15_0_ADDR,
	 PMIC_AUXADC_LBAT2_DET_PRD_15_0_MASK, PMIC_AUXADC_LBAT2_DET_PRD_15_0_SHIFT},
	{PMIC_AUXADC_LBAT2_DET_PRD_19_16, PMIC_AUXADC_LBAT2_DET_PRD_19_16_ADDR,
	 PMIC_AUXADC_LBAT2_DET_PRD_19_16_MASK, PMIC_AUXADC_LBAT2_DET_PRD_19_16_SHIFT},
	{PMIC_AUXADC_LBAT2_VOLT_MAX, PMIC_AUXADC_LBAT2_VOLT_MAX_ADDR,
	 PMIC_AUXADC_LBAT2_VOLT_MAX_MASK, PMIC_AUXADC_LBAT2_VOLT_MAX_SHIFT},
	{PMIC_AUXADC_LBAT2_IRQ_EN_MAX, PMIC_AUXADC_LBAT2_IRQ_EN_MAX_ADDR,
	 PMIC_AUXADC_LBAT2_IRQ_EN_MAX_MASK, PMIC_AUXADC_LBAT2_IRQ_EN_MAX_SHIFT},
	{PMIC_AUXADC_LBAT2_EN_MAX, PMIC_AUXADC_LBAT2_EN_MAX_ADDR,
	 PMIC_AUXADC_LBAT2_EN_MAX_MASK, PMIC_AUXADC_LBAT2_EN_MAX_SHIFT},
	{PMIC_AUXADC_LBAT2_MAX_IRQ_B, PMIC_AUXADC_LBAT2_MAX_IRQ_B_ADDR,
	 PMIC_AUXADC_LBAT2_MAX_IRQ_B_MASK, PMIC_AUXADC_LBAT2_MAX_IRQ_B_SHIFT},
	{PMIC_AUXADC_LBAT2_VOLT_MIN, PMIC_AUXADC_LBAT2_VOLT_MIN_ADDR,
	 PMIC_AUXADC_LBAT2_VOLT_MIN_MASK, PMIC_AUXADC_LBAT2_VOLT_MIN_SHIFT},
	{PMIC_AUXADC_LBAT2_IRQ_EN_MIN, PMIC_AUXADC_LBAT2_IRQ_EN_MIN_ADDR,
	 PMIC_AUXADC_LBAT2_IRQ_EN_MIN_MASK, PMIC_AUXADC_LBAT2_IRQ_EN_MIN_SHIFT},
	{PMIC_AUXADC_LBAT2_EN_MIN, PMIC_AUXADC_LBAT2_EN_MIN_ADDR,
	 PMIC_AUXADC_LBAT2_EN_MIN_MASK, PMIC_AUXADC_LBAT2_EN_MIN_SHIFT},
	{PMIC_AUXADC_LBAT2_MIN_IRQ_B, PMIC_AUXADC_LBAT2_MIN_IRQ_B_ADDR,
	 PMIC_AUXADC_LBAT2_MIN_IRQ_B_MASK, PMIC_AUXADC_LBAT2_MIN_IRQ_B_SHIFT},
	{PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX, PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_ADDR,
	 PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_MASK,
	 PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_SHIFT},
	{PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN, PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_ADDR,
	 PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_MASK,
	 PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_SHIFT},
	{PMIC_AUXADC_MDBG_DET_PRD, PMIC_AUXADC_MDBG_DET_PRD_ADDR,
	 PMIC_AUXADC_MDBG_DET_PRD_MASK, PMIC_AUXADC_MDBG_DET_PRD_SHIFT},
	{PMIC_AUXADC_MDBG_DET_EN, PMIC_AUXADC_MDBG_DET_EN_ADDR,
	 PMIC_AUXADC_MDBG_DET_EN_MASK, PMIC_AUXADC_MDBG_DET_EN_SHIFT},
	{PMIC_AUXADC_MDBG_R_PTR, PMIC_AUXADC_MDBG_R_PTR_ADDR,
	 PMIC_AUXADC_MDBG_R_PTR_MASK, PMIC_AUXADC_MDBG_R_PTR_SHIFT},
	{PMIC_AUXADC_MDBG_W_PTR, PMIC_AUXADC_MDBG_W_PTR_ADDR,
	 PMIC_AUXADC_MDBG_W_PTR_MASK, PMIC_AUXADC_MDBG_W_PTR_SHIFT},
	{PMIC_AUXADC_MDBG_BUF_LENGTH, PMIC_AUXADC_MDBG_BUF_LENGTH_ADDR,
	 PMIC_AUXADC_MDBG_BUF_LENGTH_MASK, PMIC_AUXADC_MDBG_BUF_LENGTH_SHIFT},
	{PMIC_AUXADC_MDRT_DET_PRD, PMIC_AUXADC_MDRT_DET_PRD_ADDR,
	 PMIC_AUXADC_MDRT_DET_PRD_MASK, PMIC_AUXADC_MDRT_DET_PRD_SHIFT},
	{PMIC_AUXADC_MDRT_DET_EN, PMIC_AUXADC_MDRT_DET_EN_ADDR,
	 PMIC_AUXADC_MDRT_DET_EN_MASK, PMIC_AUXADC_MDRT_DET_EN_SHIFT},
	{PMIC_AUXADC_MDRT_DET_WKUP_START_CNT, PMIC_AUXADC_MDRT_DET_WKUP_START_CNT_ADDR,
	 PMIC_AUXADC_MDRT_DET_WKUP_START_CNT_MASK,
	 PMIC_AUXADC_MDRT_DET_WKUP_START_CNT_SHIFT},
	{PMIC_AUXADC_MDRT_DET_WKUP_START_CLR, PMIC_AUXADC_MDRT_DET_WKUP_START_CLR_ADDR,
	 PMIC_AUXADC_MDRT_DET_WKUP_START_CLR_MASK,
	 PMIC_AUXADC_MDRT_DET_WKUP_START_CLR_SHIFT},
	{PMIC_AUXADC_MDRT_DET_WKUP_START, PMIC_AUXADC_MDRT_DET_WKUP_START_ADDR,
	 PMIC_AUXADC_MDRT_DET_WKUP_START_MASK, PMIC_AUXADC_MDRT_DET_WKUP_START_SHIFT},
	{PMIC_AUXADC_MDRT_DET_WKUP_START_SEL, PMIC_AUXADC_MDRT_DET_WKUP_START_SEL_ADDR,
	 PMIC_AUXADC_MDRT_DET_WKUP_START_SEL_MASK,
	 PMIC_AUXADC_MDRT_DET_WKUP_START_SEL_SHIFT},
	{PMIC_AUXADC_MDRT_DET_WKUP_EN, PMIC_AUXADC_MDRT_DET_WKUP_EN_ADDR,
	 PMIC_AUXADC_MDRT_DET_WKUP_EN_MASK, PMIC_AUXADC_MDRT_DET_WKUP_EN_SHIFT},
	{PMIC_AUXADC_MDRT_DET_SRCLKEN_IND, PMIC_AUXADC_MDRT_DET_SRCLKEN_IND_ADDR,
	 PMIC_AUXADC_MDRT_DET_SRCLKEN_IND_MASK,
	 PMIC_AUXADC_MDRT_DET_SRCLKEN_IND_SHIFT},
	{PMIC_AUXADC_DCXO_MDRT_DET_PRD, PMIC_AUXADC_DCXO_MDRT_DET_PRD_ADDR,
	 PMIC_AUXADC_DCXO_MDRT_DET_PRD_MASK, PMIC_AUXADC_DCXO_MDRT_DET_PRD_SHIFT},
	{PMIC_AUXADC_DCXO_MDRT_DET_EN, PMIC_AUXADC_DCXO_MDRT_DET_EN_ADDR,
	 PMIC_AUXADC_DCXO_MDRT_DET_EN_MASK, PMIC_AUXADC_DCXO_MDRT_DET_EN_SHIFT},
	{PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT,
	 PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT_ADDR,
	 PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT_MASK,
	 PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT_SHIFT},
	{PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR,
	 PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR_ADDR,
	 PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR_MASK,
	 PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR_SHIFT},
	{PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN, PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN_ADDR,
	 PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN_MASK,
	 PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN_SHIFT},
	{PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL,
	 PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL_ADDR,
	 PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL_MASK,
	 PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL_SHIFT},
	{PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START, PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_ADDR,
	 PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_MASK,
	 PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SHIFT},
	{PMIC_AUXADC_DCXO_MDRT_DET_SRCLKEN_IND, PMIC_AUXADC_DCXO_MDRT_DET_SRCLKEN_IND_ADDR,
	 PMIC_AUXADC_DCXO_MDRT_DET_SRCLKEN_IND_MASK,
	 PMIC_AUXADC_DCXO_MDRT_DET_SRCLKEN_IND_SHIFT},
	{PMIC_AUXADC_DCXO_CH4_MUX_AP_SEL, PMIC_AUXADC_DCXO_CH4_MUX_AP_SEL_ADDR,
	 PMIC_AUXADC_DCXO_CH4_MUX_AP_SEL_MASK, PMIC_AUXADC_DCXO_CH4_MUX_AP_SEL_SHIFT},
	{PMIC_AUXADC_NAG_EN, PMIC_AUXADC_NAG_EN_ADDR, PMIC_AUXADC_NAG_EN_MASK,
	 PMIC_AUXADC_NAG_EN_SHIFT},
	{PMIC_AUXADC_NAG_CLR, PMIC_AUXADC_NAG_CLR_ADDR, PMIC_AUXADC_NAG_CLR_MASK,
	 PMIC_AUXADC_NAG_CLR_SHIFT},
	{PMIC_AUXADC_NAG_VBAT1_SEL, PMIC_AUXADC_NAG_VBAT1_SEL_ADDR,
	 PMIC_AUXADC_NAG_VBAT1_SEL_MASK, PMIC_AUXADC_NAG_VBAT1_SEL_SHIFT},
	{PMIC_AUXADC_NAG_PRD, PMIC_AUXADC_NAG_PRD_ADDR, PMIC_AUXADC_NAG_PRD_MASK,
	 PMIC_AUXADC_NAG_PRD_SHIFT},
	{PMIC_AUXADC_NAG_IRQ_EN, PMIC_AUXADC_NAG_IRQ_EN_ADDR,
	 PMIC_AUXADC_NAG_IRQ_EN_MASK, PMIC_AUXADC_NAG_IRQ_EN_SHIFT},
	{PMIC_AUXADC_NAG_C_DLTV_IRQ, PMIC_AUXADC_NAG_C_DLTV_IRQ_ADDR,
	 PMIC_AUXADC_NAG_C_DLTV_IRQ_MASK, PMIC_AUXADC_NAG_C_DLTV_IRQ_SHIFT},
	{PMIC_AUXADC_NAG_ZCV, PMIC_AUXADC_NAG_ZCV_ADDR, PMIC_AUXADC_NAG_ZCV_MASK,
	 PMIC_AUXADC_NAG_ZCV_SHIFT},
	{PMIC_AUXADC_NAG_C_DLTV_TH_15_0, PMIC_AUXADC_NAG_C_DLTV_TH_15_0_ADDR,
	 PMIC_AUXADC_NAG_C_DLTV_TH_15_0_MASK, PMIC_AUXADC_NAG_C_DLTV_TH_15_0_SHIFT},
	{PMIC_AUXADC_NAG_C_DLTV_TH_26_16, PMIC_AUXADC_NAG_C_DLTV_TH_26_16_ADDR,
	 PMIC_AUXADC_NAG_C_DLTV_TH_26_16_MASK, PMIC_AUXADC_NAG_C_DLTV_TH_26_16_SHIFT},
	{PMIC_AUXADC_NAG_CNT_15_0, PMIC_AUXADC_NAG_CNT_15_0_ADDR,
	 PMIC_AUXADC_NAG_CNT_15_0_MASK, PMIC_AUXADC_NAG_CNT_15_0_SHIFT},
	{PMIC_AUXADC_NAG_CNT_25_16, PMIC_AUXADC_NAG_CNT_25_16_ADDR,
	 PMIC_AUXADC_NAG_CNT_25_16_MASK, PMIC_AUXADC_NAG_CNT_25_16_SHIFT},
	{PMIC_AUXADC_NAG_DLTV, PMIC_AUXADC_NAG_DLTV_ADDR, PMIC_AUXADC_NAG_DLTV_MASK,
	 PMIC_AUXADC_NAG_DLTV_SHIFT},
	{PMIC_AUXADC_NAG_C_DLTV_15_0, PMIC_AUXADC_NAG_C_DLTV_15_0_ADDR,
	 PMIC_AUXADC_NAG_C_DLTV_15_0_MASK, PMIC_AUXADC_NAG_C_DLTV_15_0_SHIFT},
	{PMIC_AUXADC_NAG_C_DLTV_26_16, PMIC_AUXADC_NAG_C_DLTV_26_16_ADDR,
	 PMIC_AUXADC_NAG_C_DLTV_26_16_MASK, PMIC_AUXADC_NAG_C_DLTV_26_16_SHIFT},
	{PMIC_AUXADC_TYPEC_H_DEBT_MAX, PMIC_AUXADC_TYPEC_H_DEBT_MAX_ADDR,
	 PMIC_AUXADC_TYPEC_H_DEBT_MAX_MASK, PMIC_AUXADC_TYPEC_H_DEBT_MAX_SHIFT},
	{PMIC_AUXADC_TYPEC_H_DEBT_MIN, PMIC_AUXADC_TYPEC_H_DEBT_MIN_ADDR,
	 PMIC_AUXADC_TYPEC_H_DEBT_MIN_MASK, PMIC_AUXADC_TYPEC_H_DEBT_MIN_SHIFT},
	{PMIC_AUXADC_TYPEC_H_DET_PRD_15_0, PMIC_AUXADC_TYPEC_H_DET_PRD_15_0_ADDR,
	 PMIC_AUXADC_TYPEC_H_DET_PRD_15_0_MASK,
	 PMIC_AUXADC_TYPEC_H_DET_PRD_15_0_SHIFT},
	{PMIC_AUXADC_TYPEC_H_DET_PRD_19_16, PMIC_AUXADC_TYPEC_H_DET_PRD_19_16_ADDR,
	 PMIC_AUXADC_TYPEC_H_DET_PRD_19_16_MASK,
	 PMIC_AUXADC_TYPEC_H_DET_PRD_19_16_SHIFT},
	{PMIC_AUXADC_TYPEC_H_VOLT_MAX, PMIC_AUXADC_TYPEC_H_VOLT_MAX_ADDR,
	 PMIC_AUXADC_TYPEC_H_VOLT_MAX_MASK, PMIC_AUXADC_TYPEC_H_VOLT_MAX_SHIFT},
	{PMIC_AUXADC_TYPEC_H_IRQ_EN_MAX, PMIC_AUXADC_TYPEC_H_IRQ_EN_MAX_ADDR,
	 PMIC_AUXADC_TYPEC_H_IRQ_EN_MAX_MASK, PMIC_AUXADC_TYPEC_H_IRQ_EN_MAX_SHIFT},
	{PMIC_AUXADC_TYPEC_H_EN_MAX, PMIC_AUXADC_TYPEC_H_EN_MAX_ADDR,
	 PMIC_AUXADC_TYPEC_H_EN_MAX_MASK, PMIC_AUXADC_TYPEC_H_EN_MAX_SHIFT},
	{PMIC_AUXADC_TYPEC_H_MAX_IRQ_B, PMIC_AUXADC_TYPEC_H_MAX_IRQ_B_ADDR,
	 PMIC_AUXADC_TYPEC_H_MAX_IRQ_B_MASK, PMIC_AUXADC_TYPEC_H_MAX_IRQ_B_SHIFT},
	{PMIC_AUXADC_TYPEC_H_VOLT_MIN, PMIC_AUXADC_TYPEC_H_VOLT_MIN_ADDR,
	 PMIC_AUXADC_TYPEC_H_VOLT_MIN_MASK, PMIC_AUXADC_TYPEC_H_VOLT_MIN_SHIFT},
	{PMIC_AUXADC_TYPEC_H_IRQ_EN_MIN, PMIC_AUXADC_TYPEC_H_IRQ_EN_MIN_ADDR,
	 PMIC_AUXADC_TYPEC_H_IRQ_EN_MIN_MASK, PMIC_AUXADC_TYPEC_H_IRQ_EN_MIN_SHIFT},
	{PMIC_AUXADC_TYPEC_H_EN_MIN, PMIC_AUXADC_TYPEC_H_EN_MIN_ADDR,
	 PMIC_AUXADC_TYPEC_H_EN_MIN_MASK, PMIC_AUXADC_TYPEC_H_EN_MIN_SHIFT},
	{PMIC_AUXADC_TYPEC_H_MIN_IRQ_B, PMIC_AUXADC_TYPEC_H_MIN_IRQ_B_ADDR,
	 PMIC_AUXADC_TYPEC_H_MIN_IRQ_B_MASK, PMIC_AUXADC_TYPEC_H_MIN_IRQ_B_SHIFT},
	{PMIC_AUXADC_TYPEC_H_DEBOUNCE_COUNT_MAX, PMIC_AUXADC_TYPEC_H_DEBOUNCE_COUNT_MAX_ADDR,
	 PMIC_AUXADC_TYPEC_H_DEBOUNCE_COUNT_MAX_MASK,
	 PMIC_AUXADC_TYPEC_H_DEBOUNCE_COUNT_MAX_SHIFT},
	{PMIC_AUXADC_TYPEC_H_DEBOUNCE_COUNT_MIN, PMIC_AUXADC_TYPEC_H_DEBOUNCE_COUNT_MIN_ADDR,
	 PMIC_AUXADC_TYPEC_H_DEBOUNCE_COUNT_MIN_MASK,
	 PMIC_AUXADC_TYPEC_H_DEBOUNCE_COUNT_MIN_SHIFT},
	{PMIC_AUXADC_TYPEC_L_DEBT_MAX, PMIC_AUXADC_TYPEC_L_DEBT_MAX_ADDR,
	 PMIC_AUXADC_TYPEC_L_DEBT_MAX_MASK, PMIC_AUXADC_TYPEC_L_DEBT_MAX_SHIFT},
	{PMIC_AUXADC_TYPEC_L_DEBT_MIN, PMIC_AUXADC_TYPEC_L_DEBT_MIN_ADDR,
	 PMIC_AUXADC_TYPEC_L_DEBT_MIN_MASK, PMIC_AUXADC_TYPEC_L_DEBT_MIN_SHIFT},
	{PMIC_AUXADC_TYPEC_L_DET_PRD_15_0, PMIC_AUXADC_TYPEC_L_DET_PRD_15_0_ADDR,
	 PMIC_AUXADC_TYPEC_L_DET_PRD_15_0_MASK,
	 PMIC_AUXADC_TYPEC_L_DET_PRD_15_0_SHIFT},
	{PMIC_AUXADC_TYPEC_L_DET_PRD_19_16, PMIC_AUXADC_TYPEC_L_DET_PRD_19_16_ADDR,
	 PMIC_AUXADC_TYPEC_L_DET_PRD_19_16_MASK,
	 PMIC_AUXADC_TYPEC_L_DET_PRD_19_16_SHIFT},
	{PMIC_AUXADC_TYPEC_L_VOLT_MAX, PMIC_AUXADC_TYPEC_L_VOLT_MAX_ADDR,
	 PMIC_AUXADC_TYPEC_L_VOLT_MAX_MASK, PMIC_AUXADC_TYPEC_L_VOLT_MAX_SHIFT},
	{PMIC_AUXADC_TYPEC_L_IRQ_EN_MAX, PMIC_AUXADC_TYPEC_L_IRQ_EN_MAX_ADDR,
	 PMIC_AUXADC_TYPEC_L_IRQ_EN_MAX_MASK, PMIC_AUXADC_TYPEC_L_IRQ_EN_MAX_SHIFT},
	{PMIC_AUXADC_TYPEC_L_EN_MAX, PMIC_AUXADC_TYPEC_L_EN_MAX_ADDR,
	 PMIC_AUXADC_TYPEC_L_EN_MAX_MASK, PMIC_AUXADC_TYPEC_L_EN_MAX_SHIFT},
	{PMIC_AUXADC_TYPEC_L_MAX_IRQ_B, PMIC_AUXADC_TYPEC_L_MAX_IRQ_B_ADDR,
	 PMIC_AUXADC_TYPEC_L_MAX_IRQ_B_MASK, PMIC_AUXADC_TYPEC_L_MAX_IRQ_B_SHIFT},
	{PMIC_AUXADC_TYPEC_L_VOLT_MIN, PMIC_AUXADC_TYPEC_L_VOLT_MIN_ADDR,
	 PMIC_AUXADC_TYPEC_L_VOLT_MIN_MASK, PMIC_AUXADC_TYPEC_L_VOLT_MIN_SHIFT},
	{PMIC_AUXADC_TYPEC_L_IRQ_EN_MIN, PMIC_AUXADC_TYPEC_L_IRQ_EN_MIN_ADDR,
	 PMIC_AUXADC_TYPEC_L_IRQ_EN_MIN_MASK, PMIC_AUXADC_TYPEC_L_IRQ_EN_MIN_SHIFT},
	{PMIC_AUXADC_TYPEC_L_EN_MIN, PMIC_AUXADC_TYPEC_L_EN_MIN_ADDR,
	 PMIC_AUXADC_TYPEC_L_EN_MIN_MASK, PMIC_AUXADC_TYPEC_L_EN_MIN_SHIFT},
	{PMIC_AUXADC_TYPEC_L_MIN_IRQ_B, PMIC_AUXADC_TYPEC_L_MIN_IRQ_B_ADDR,
	 PMIC_AUXADC_TYPEC_L_MIN_IRQ_B_MASK, PMIC_AUXADC_TYPEC_L_MIN_IRQ_B_SHIFT},
	{PMIC_AUXADC_TYPEC_L_DEBOUNCE_COUNT_MAX, PMIC_AUXADC_TYPEC_L_DEBOUNCE_COUNT_MAX_ADDR,
	 PMIC_AUXADC_TYPEC_L_DEBOUNCE_COUNT_MAX_MASK,
	 PMIC_AUXADC_TYPEC_L_DEBOUNCE_COUNT_MAX_SHIFT},
	{PMIC_AUXADC_TYPEC_L_DEBOUNCE_COUNT_MIN, PMIC_AUXADC_TYPEC_L_DEBOUNCE_COUNT_MIN_ADDR,
	 PMIC_AUXADC_TYPEC_L_DEBOUNCE_COUNT_MIN_MASK,
	 PMIC_AUXADC_TYPEC_L_DEBOUNCE_COUNT_MIN_SHIFT},
	{PMIC_RG_AUDACCDETVTHBCAL, PMIC_RG_AUDACCDETVTHBCAL_ADDR,
	 PMIC_RG_AUDACCDETVTHBCAL_MASK, PMIC_RG_AUDACCDETVTHBCAL_SHIFT},
	{PMIC_RG_AUDACCDETVTHACAL, PMIC_RG_AUDACCDETVTHACAL_ADDR,
	 PMIC_RG_AUDACCDETVTHACAL_MASK, PMIC_RG_AUDACCDETVTHACAL_SHIFT},
	{PMIC_RG_AUDACCDETANASWCTRLENB, PMIC_RG_AUDACCDETANASWCTRLENB_ADDR,
	 PMIC_RG_AUDACCDETANASWCTRLENB_MASK, PMIC_RG_AUDACCDETANASWCTRLENB_SHIFT},
	{PMIC_RG_ACCDETSEL, PMIC_RG_ACCDETSEL_ADDR, PMIC_RG_ACCDETSEL_MASK,
	 PMIC_RG_ACCDETSEL_SHIFT},
	{PMIC_RG_AUDACCDETSWCTRL, PMIC_RG_AUDACCDETSWCTRL_ADDR,
	 PMIC_RG_AUDACCDETSWCTRL_MASK, PMIC_RG_AUDACCDETSWCTRL_SHIFT},
	{PMIC_RG_AUDACCDETMICBIAS1PULLLOW, PMIC_RG_AUDACCDETMICBIAS1PULLLOW_ADDR,
	 PMIC_RG_AUDACCDETMICBIAS1PULLLOW_MASK,
	 PMIC_RG_AUDACCDETMICBIAS1PULLLOW_SHIFT},
	{PMIC_RG_AUDACCDETTVDET, PMIC_RG_AUDACCDETTVDET_ADDR,
	 PMIC_RG_AUDACCDETTVDET_MASK, PMIC_RG_AUDACCDETTVDET_SHIFT},
	{PMIC_RG_AUDACCDETVIN1PULLLOW, PMIC_RG_AUDACCDETVIN1PULLLOW_ADDR,
	 PMIC_RG_AUDACCDETVIN1PULLLOW_MASK, PMIC_RG_AUDACCDETVIN1PULLLOW_SHIFT},
	{PMIC_AUDACCDETAUXADCSWCTRL, PMIC_AUDACCDETAUXADCSWCTRL_ADDR,
	 PMIC_AUDACCDETAUXADCSWCTRL_MASK, PMIC_AUDACCDETAUXADCSWCTRL_SHIFT},
	{PMIC_AUDACCDETAUXADCSWCTRL_SEL, PMIC_AUDACCDETAUXADCSWCTRL_SEL_ADDR,
	 PMIC_AUDACCDETAUXADCSWCTRL_SEL_MASK, PMIC_AUDACCDETAUXADCSWCTRL_SEL_SHIFT},
	{PMIC_RG_AUDACCDETMICBIAS0PULLLOW, PMIC_RG_AUDACCDETMICBIAS0PULLLOW_ADDR,
	 PMIC_RG_AUDACCDETMICBIAS0PULLLOW_MASK,
	 PMIC_RG_AUDACCDETMICBIAS0PULLLOW_SHIFT},
	{PMIC_RG_AUDACCDETRSV, PMIC_RG_AUDACCDETRSV_ADDR, PMIC_RG_AUDACCDETRSV_MASK,
	 PMIC_RG_AUDACCDETRSV_SHIFT},
	{PMIC_ACCDET_EN, PMIC_ACCDET_EN_ADDR, PMIC_ACCDET_EN_MASK,
	 PMIC_ACCDET_EN_SHIFT},
	{PMIC_ACCDET_SEQ_INIT, PMIC_ACCDET_SEQ_INIT_ADDR, PMIC_ACCDET_SEQ_INIT_MASK,
	 PMIC_ACCDET_SEQ_INIT_SHIFT},
	{PMIC_ACCDET_EINTDET_EN, PMIC_ACCDET_EINTDET_EN_ADDR,
	 PMIC_ACCDET_EINTDET_EN_MASK, PMIC_ACCDET_EINTDET_EN_SHIFT},
	{PMIC_ACCDET_EINT_SEQ_INIT, PMIC_ACCDET_EINT_SEQ_INIT_ADDR,
	 PMIC_ACCDET_EINT_SEQ_INIT_MASK, PMIC_ACCDET_EINT_SEQ_INIT_SHIFT},
	{PMIC_ACCDET_NEGVDET_EN, PMIC_ACCDET_NEGVDET_EN_ADDR,
	 PMIC_ACCDET_NEGVDET_EN_MASK, PMIC_ACCDET_NEGVDET_EN_SHIFT},
	{PMIC_ACCDET_NEGVDET_EN_CTRL, PMIC_ACCDET_NEGVDET_EN_CTRL_ADDR,
	 PMIC_ACCDET_NEGVDET_EN_CTRL_MASK, PMIC_ACCDET_NEGVDET_EN_CTRL_SHIFT},
	{PMIC_ACCDET_ANASWCTRL_SEL, PMIC_ACCDET_ANASWCTRL_SEL_ADDR,
	 PMIC_ACCDET_ANASWCTRL_SEL_MASK, PMIC_ACCDET_ANASWCTRL_SEL_SHIFT},
	{PMIC_ACCDET_CMP_PWM_EN, PMIC_ACCDET_CMP_PWM_EN_ADDR,
	 PMIC_ACCDET_CMP_PWM_EN_MASK, PMIC_ACCDET_CMP_PWM_EN_SHIFT},
	{PMIC_ACCDET_VTH_PWM_EN, PMIC_ACCDET_VTH_PWM_EN_ADDR,
	 PMIC_ACCDET_VTH_PWM_EN_MASK, PMIC_ACCDET_VTH_PWM_EN_SHIFT},
	{PMIC_ACCDET_MBIAS_PWM_EN, PMIC_ACCDET_MBIAS_PWM_EN_ADDR,
	 PMIC_ACCDET_MBIAS_PWM_EN_MASK, PMIC_ACCDET_MBIAS_PWM_EN_SHIFT},
	{PMIC_ACCDET_EINT_PWM_EN, PMIC_ACCDET_EINT_PWM_EN_ADDR,
	 PMIC_ACCDET_EINT_PWM_EN_MASK, PMIC_ACCDET_EINT_PWM_EN_SHIFT},
	{PMIC_ACCDET_CMP_PWM_IDLE, PMIC_ACCDET_CMP_PWM_IDLE_ADDR,
	 PMIC_ACCDET_CMP_PWM_IDLE_MASK, PMIC_ACCDET_CMP_PWM_IDLE_SHIFT},
	{PMIC_ACCDET_VTH_PWM_IDLE, PMIC_ACCDET_VTH_PWM_IDLE_ADDR,
	 PMIC_ACCDET_VTH_PWM_IDLE_MASK, PMIC_ACCDET_VTH_PWM_IDLE_SHIFT},
	{PMIC_ACCDET_MBIAS_PWM_IDLE, PMIC_ACCDET_MBIAS_PWM_IDLE_ADDR,
	 PMIC_ACCDET_MBIAS_PWM_IDLE_MASK, PMIC_ACCDET_MBIAS_PWM_IDLE_SHIFT},
	{PMIC_ACCDET_EINT_PWM_IDLE, PMIC_ACCDET_EINT_PWM_IDLE_ADDR,
	 PMIC_ACCDET_EINT_PWM_IDLE_MASK, PMIC_ACCDET_EINT_PWM_IDLE_SHIFT},
	{PMIC_ACCDET_PWM_WIDTH, PMIC_ACCDET_PWM_WIDTH_ADDR,
	 PMIC_ACCDET_PWM_WIDTH_MASK, PMIC_ACCDET_PWM_WIDTH_SHIFT},
	{PMIC_ACCDET_PWM_THRESH, PMIC_ACCDET_PWM_THRESH_ADDR,
	 PMIC_ACCDET_PWM_THRESH_MASK, PMIC_ACCDET_PWM_THRESH_SHIFT},
	{PMIC_ACCDET_RISE_DELAY, PMIC_ACCDET_RISE_DELAY_ADDR,
	 PMIC_ACCDET_RISE_DELAY_MASK, PMIC_ACCDET_RISE_DELAY_SHIFT},
	{PMIC_ACCDET_FALL_DELAY, PMIC_ACCDET_FALL_DELAY_ADDR,
	 PMIC_ACCDET_FALL_DELAY_MASK, PMIC_ACCDET_FALL_DELAY_SHIFT},
	{PMIC_ACCDET_DEBOUNCE0, PMIC_ACCDET_DEBOUNCE0_ADDR,
	 PMIC_ACCDET_DEBOUNCE0_MASK, PMIC_ACCDET_DEBOUNCE0_SHIFT},
	{PMIC_ACCDET_DEBOUNCE1, PMIC_ACCDET_DEBOUNCE1_ADDR,
	 PMIC_ACCDET_DEBOUNCE1_MASK, PMIC_ACCDET_DEBOUNCE1_SHIFT},
	{PMIC_ACCDET_DEBOUNCE2, PMIC_ACCDET_DEBOUNCE2_ADDR,
	 PMIC_ACCDET_DEBOUNCE2_MASK, PMIC_ACCDET_DEBOUNCE2_SHIFT},
	{PMIC_ACCDET_DEBOUNCE3, PMIC_ACCDET_DEBOUNCE3_ADDR,
	 PMIC_ACCDET_DEBOUNCE3_MASK, PMIC_ACCDET_DEBOUNCE3_SHIFT},
	{PMIC_ACCDET_DEBOUNCE4, PMIC_ACCDET_DEBOUNCE4_ADDR,
	 PMIC_ACCDET_DEBOUNCE4_MASK, PMIC_ACCDET_DEBOUNCE4_SHIFT},
	{PMIC_ACCDET_IVAL_CUR_IN, PMIC_ACCDET_IVAL_CUR_IN_ADDR,
	 PMIC_ACCDET_IVAL_CUR_IN_MASK, PMIC_ACCDET_IVAL_CUR_IN_SHIFT},
	{PMIC_ACCDET_EINT_IVAL_CUR_IN, PMIC_ACCDET_EINT_IVAL_CUR_IN_ADDR,
	 PMIC_ACCDET_EINT_IVAL_CUR_IN_MASK, PMIC_ACCDET_EINT_IVAL_CUR_IN_SHIFT},
	{PMIC_ACCDET_IVAL_SAM_IN, PMIC_ACCDET_IVAL_SAM_IN_ADDR,
	 PMIC_ACCDET_IVAL_SAM_IN_MASK, PMIC_ACCDET_IVAL_SAM_IN_SHIFT},
	{PMIC_ACCDET_EINT_IVAL_SAM_IN, PMIC_ACCDET_EINT_IVAL_SAM_IN_ADDR,
	 PMIC_ACCDET_EINT_IVAL_SAM_IN_MASK, PMIC_ACCDET_EINT_IVAL_SAM_IN_SHIFT},
	{PMIC_ACCDET_IVAL_MEM_IN, PMIC_ACCDET_IVAL_MEM_IN_ADDR,
	 PMIC_ACCDET_IVAL_MEM_IN_MASK, PMIC_ACCDET_IVAL_MEM_IN_SHIFT},
	{PMIC_ACCDET_EINT_IVAL_MEM_IN, PMIC_ACCDET_EINT_IVAL_MEM_IN_ADDR,
	 PMIC_ACCDET_EINT_IVAL_MEM_IN_MASK, PMIC_ACCDET_EINT_IVAL_MEM_IN_SHIFT},
	{PMIC_ACCDET_EINT_IVAL_SEL, PMIC_ACCDET_EINT_IVAL_SEL_ADDR,
	 PMIC_ACCDET_EINT_IVAL_SEL_MASK, PMIC_ACCDET_EINT_IVAL_SEL_SHIFT},
	{PMIC_ACCDET_IVAL_SEL, PMIC_ACCDET_IVAL_SEL_ADDR, PMIC_ACCDET_IVAL_SEL_MASK,
	 PMIC_ACCDET_IVAL_SEL_SHIFT},
	{PMIC_ACCDET_IRQ, PMIC_ACCDET_IRQ_ADDR, PMIC_ACCDET_IRQ_MASK,
	 PMIC_ACCDET_IRQ_SHIFT},
	{PMIC_ACCDET_NEGV_IRQ, PMIC_ACCDET_NEGV_IRQ_ADDR, PMIC_ACCDET_NEGV_IRQ_MASK,
	 PMIC_ACCDET_NEGV_IRQ_SHIFT},
	{PMIC_ACCDET_EINT_IRQ, PMIC_ACCDET_EINT_IRQ_ADDR, PMIC_ACCDET_EINT_IRQ_MASK,
	 PMIC_ACCDET_EINT_IRQ_SHIFT},
	{PMIC_ACCDET_IRQ_CLR, PMIC_ACCDET_IRQ_CLR_ADDR, PMIC_ACCDET_IRQ_CLR_MASK,
	 PMIC_ACCDET_IRQ_CLR_SHIFT},
	{PMIC_ACCDET_NEGV_IRQ_CLR, PMIC_ACCDET_NEGV_IRQ_CLR_ADDR,
	 PMIC_ACCDET_NEGV_IRQ_CLR_MASK, PMIC_ACCDET_NEGV_IRQ_CLR_SHIFT},
	{PMIC_ACCDET_EINT_IRQ_CLR, PMIC_ACCDET_EINT_IRQ_CLR_ADDR,
	 PMIC_ACCDET_EINT_IRQ_CLR_MASK, PMIC_ACCDET_EINT_IRQ_CLR_SHIFT},
	{PMIC_ACCDET_EINT_IRQ_POLARITY, PMIC_ACCDET_EINT_IRQ_POLARITY_ADDR,
	 PMIC_ACCDET_EINT_IRQ_POLARITY_MASK, PMIC_ACCDET_EINT_IRQ_POLARITY_SHIFT},
	{PMIC_ACCDET_TEST_MODE0, PMIC_ACCDET_TEST_MODE0_ADDR,
	 PMIC_ACCDET_TEST_MODE0_MASK, PMIC_ACCDET_TEST_MODE0_SHIFT},
	{PMIC_ACCDET_TEST_MODE1, PMIC_ACCDET_TEST_MODE1_ADDR,
	 PMIC_ACCDET_TEST_MODE1_MASK, PMIC_ACCDET_TEST_MODE1_SHIFT},
	{PMIC_ACCDET_TEST_MODE2, PMIC_ACCDET_TEST_MODE2_ADDR,
	 PMIC_ACCDET_TEST_MODE2_MASK, PMIC_ACCDET_TEST_MODE2_SHIFT},
	{PMIC_ACCDET_TEST_MODE3, PMIC_ACCDET_TEST_MODE3_ADDR,
	 PMIC_ACCDET_TEST_MODE3_MASK, PMIC_ACCDET_TEST_MODE3_SHIFT},
	{PMIC_ACCDET_TEST_MODE4, PMIC_ACCDET_TEST_MODE4_ADDR,
	 PMIC_ACCDET_TEST_MODE4_MASK, PMIC_ACCDET_TEST_MODE4_SHIFT},
	{PMIC_ACCDET_TEST_MODE5, PMIC_ACCDET_TEST_MODE5_ADDR,
	 PMIC_ACCDET_TEST_MODE5_MASK, PMIC_ACCDET_TEST_MODE5_SHIFT},
	{PMIC_ACCDET_PWM_SEL, PMIC_ACCDET_PWM_SEL_ADDR, PMIC_ACCDET_PWM_SEL_MASK,
	 PMIC_ACCDET_PWM_SEL_SHIFT},
	{PMIC_ACCDET_IN_SW, PMIC_ACCDET_IN_SW_ADDR, PMIC_ACCDET_IN_SW_MASK,
	 PMIC_ACCDET_IN_SW_SHIFT},
	{PMIC_ACCDET_CMP_EN_SW, PMIC_ACCDET_CMP_EN_SW_ADDR,
	 PMIC_ACCDET_CMP_EN_SW_MASK, PMIC_ACCDET_CMP_EN_SW_SHIFT},
	{PMIC_ACCDET_VTH_EN_SW, PMIC_ACCDET_VTH_EN_SW_ADDR,
	 PMIC_ACCDET_VTH_EN_SW_MASK, PMIC_ACCDET_VTH_EN_SW_SHIFT},
	{PMIC_ACCDET_MBIAS_EN_SW, PMIC_ACCDET_MBIAS_EN_SW_ADDR,
	 PMIC_ACCDET_MBIAS_EN_SW_MASK, PMIC_ACCDET_MBIAS_EN_SW_SHIFT},
	{PMIC_ACCDET_PWM_EN_SW, PMIC_ACCDET_PWM_EN_SW_ADDR,
	 PMIC_ACCDET_PWM_EN_SW_MASK, PMIC_ACCDET_PWM_EN_SW_SHIFT},
	{PMIC_ACCDET_IN, PMIC_ACCDET_IN_ADDR, PMIC_ACCDET_IN_MASK,
	 PMIC_ACCDET_IN_SHIFT},
	{PMIC_ACCDET_CUR_IN, PMIC_ACCDET_CUR_IN_ADDR, PMIC_ACCDET_CUR_IN_MASK,
	 PMIC_ACCDET_CUR_IN_SHIFT},
	{PMIC_ACCDET_SAM_IN, PMIC_ACCDET_SAM_IN_ADDR, PMIC_ACCDET_SAM_IN_MASK,
	 PMIC_ACCDET_SAM_IN_SHIFT},
	{PMIC_ACCDET_MEM_IN, PMIC_ACCDET_MEM_IN_ADDR, PMIC_ACCDET_MEM_IN_MASK,
	 PMIC_ACCDET_MEM_IN_SHIFT},
	{PMIC_ACCDET_STATE, PMIC_ACCDET_STATE_ADDR, PMIC_ACCDET_STATE_MASK,
	 PMIC_ACCDET_STATE_SHIFT},
	{PMIC_ACCDET_MBIAS_CLK, PMIC_ACCDET_MBIAS_CLK_ADDR,
	 PMIC_ACCDET_MBIAS_CLK_MASK, PMIC_ACCDET_MBIAS_CLK_SHIFT},
	{PMIC_ACCDET_VTH_CLK, PMIC_ACCDET_VTH_CLK_ADDR, PMIC_ACCDET_VTH_CLK_MASK,
	 PMIC_ACCDET_VTH_CLK_SHIFT},
	{PMIC_ACCDET_CMP_CLK, PMIC_ACCDET_CMP_CLK_ADDR, PMIC_ACCDET_CMP_CLK_MASK,
	 PMIC_ACCDET_CMP_CLK_SHIFT},
	{PMIC_DA_AUDACCDETAUXADCSWCTRL, PMIC_DA_AUDACCDETAUXADCSWCTRL_ADDR,
	 PMIC_DA_AUDACCDETAUXADCSWCTRL_MASK, PMIC_DA_AUDACCDETAUXADCSWCTRL_SHIFT},
	{PMIC_ACCDET_EINT_DEB_SEL, PMIC_ACCDET_EINT_DEB_SEL_ADDR,
	 PMIC_ACCDET_EINT_DEB_SEL_MASK, PMIC_ACCDET_EINT_DEB_SEL_SHIFT},
	{PMIC_ACCDET_EINT_DEBOUNCE, PMIC_ACCDET_EINT_DEBOUNCE_ADDR,
	 PMIC_ACCDET_EINT_DEBOUNCE_MASK, PMIC_ACCDET_EINT_DEBOUNCE_SHIFT},
	{PMIC_ACCDET_EINT_PWM_THRESH, PMIC_ACCDET_EINT_PWM_THRESH_ADDR,
	 PMIC_ACCDET_EINT_PWM_THRESH_MASK, PMIC_ACCDET_EINT_PWM_THRESH_SHIFT},
	{PMIC_ACCDET_EINT_PWM_WIDTH, PMIC_ACCDET_EINT_PWM_WIDTH_ADDR,
	 PMIC_ACCDET_EINT_PWM_WIDTH_MASK, PMIC_ACCDET_EINT_PWM_WIDTH_SHIFT},
	{PMIC_ACCDET_NEGV_THRESH, PMIC_ACCDET_NEGV_THRESH_ADDR,
	 PMIC_ACCDET_NEGV_THRESH_MASK, PMIC_ACCDET_NEGV_THRESH_SHIFT},
	{PMIC_ACCDET_EINT_PWM_FALL_DELAY, PMIC_ACCDET_EINT_PWM_FALL_DELAY_ADDR,
	 PMIC_ACCDET_EINT_PWM_FALL_DELAY_MASK, PMIC_ACCDET_EINT_PWM_FALL_DELAY_SHIFT},
	{PMIC_ACCDET_EINT_PWM_RISE_DELAY, PMIC_ACCDET_EINT_PWM_RISE_DELAY_ADDR,
	 PMIC_ACCDET_EINT_PWM_RISE_DELAY_MASK, PMIC_ACCDET_EINT_PWM_RISE_DELAY_SHIFT},
	{PMIC_ACCDET_TEST_MODE13, PMIC_ACCDET_TEST_MODE13_ADDR,
	 PMIC_ACCDET_TEST_MODE13_MASK, PMIC_ACCDET_TEST_MODE13_SHIFT},
	{PMIC_ACCDET_TEST_MODE12, PMIC_ACCDET_TEST_MODE12_ADDR,
	 PMIC_ACCDET_TEST_MODE12_MASK, PMIC_ACCDET_TEST_MODE12_SHIFT},
	{PMIC_ACCDET_NVDETECTOUT_SW, PMIC_ACCDET_NVDETECTOUT_SW_ADDR,
	 PMIC_ACCDET_NVDETECTOUT_SW_MASK, PMIC_ACCDET_NVDETECTOUT_SW_SHIFT},
	{PMIC_ACCDET_TEST_MODE11, PMIC_ACCDET_TEST_MODE11_ADDR,
	 PMIC_ACCDET_TEST_MODE11_MASK, PMIC_ACCDET_TEST_MODE11_SHIFT},
	{PMIC_ACCDET_TEST_MODE10, PMIC_ACCDET_TEST_MODE10_ADDR,
	 PMIC_ACCDET_TEST_MODE10_MASK, PMIC_ACCDET_TEST_MODE10_SHIFT},
	{PMIC_ACCDET_EINTCMPOUT_SW, PMIC_ACCDET_EINTCMPOUT_SW_ADDR,
	 PMIC_ACCDET_EINTCMPOUT_SW_MASK, PMIC_ACCDET_EINTCMPOUT_SW_SHIFT},
	{PMIC_ACCDET_TEST_MODE9, PMIC_ACCDET_TEST_MODE9_ADDR,
	 PMIC_ACCDET_TEST_MODE9_MASK, PMIC_ACCDET_TEST_MODE9_SHIFT},
	{PMIC_ACCDET_TEST_MODE8, PMIC_ACCDET_TEST_MODE8_ADDR,
	 PMIC_ACCDET_TEST_MODE8_MASK, PMIC_ACCDET_TEST_MODE8_SHIFT},
	{PMIC_ACCDET_AUXADC_CTRL_SW, PMIC_ACCDET_AUXADC_CTRL_SW_ADDR,
	 PMIC_ACCDET_AUXADC_CTRL_SW_MASK, PMIC_ACCDET_AUXADC_CTRL_SW_SHIFT},
	{PMIC_ACCDET_TEST_MODE7, PMIC_ACCDET_TEST_MODE7_ADDR,
	 PMIC_ACCDET_TEST_MODE7_MASK, PMIC_ACCDET_TEST_MODE7_SHIFT},
	{PMIC_ACCDET_TEST_MODE6, PMIC_ACCDET_TEST_MODE6_ADDR,
	 PMIC_ACCDET_TEST_MODE6_MASK, PMIC_ACCDET_TEST_MODE6_SHIFT},
	{PMIC_ACCDET_EINTCMP_EN_SW, PMIC_ACCDET_EINTCMP_EN_SW_ADDR,
	 PMIC_ACCDET_EINTCMP_EN_SW_MASK, PMIC_ACCDET_EINTCMP_EN_SW_SHIFT},
	{PMIC_RG_NVCMPSWEN, PMIC_RG_NVCMPSWEN_ADDR, PMIC_RG_NVCMPSWEN_MASK,
	 PMIC_RG_NVCMPSWEN_SHIFT},
	{PMIC_RG_NVMODSEL, PMIC_RG_NVMODSEL_ADDR, PMIC_RG_NVMODSEL_MASK,
	 PMIC_RG_NVMODSEL_SHIFT},
	{PMIC_RG_SWBUFSWEN, PMIC_RG_SWBUFSWEN_ADDR, PMIC_RG_SWBUFSWEN_MASK,
	 PMIC_RG_SWBUFSWEN_SHIFT},
	{PMIC_RG_SWBUFMODSEL, PMIC_RG_SWBUFMODSEL_ADDR, PMIC_RG_SWBUFMODSEL_MASK,
	 PMIC_RG_SWBUFMODSEL_SHIFT},
	{PMIC_RG_NVDETVTH, PMIC_RG_NVDETVTH_ADDR, PMIC_RG_NVDETVTH_MASK,
	 PMIC_RG_NVDETVTH_SHIFT},
	{PMIC_RG_NVDETCMPEN, PMIC_RG_NVDETCMPEN_ADDR, PMIC_RG_NVDETCMPEN_MASK,
	 PMIC_RG_NVDETCMPEN_SHIFT},
	{PMIC_RG_EINTCONFIGACCDET, PMIC_RG_EINTCONFIGACCDET_ADDR,
	 PMIC_RG_EINTCONFIGACCDET_MASK, PMIC_RG_EINTCONFIGACCDET_SHIFT},
	{PMIC_RG_EINTCOMPVTH, PMIC_RG_EINTCOMPVTH_ADDR, PMIC_RG_EINTCOMPVTH_MASK,
	 PMIC_RG_EINTCOMPVTH_SHIFT},
	{PMIC_ACCDET_EINT_STATE, PMIC_ACCDET_EINT_STATE_ADDR,
	 PMIC_ACCDET_EINT_STATE_MASK, PMIC_ACCDET_EINT_STATE_SHIFT},
	{PMIC_ACCDET_AUXADC_DEBOUNCE_END, PMIC_ACCDET_AUXADC_DEBOUNCE_END_ADDR,
	 PMIC_ACCDET_AUXADC_DEBOUNCE_END_MASK, PMIC_ACCDET_AUXADC_DEBOUNCE_END_SHIFT},
	{PMIC_ACCDET_AUXADC_CONNECT_PRE, PMIC_ACCDET_AUXADC_CONNECT_PRE_ADDR,
	 PMIC_ACCDET_AUXADC_CONNECT_PRE_MASK, PMIC_ACCDET_AUXADC_CONNECT_PRE_SHIFT},
	{PMIC_ACCDET_EINT_CUR_IN, PMIC_ACCDET_EINT_CUR_IN_ADDR,
	 PMIC_ACCDET_EINT_CUR_IN_MASK, PMIC_ACCDET_EINT_CUR_IN_SHIFT},
	{PMIC_ACCDET_EINT_SAM_IN, PMIC_ACCDET_EINT_SAM_IN_ADDR,
	 PMIC_ACCDET_EINT_SAM_IN_MASK, PMIC_ACCDET_EINT_SAM_IN_SHIFT},
	{PMIC_ACCDET_EINT_MEM_IN, PMIC_ACCDET_EINT_MEM_IN_ADDR,
	 PMIC_ACCDET_EINT_MEM_IN_MASK, PMIC_ACCDET_EINT_MEM_IN_SHIFT},
	{PMIC_AD_NVDETECTOUT, PMIC_AD_NVDETECTOUT_ADDR, PMIC_AD_NVDETECTOUT_MASK,
	 PMIC_AD_NVDETECTOUT_SHIFT},
	{PMIC_AD_EINTCMPOUT, PMIC_AD_EINTCMPOUT_ADDR, PMIC_AD_EINTCMPOUT_MASK,
	 PMIC_AD_EINTCMPOUT_SHIFT},
	{PMIC_DA_NI_EINTCMPEN, PMIC_DA_NI_EINTCMPEN_ADDR, PMIC_DA_NI_EINTCMPEN_MASK,
	 PMIC_DA_NI_EINTCMPEN_SHIFT},
	{PMIC_ACCDET_NEGV_COUNT_IN, PMIC_ACCDET_NEGV_COUNT_IN_ADDR,
	 PMIC_ACCDET_NEGV_COUNT_IN_MASK, PMIC_ACCDET_NEGV_COUNT_IN_SHIFT},
	{PMIC_ACCDET_NEGV_EN_FINAL, PMIC_ACCDET_NEGV_EN_FINAL_ADDR,
	 PMIC_ACCDET_NEGV_EN_FINAL_MASK, PMIC_ACCDET_NEGV_EN_FINAL_SHIFT},
	{PMIC_ACCDET_NEGV_COUNT_END, PMIC_ACCDET_NEGV_COUNT_END_ADDR,
	 PMIC_ACCDET_NEGV_COUNT_END_MASK, PMIC_ACCDET_NEGV_COUNT_END_SHIFT},
	{PMIC_ACCDET_NEGV_MINU, PMIC_ACCDET_NEGV_MINU_ADDR,
	 PMIC_ACCDET_NEGV_MINU_MASK, PMIC_ACCDET_NEGV_MINU_SHIFT},
	{PMIC_ACCDET_NEGV_ADD, PMIC_ACCDET_NEGV_ADD_ADDR, PMIC_ACCDET_NEGV_ADD_MASK,
	 PMIC_ACCDET_NEGV_ADD_SHIFT},
	{PMIC_ACCDET_NEGV_CMP, PMIC_ACCDET_NEGV_CMP_ADDR, PMIC_ACCDET_NEGV_CMP_MASK,
	 PMIC_ACCDET_NEGV_CMP_SHIFT},
	{PMIC_ACCDET_CUR_DEB, PMIC_ACCDET_CUR_DEB_ADDR, PMIC_ACCDET_CUR_DEB_MASK,
	 PMIC_ACCDET_CUR_DEB_SHIFT},
	{PMIC_ACCDET_EINT_CUR_DEB, PMIC_ACCDET_EINT_CUR_DEB_ADDR,
	 PMIC_ACCDET_EINT_CUR_DEB_MASK, PMIC_ACCDET_EINT_CUR_DEB_SHIFT},
	{PMIC_ACCDET_RSV_CON0, PMIC_ACCDET_RSV_CON0_ADDR, PMIC_ACCDET_RSV_CON0_MASK,
	 PMIC_ACCDET_RSV_CON0_SHIFT},
	{PMIC_ACCDET_RSV_CON1, PMIC_ACCDET_RSV_CON1_ADDR, PMIC_ACCDET_RSV_CON1_MASK,
	 PMIC_ACCDET_RSV_CON1_SHIFT},
	{PMIC_ACCDET_AUXADC_CONNECT_TIME, PMIC_ACCDET_AUXADC_CONNECT_TIME_ADDR,
	 PMIC_ACCDET_AUXADC_CONNECT_TIME_MASK, PMIC_ACCDET_AUXADC_CONNECT_TIME_SHIFT},
	{PMIC_RG_VCDT_HV_EN, PMIC_RG_VCDT_HV_EN_ADDR, PMIC_RG_VCDT_HV_EN_MASK,
	 PMIC_RG_VCDT_HV_EN_SHIFT},
	{PMIC_RGS_CHR_LDO_DET, PMIC_RGS_CHR_LDO_DET_ADDR, PMIC_RGS_CHR_LDO_DET_MASK,
	 PMIC_RGS_CHR_LDO_DET_SHIFT},
	{PMIC_RG_PCHR_AUTOMODE, PMIC_RG_PCHR_AUTOMODE_ADDR,
	 PMIC_RG_PCHR_AUTOMODE_MASK, PMIC_RG_PCHR_AUTOMODE_SHIFT},
	{PMIC_RG_CSDAC_EN, PMIC_RG_CSDAC_EN_ADDR, PMIC_RG_CSDAC_EN_MASK,
	 PMIC_RG_CSDAC_EN_SHIFT},
	{PMIC_RG_CHR_EN, PMIC_RG_CHR_EN_ADDR, PMIC_RG_CHR_EN_MASK,
	 PMIC_RG_CHR_EN_SHIFT},
	{PMIC_RGS_CHRDET, PMIC_RGS_CHRDET_ADDR, PMIC_RGS_CHRDET_MASK,
	 PMIC_RGS_CHRDET_SHIFT},
	{PMIC_RGS_VCDT_LV_DET, PMIC_RGS_VCDT_LV_DET_ADDR, PMIC_RGS_VCDT_LV_DET_MASK,
	 PMIC_RGS_VCDT_LV_DET_SHIFT},
	{PMIC_RGS_VCDT_HV_DET, PMIC_RGS_VCDT_HV_DET_ADDR, PMIC_RGS_VCDT_HV_DET_MASK,
	 PMIC_RGS_VCDT_HV_DET_SHIFT},
	{PMIC_RG_VCDT_LV_VTH, PMIC_RG_VCDT_LV_VTH_ADDR, PMIC_RG_VCDT_LV_VTH_MASK,
	 PMIC_RG_VCDT_LV_VTH_SHIFT},
	{PMIC_RG_VCDT_HV_VTH, PMIC_RG_VCDT_HV_VTH_ADDR, PMIC_RG_VCDT_HV_VTH_MASK,
	 PMIC_RG_VCDT_HV_VTH_SHIFT},
	{PMIC_RG_VBAT_CV_EN, PMIC_RG_VBAT_CV_EN_ADDR, PMIC_RG_VBAT_CV_EN_MASK,
	 PMIC_RG_VBAT_CV_EN_SHIFT},
	{PMIC_RG_VBAT_CC_EN, PMIC_RG_VBAT_CC_EN_ADDR, PMIC_RG_VBAT_CC_EN_MASK,
	 PMIC_RG_VBAT_CC_EN_SHIFT},
	{PMIC_RG_CS_EN, PMIC_RG_CS_EN_ADDR, PMIC_RG_CS_EN_MASK,
	 PMIC_RG_CS_EN_SHIFT},
	{PMIC_RGS_CS_DET, PMIC_RGS_CS_DET_ADDR, PMIC_RGS_CS_DET_MASK,
	 PMIC_RGS_CS_DET_SHIFT},
	{PMIC_RGS_VBAT_CV_DET, PMIC_RGS_VBAT_CV_DET_ADDR, PMIC_RGS_VBAT_CV_DET_MASK,
	 PMIC_RGS_VBAT_CV_DET_SHIFT},
	{PMIC_RGS_VBAT_CC_DET, PMIC_RGS_VBAT_CC_DET_ADDR, PMIC_RGS_VBAT_CC_DET_MASK,
	 PMIC_RGS_VBAT_CC_DET_SHIFT},
	{PMIC_RG_VBAT_CV_VTH, PMIC_RG_VBAT_CV_VTH_ADDR, PMIC_RG_VBAT_CV_VTH_MASK,
	 PMIC_RG_VBAT_CV_VTH_SHIFT},
	{PMIC_RG_VBAT_CC_VTH, PMIC_RG_VBAT_CC_VTH_ADDR, PMIC_RG_VBAT_CC_VTH_MASK,
	 PMIC_RG_VBAT_CC_VTH_SHIFT},
	{PMIC_RG_CS_VTH, PMIC_RG_CS_VTH_ADDR, PMIC_RG_CS_VTH_MASK,
	 PMIC_RG_CS_VTH_SHIFT},
	{PMIC_RG_PCHR_TOHTC, PMIC_RG_PCHR_TOHTC_ADDR, PMIC_RG_PCHR_TOHTC_MASK,
	 PMIC_RG_PCHR_TOHTC_SHIFT},
	{PMIC_RG_PCHR_TOLTC, PMIC_RG_PCHR_TOLTC_ADDR, PMIC_RG_PCHR_TOLTC_MASK,
	 PMIC_RG_PCHR_TOLTC_SHIFT},
	{PMIC_RG_VBAT_OV_EN, PMIC_RG_VBAT_OV_EN_ADDR, PMIC_RG_VBAT_OV_EN_MASK,
	 PMIC_RG_VBAT_OV_EN_SHIFT},
	{PMIC_RG_VBAT_OV_VTH, PMIC_RG_VBAT_OV_VTH_ADDR, PMIC_RG_VBAT_OV_VTH_MASK,
	 PMIC_RG_VBAT_OV_VTH_SHIFT},
	{PMIC_RG_VBAT_OV_DEG, PMIC_RG_VBAT_OV_DEG_ADDR, PMIC_RG_VBAT_OV_DEG_MASK,
	 PMIC_RG_VBAT_OV_DEG_SHIFT},
	{PMIC_RGS_VBAT_OV_DET, PMIC_RGS_VBAT_OV_DET_ADDR, PMIC_RGS_VBAT_OV_DET_MASK,
	 PMIC_RGS_VBAT_OV_DET_SHIFT},
	{PMIC_RG_BATON_EN, PMIC_RG_BATON_EN_ADDR, PMIC_RG_BATON_EN_MASK,
	 PMIC_RG_BATON_EN_SHIFT},
	{PMIC_RG_BATON_HT_EN_RSV0, PMIC_RG_BATON_HT_EN_RSV0_ADDR,
	 PMIC_RG_BATON_HT_EN_RSV0_MASK, PMIC_RG_BATON_HT_EN_RSV0_SHIFT},
	{PMIC_BATON_TDET_EN, PMIC_BATON_TDET_EN_ADDR, PMIC_BATON_TDET_EN_MASK,
	 PMIC_BATON_TDET_EN_SHIFT},
	{PMIC_RG_BATON_HT_TRIM, PMIC_RG_BATON_HT_TRIM_ADDR,
	 PMIC_RG_BATON_HT_TRIM_MASK, PMIC_RG_BATON_HT_TRIM_SHIFT},
	{PMIC_RG_BATON_HT_TRIM_SET, PMIC_RG_BATON_HT_TRIM_SET_ADDR,
	 PMIC_RG_BATON_HT_TRIM_SET_MASK, PMIC_RG_BATON_HT_TRIM_SET_SHIFT},
	{PMIC_RG_BATON_TDET_EN, PMIC_RG_BATON_TDET_EN_ADDR,
	 PMIC_RG_BATON_TDET_EN_MASK, PMIC_RG_BATON_TDET_EN_SHIFT},
	{PMIC_RG_CSDAC_DATA, PMIC_RG_CSDAC_DATA_ADDR, PMIC_RG_CSDAC_DATA_MASK,
	 PMIC_RG_CSDAC_DATA_SHIFT},
	{PMIC_RG_FRC_CSVTH_USBDL, PMIC_RG_FRC_CSVTH_USBDL_ADDR,
	 PMIC_RG_FRC_CSVTH_USBDL_MASK, PMIC_RG_FRC_CSVTH_USBDL_SHIFT},
	{PMIC_RGS_PCHR_FLAG_OUT, PMIC_RGS_PCHR_FLAG_OUT_ADDR,
	 PMIC_RGS_PCHR_FLAG_OUT_MASK, PMIC_RGS_PCHR_FLAG_OUT_SHIFT},
	{PMIC_RG_PCHR_FLAG_EN, PMIC_RG_PCHR_FLAG_EN_ADDR, PMIC_RG_PCHR_FLAG_EN_MASK,
	 PMIC_RG_PCHR_FLAG_EN_SHIFT},
	{PMIC_RG_OTG_BVALID_EN, PMIC_RG_OTG_BVALID_EN_ADDR,
	 PMIC_RG_OTG_BVALID_EN_MASK, PMIC_RG_OTG_BVALID_EN_SHIFT},
	{PMIC_RGS_OTG_BVALID_DET, PMIC_RGS_OTG_BVALID_DET_ADDR,
	 PMIC_RGS_OTG_BVALID_DET_MASK, PMIC_RGS_OTG_BVALID_DET_SHIFT},
	{PMIC_RG_PCHR_FLAG_SEL, PMIC_RG_PCHR_FLAG_SEL_ADDR,
	 PMIC_RG_PCHR_FLAG_SEL_MASK, PMIC_RG_PCHR_FLAG_SEL_SHIFT},
	{PMIC_RG_PCHR_TESTMODE, PMIC_RG_PCHR_TESTMODE_ADDR,
	 PMIC_RG_PCHR_TESTMODE_MASK, PMIC_RG_PCHR_TESTMODE_SHIFT},
	{PMIC_RG_CSDAC_TESTMODE, PMIC_RG_CSDAC_TESTMODE_ADDR,
	 PMIC_RG_CSDAC_TESTMODE_MASK, PMIC_RG_CSDAC_TESTMODE_SHIFT},
	{PMIC_RG_PCHR_RST, PMIC_RG_PCHR_RST_ADDR, PMIC_RG_PCHR_RST_MASK,
	 PMIC_RG_PCHR_RST_SHIFT},
	{PMIC_RG_PCHR_FT_CTRL, PMIC_RG_PCHR_FT_CTRL_ADDR, PMIC_RG_PCHR_FT_CTRL_MASK,
	 PMIC_RG_PCHR_FT_CTRL_SHIFT},
	{PMIC_RG_CHRWDT_TD, PMIC_RG_CHRWDT_TD_ADDR, PMIC_RG_CHRWDT_TD_MASK,
	 PMIC_RG_CHRWDT_TD_SHIFT},
	{PMIC_RG_CHRWDT_EN, PMIC_RG_CHRWDT_EN_ADDR, PMIC_RG_CHRWDT_EN_MASK,
	 PMIC_RG_CHRWDT_EN_SHIFT},
	{PMIC_RG_CHRWDT_WR, PMIC_RG_CHRWDT_WR_ADDR, PMIC_RG_CHRWDT_WR_MASK,
	 PMIC_RG_CHRWDT_WR_SHIFT},
	{PMIC_RG_PCHR_RV, PMIC_RG_PCHR_RV_ADDR, PMIC_RG_PCHR_RV_MASK,
	 PMIC_RG_PCHR_RV_SHIFT},
	{PMIC_RG_CHRWDT_INT_EN, PMIC_RG_CHRWDT_INT_EN_ADDR,
	 PMIC_RG_CHRWDT_INT_EN_MASK, PMIC_RG_CHRWDT_INT_EN_SHIFT},
	{PMIC_RG_CHRWDT_FLAG_WR, PMIC_RG_CHRWDT_FLAG_WR_ADDR,
	 PMIC_RG_CHRWDT_FLAG_WR_MASK, PMIC_RG_CHRWDT_FLAG_WR_SHIFT},
	{PMIC_RGS_CHRWDT_OUT, PMIC_RGS_CHRWDT_OUT_ADDR, PMIC_RGS_CHRWDT_OUT_MASK,
	 PMIC_RGS_CHRWDT_OUT_SHIFT},
	{PMIC_RG_USBDL_RST, PMIC_RG_USBDL_RST_ADDR, PMIC_RG_USBDL_RST_MASK,
	 PMIC_RG_USBDL_RST_SHIFT},
	{PMIC_RG_USBDL_SET, PMIC_RG_USBDL_SET_ADDR, PMIC_RG_USBDL_SET_MASK,
	 PMIC_RG_USBDL_SET_SHIFT},
	{PMIC_RG_ADCIN_VSEN_MUX_EN, PMIC_RG_ADCIN_VSEN_MUX_EN_ADDR,
	 PMIC_RG_ADCIN_VSEN_MUX_EN_MASK, PMIC_RG_ADCIN_VSEN_MUX_EN_SHIFT},
	{PMIC_RG_ADCIN_VSEN_EXT_BATON_EN, PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_ADDR,
	 PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_MASK, PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_SHIFT},
	{PMIC_RG_ADCIN_VBAT_EN, PMIC_RG_ADCIN_VBAT_EN_ADDR,
	 PMIC_RG_ADCIN_VBAT_EN_MASK, PMIC_RG_ADCIN_VBAT_EN_SHIFT},
	{PMIC_RG_ADCIN_VSEN_EN, PMIC_RG_ADCIN_VSEN_EN_ADDR,
	 PMIC_RG_ADCIN_VSEN_EN_MASK, PMIC_RG_ADCIN_VSEN_EN_SHIFT},
	{PMIC_RG_ADCIN_CHR_EN, PMIC_RG_ADCIN_CHR_EN_ADDR, PMIC_RG_ADCIN_CHR_EN_MASK,
	 PMIC_RG_ADCIN_CHR_EN_SHIFT},
	{PMIC_RG_UVLO_VTHL, PMIC_RG_UVLO_VTHL_ADDR, PMIC_RG_UVLO_VTHL_MASK,
	 PMIC_RG_UVLO_VTHL_SHIFT},
	{PMIC_RG_UVLO_VH_LAT, PMIC_RG_UVLO_VH_LAT_ADDR, PMIC_RG_UVLO_VH_LAT_MASK,
	 PMIC_RG_UVLO_VH_LAT_SHIFT},
	{PMIC_RG_LBAT_INT_VTH, PMIC_RG_LBAT_INT_VTH_ADDR, PMIC_RG_LBAT_INT_VTH_MASK,
	 PMIC_RG_LBAT_INT_VTH_SHIFT},
	{PMIC_RG_BGR_RSEL, PMIC_RG_BGR_RSEL_ADDR, PMIC_RG_BGR_RSEL_MASK,
	 PMIC_RG_BGR_RSEL_SHIFT},
	{PMIC_RG_BGR_UNCHOP_PH, PMIC_RG_BGR_UNCHOP_PH_ADDR,
	 PMIC_RG_BGR_UNCHOP_PH_MASK, PMIC_RG_BGR_UNCHOP_PH_SHIFT},
	{PMIC_RG_BGR_UNCHOP, PMIC_RG_BGR_UNCHOP_ADDR, PMIC_RG_BGR_UNCHOP_MASK,
	 PMIC_RG_BGR_UNCHOP_SHIFT},
	{PMIC_RG_BC11_BB_CTRL, PMIC_RG_BC11_BB_CTRL_ADDR, PMIC_RG_BC11_BB_CTRL_MASK,
	 PMIC_RG_BC11_BB_CTRL_SHIFT},
	{PMIC_RG_BC11_RST, PMIC_RG_BC11_RST_ADDR, PMIC_RG_BC11_RST_MASK,
	 PMIC_RG_BC11_RST_SHIFT},
	{PMIC_RG_BC11_VSRC_EN, PMIC_RG_BC11_VSRC_EN_ADDR, PMIC_RG_BC11_VSRC_EN_MASK,
	 PMIC_RG_BC11_VSRC_EN_SHIFT},
	{PMIC_RGS_BC11_CMP_OUT, PMIC_RGS_BC11_CMP_OUT_ADDR,
	 PMIC_RGS_BC11_CMP_OUT_MASK, PMIC_RGS_BC11_CMP_OUT_SHIFT},
	{PMIC_RG_BC11_VREF_VTH, PMIC_RG_BC11_VREF_VTH_ADDR,
	 PMIC_RG_BC11_VREF_VTH_MASK, PMIC_RG_BC11_VREF_VTH_SHIFT},
	{PMIC_RG_BC11_CMP_EN, PMIC_RG_BC11_CMP_EN_ADDR, PMIC_RG_BC11_CMP_EN_MASK,
	 PMIC_RG_BC11_CMP_EN_SHIFT},
	{PMIC_RG_BC11_IPD_EN, PMIC_RG_BC11_IPD_EN_ADDR, PMIC_RG_BC11_IPD_EN_MASK,
	 PMIC_RG_BC11_IPD_EN_SHIFT},
	{PMIC_RG_BC11_IPU_EN, PMIC_RG_BC11_IPU_EN_ADDR, PMIC_RG_BC11_IPU_EN_MASK,
	 PMIC_RG_BC11_IPU_EN_SHIFT},
	{PMIC_RG_BC11_BIAS_EN, PMIC_RG_BC11_BIAS_EN_ADDR, PMIC_RG_BC11_BIAS_EN_MASK,
	 PMIC_RG_BC11_BIAS_EN_SHIFT},
	{PMIC_RG_CSDAC_STP_INC, PMIC_RG_CSDAC_STP_INC_ADDR,
	 PMIC_RG_CSDAC_STP_INC_MASK, PMIC_RG_CSDAC_STP_INC_SHIFT},
	{PMIC_RG_CSDAC_STP_DEC, PMIC_RG_CSDAC_STP_DEC_ADDR,
	 PMIC_RG_CSDAC_STP_DEC_MASK, PMIC_RG_CSDAC_STP_DEC_SHIFT},
	{PMIC_RG_CSDAC_DLY, PMIC_RG_CSDAC_DLY_ADDR, PMIC_RG_CSDAC_DLY_MASK,
	 PMIC_RG_CSDAC_DLY_SHIFT},
	{PMIC_RG_CSDAC_STP, PMIC_RG_CSDAC_STP_ADDR, PMIC_RG_CSDAC_STP_MASK,
	 PMIC_RG_CSDAC_STP_SHIFT},
	{PMIC_RG_LOW_ICH_DB, PMIC_RG_LOW_ICH_DB_ADDR, PMIC_RG_LOW_ICH_DB_MASK,
	 PMIC_RG_LOW_ICH_DB_SHIFT},
	{PMIC_RG_CHRIND_ON, PMIC_RG_CHRIND_ON_ADDR, PMIC_RG_CHRIND_ON_MASK,
	 PMIC_RG_CHRIND_ON_SHIFT},
	{PMIC_RG_CHRIND_DIMMING, PMIC_RG_CHRIND_DIMMING_ADDR,
	 PMIC_RG_CHRIND_DIMMING_MASK, PMIC_RG_CHRIND_DIMMING_SHIFT},
	{PMIC_RG_CV_MODE, PMIC_RG_CV_MODE_ADDR, PMIC_RG_CV_MODE_MASK,
	 PMIC_RG_CV_MODE_SHIFT},
	{PMIC_RG_VCDT_MODE, PMIC_RG_VCDT_MODE_ADDR, PMIC_RG_VCDT_MODE_MASK,
	 PMIC_RG_VCDT_MODE_SHIFT},
	{PMIC_RG_CSDAC_MODE, PMIC_RG_CSDAC_MODE_ADDR, PMIC_RG_CSDAC_MODE_MASK,
	 PMIC_RG_CSDAC_MODE_SHIFT},
	{PMIC_RG_TRACKING_EN, PMIC_RG_TRACKING_EN_ADDR, PMIC_RG_TRACKING_EN_MASK,
	 PMIC_RG_TRACKING_EN_SHIFT},
	{PMIC_RG_HWCV_EN, PMIC_RG_HWCV_EN_ADDR, PMIC_RG_HWCV_EN_MASK,
	 PMIC_RG_HWCV_EN_SHIFT},
	{PMIC_RG_ULC_DET_EN, PMIC_RG_ULC_DET_EN_ADDR, PMIC_RG_ULC_DET_EN_MASK,
	 PMIC_RG_ULC_DET_EN_SHIFT},
	{PMIC_RG_BGR_TRIM_EN, PMIC_RG_BGR_TRIM_EN_ADDR, PMIC_RG_BGR_TRIM_EN_MASK,
	 PMIC_RG_BGR_TRIM_EN_SHIFT},
	{PMIC_RG_ICHRG_TRIM, PMIC_RG_ICHRG_TRIM_ADDR, PMIC_RG_ICHRG_TRIM_MASK,
	 PMIC_RG_ICHRG_TRIM_SHIFT},
	{PMIC_RG_BGR_TRIM, PMIC_RG_BGR_TRIM_ADDR, PMIC_RG_BGR_TRIM_MASK,
	 PMIC_RG_BGR_TRIM_SHIFT},
	{PMIC_RG_OVP_TRIM, PMIC_RG_OVP_TRIM_ADDR, PMIC_RG_OVP_TRIM_MASK,
	 PMIC_RG_OVP_TRIM_SHIFT},
	{PMIC_RG_CHR_OSC_TRIM, PMIC_RG_CHR_OSC_TRIM_ADDR, PMIC_RG_CHR_OSC_TRIM_MASK,
	 PMIC_RG_CHR_OSC_TRIM_SHIFT},
	{PMIC_DA_QI_BGR_EXT_BUF_EN, PMIC_DA_QI_BGR_EXT_BUF_EN_ADDR,
	 PMIC_DA_QI_BGR_EXT_BUF_EN_MASK, PMIC_DA_QI_BGR_EXT_BUF_EN_SHIFT},
	{PMIC_RG_BGR_TEST_EN, PMIC_RG_BGR_TEST_EN_ADDR, PMIC_RG_BGR_TEST_EN_MASK,
	 PMIC_RG_BGR_TEST_EN_SHIFT},
	{PMIC_RG_BGR_TEST_RSTB, PMIC_RG_BGR_TEST_RSTB_ADDR,
	 PMIC_RG_BGR_TEST_RSTB_MASK, PMIC_RG_BGR_TEST_RSTB_SHIFT},
	{PMIC_RG_DAC_USBDL_MAX, PMIC_RG_DAC_USBDL_MAX_ADDR,
	 PMIC_RG_DAC_USBDL_MAX_MASK, PMIC_RG_DAC_USBDL_MAX_SHIFT},
	{PMIC_RG_CM_VDEC_TRIG, PMIC_RG_CM_VDEC_TRIG_ADDR, PMIC_RG_CM_VDEC_TRIG_MASK,
	 PMIC_RG_CM_VDEC_TRIG_SHIFT},
	{PMIC_PCHR_CM_VDEC_STATUS, PMIC_PCHR_CM_VDEC_STATUS_ADDR,
	 PMIC_PCHR_CM_VDEC_STATUS_MASK, PMIC_PCHR_CM_VDEC_STATUS_SHIFT},
	{PMIC_RG_CM_VINC_TRIG, PMIC_RG_CM_VINC_TRIG_ADDR, PMIC_RG_CM_VINC_TRIG_MASK,
	 PMIC_RG_CM_VINC_TRIG_SHIFT},
	{PMIC_PCHR_CM_VINC_STATUS, PMIC_PCHR_CM_VINC_STATUS_ADDR,
	 PMIC_PCHR_CM_VINC_STATUS_MASK, PMIC_PCHR_CM_VINC_STATUS_SHIFT},
	{PMIC_RG_CM_VDEC_HPRD1, PMIC_RG_CM_VDEC_HPRD1_ADDR,
	 PMIC_RG_CM_VDEC_HPRD1_MASK, PMIC_RG_CM_VDEC_HPRD1_SHIFT},
	{PMIC_RG_CM_VDEC_HPRD2, PMIC_RG_CM_VDEC_HPRD2_ADDR,
	 PMIC_RG_CM_VDEC_HPRD2_MASK, PMIC_RG_CM_VDEC_HPRD2_SHIFT},
	{PMIC_RG_CM_VDEC_HPRD3, PMIC_RG_CM_VDEC_HPRD3_ADDR,
	 PMIC_RG_CM_VDEC_HPRD3_MASK, PMIC_RG_CM_VDEC_HPRD3_SHIFT},
	{PMIC_RG_CM_VDEC_HPRD4, PMIC_RG_CM_VDEC_HPRD4_ADDR,
	 PMIC_RG_CM_VDEC_HPRD4_MASK, PMIC_RG_CM_VDEC_HPRD4_SHIFT},
	{PMIC_RG_CM_VDEC_HPRD5, PMIC_RG_CM_VDEC_HPRD5_ADDR,
	 PMIC_RG_CM_VDEC_HPRD5_MASK, PMIC_RG_CM_VDEC_HPRD5_SHIFT},
	{PMIC_RG_CM_VDEC_HPRD6, PMIC_RG_CM_VDEC_HPRD6_ADDR,
	 PMIC_RG_CM_VDEC_HPRD6_MASK, PMIC_RG_CM_VDEC_HPRD6_SHIFT},
	{PMIC_RG_CM_VINC_HPRD1, PMIC_RG_CM_VINC_HPRD1_ADDR,
	 PMIC_RG_CM_VINC_HPRD1_MASK, PMIC_RG_CM_VINC_HPRD1_SHIFT},
	{PMIC_RG_CM_VINC_HPRD2, PMIC_RG_CM_VINC_HPRD2_ADDR,
	 PMIC_RG_CM_VINC_HPRD2_MASK, PMIC_RG_CM_VINC_HPRD2_SHIFT},
	{PMIC_RG_CM_VINC_HPRD3, PMIC_RG_CM_VINC_HPRD3_ADDR,
	 PMIC_RG_CM_VINC_HPRD3_MASK, PMIC_RG_CM_VINC_HPRD3_SHIFT},
	{PMIC_RG_CM_VINC_HPRD4, PMIC_RG_CM_VINC_HPRD4_ADDR,
	 PMIC_RG_CM_VINC_HPRD4_MASK, PMIC_RG_CM_VINC_HPRD4_SHIFT},
	{PMIC_RG_CM_VINC_HPRD5, PMIC_RG_CM_VINC_HPRD5_ADDR,
	 PMIC_RG_CM_VINC_HPRD5_MASK, PMIC_RG_CM_VINC_HPRD5_SHIFT},
	{PMIC_RG_CM_VINC_HPRD6, PMIC_RG_CM_VINC_HPRD6_ADDR,
	 PMIC_RG_CM_VINC_HPRD6_MASK, PMIC_RG_CM_VINC_HPRD6_SHIFT},
	{PMIC_RG_CM_LPRD, PMIC_RG_CM_LPRD_ADDR, PMIC_RG_CM_LPRD_MASK,
	 PMIC_RG_CM_LPRD_SHIFT},
	{PMIC_RG_CM_CS_VTHL, PMIC_RG_CM_CS_VTHL_ADDR, PMIC_RG_CM_CS_VTHL_MASK,
	 PMIC_RG_CM_CS_VTHL_SHIFT},
	{PMIC_RG_CM_CS_VTHH, PMIC_RG_CM_CS_VTHH_ADDR, PMIC_RG_CM_CS_VTHH_MASK,
	 PMIC_RG_CM_CS_VTHH_SHIFT},
	{PMIC_RG_PCHR_RSV, PMIC_RG_PCHR_RSV_ADDR, PMIC_RG_PCHR_RSV_MASK,
	 PMIC_RG_PCHR_RSV_SHIFT},
	{PMIC_RG_ENVTEM_D, PMIC_RG_ENVTEM_D_ADDR, PMIC_RG_ENVTEM_D_MASK,
	 PMIC_RG_ENVTEM_D_SHIFT},
	{PMIC_RG_ENVTEM_EN, PMIC_RG_ENVTEM_EN_ADDR, PMIC_RG_ENVTEM_EN_MASK,
	 PMIC_RG_ENVTEM_EN_SHIFT},
	{PMIC_RGS_BATON_HV, PMIC_RGS_BATON_HV_ADDR, PMIC_RGS_BATON_HV_MASK,
	 PMIC_RGS_BATON_HV_SHIFT},
	{PMIC_RG_HW_VTH_CTRL, PMIC_RG_HW_VTH_CTRL_ADDR, PMIC_RG_HW_VTH_CTRL_MASK,
	 PMIC_RG_HW_VTH_CTRL_SHIFT},
	{PMIC_RG_HW_VTH2, PMIC_RG_HW_VTH2_ADDR, PMIC_RG_HW_VTH2_MASK,
	 PMIC_RG_HW_VTH2_SHIFT},
	{PMIC_RG_HW_VTH1, PMIC_RG_HW_VTH1_ADDR, PMIC_RG_HW_VTH1_MASK,
	 PMIC_RG_HW_VTH1_SHIFT},
	{PMIC_RG_CM_VDEC_INT_EN, PMIC_RG_CM_VDEC_INT_EN_ADDR,
	 PMIC_RG_CM_VDEC_INT_EN_MASK, PMIC_RG_CM_VDEC_INT_EN_SHIFT},
	{PMIC_RG_CM_VINC_INT_EN, PMIC_RG_CM_VINC_INT_EN_ADDR,
	 PMIC_RG_CM_VINC_INT_EN_MASK, PMIC_RG_CM_VINC_INT_EN_SHIFT},
	{PMIC_RG_QI_BATON_LT_EN, PMIC_RG_QI_BATON_LT_EN_ADDR,
	 PMIC_RG_QI_BATON_LT_EN_MASK, PMIC_RG_QI_BATON_LT_EN_SHIFT},
	{PMIC_RGS_BATON_UNDET, PMIC_RGS_BATON_UNDET_ADDR, PMIC_RGS_BATON_UNDET_MASK,
	 PMIC_RGS_BATON_UNDET_SHIFT},
	{PMIC_RG_VCDT_TRIM, PMIC_RG_VCDT_TRIM_ADDR, PMIC_RG_VCDT_TRIM_MASK,
	 PMIC_RG_VCDT_TRIM_SHIFT},
	{PMIC_RG_INDICATOR_TRIM, PMIC_RG_INDICATOR_TRIM_ADDR,
	 PMIC_RG_INDICATOR_TRIM_MASK, PMIC_RG_INDICATOR_TRIM_SHIFT},
	{PMIC_EOSC_CALI_START, PMIC_EOSC_CALI_START_ADDR, PMIC_EOSC_CALI_START_MASK,
	 PMIC_EOSC_CALI_START_SHIFT},
	{PMIC_EOSC_CALI_TD, PMIC_EOSC_CALI_TD_ADDR, PMIC_EOSC_CALI_TD_MASK,
	 PMIC_EOSC_CALI_TD_SHIFT},
	{PMIC_EOSC_CALI_TEST, PMIC_EOSC_CALI_TEST_ADDR, PMIC_EOSC_CALI_TEST_MASK,
	 PMIC_EOSC_CALI_TEST_SHIFT},
	{PMIC_EOSC_CALI_DCXO_RDY_TD, PMIC_EOSC_CALI_DCXO_RDY_TD_ADDR,
	 PMIC_EOSC_CALI_DCXO_RDY_TD_MASK, PMIC_EOSC_CALI_DCXO_RDY_TD_SHIFT},
	{PMIC_FRC_VTCXO0_ON, PMIC_FRC_VTCXO0_ON_ADDR, PMIC_FRC_VTCXO0_ON_MASK,
	 PMIC_FRC_VTCXO0_ON_SHIFT},
	{PMIC_EOSC_CALI_RSV, PMIC_EOSC_CALI_RSV_ADDR, PMIC_EOSC_CALI_RSV_MASK,
	 PMIC_EOSC_CALI_RSV_SHIFT},
	{PMIC_VRTC_PWM_MODE, PMIC_VRTC_PWM_MODE_ADDR, PMIC_VRTC_PWM_MODE_MASK,
	 PMIC_VRTC_PWM_MODE_SHIFT},
	{PMIC_VRTC_PWM_RSV, PMIC_VRTC_PWM_RSV_ADDR, PMIC_VRTC_PWM_RSV_MASK,
	 PMIC_VRTC_PWM_RSV_SHIFT},
	{PMIC_VRTC_PWM_L_DUTY, PMIC_VRTC_PWM_L_DUTY_ADDR, PMIC_VRTC_PWM_L_DUTY_MASK,
	 PMIC_VRTC_PWM_L_DUTY_SHIFT},
	{PMIC_VRTC_PWM_H_DUTY, PMIC_VRTC_PWM_H_DUTY_ADDR, PMIC_VRTC_PWM_H_DUTY_MASK,
	 PMIC_VRTC_PWM_H_DUTY_SHIFT},
	{PMIC_VRTC_CAP_SEL, PMIC_VRTC_CAP_SEL_ADDR, PMIC_VRTC_CAP_SEL_MASK,
	 PMIC_VRTC_CAP_SEL_SHIFT},
};


unsigned short mt6353_set_register_value(PMU_FLAGS_LIST_ENUM flagname, unsigned int val)
{
	const PMU_FLAG_TABLE_ENTRY *pFlag = &pmu_flags_table[flagname];
	unsigned int ret = 0;


	if (pFlag->flagname != flagname) {
		pr_notice("[pmu_set_register_value]pmic flag idx error\n");
		return 1;
	}

	ret = pmic_config_interface((pFlag->offset),
				    (unsigned int)(val),
				    (unsigned int)(pFlag->mask), (unsigned int)(pFlag->shift)
	    );

	return 0;
}

unsigned short mt6353_get_register_value(PMU_FLAGS_LIST_ENUM flagname)
{
	const PMU_FLAG_TABLE_ENTRY *pFlag = &pmu_flags_table[flagname];
	unsigned int val = 0;
	unsigned int ret = 0;

	ret =
	    pmic_read_interface((unsigned int)pFlag->offset, &val, (unsigned int)(pFlag->mask),
				(unsigned int)(pFlag->shift));

	return val;
}

unsigned short mt6353_set_register_value_nolock(PMU_FLAGS_LIST_ENUM flagname, unsigned int val)
{
	const PMU_FLAG_TABLE_ENTRY *pFlag = &pmu_flags_table[flagname];
	unsigned int ret = 0;


	if (pFlag->flagname != flagname) {
		pr_notice("[pmu_set_register_value]pmic flag idx error\n");
		return 1;
	}

	ret = pmic_config_interface_nolock((pFlag->offset),
				    (unsigned int)(val),
				    (unsigned int)(pFlag->mask), (unsigned int)(pFlag->shift)
	    );

	return 0;
}


unsigned short mt6353_get_register_value_nolock(PMU_FLAGS_LIST_ENUM flagname)
{
	const PMU_FLAG_TABLE_ENTRY *pFlag = &pmu_flags_table[flagname];
	unsigned int val = 0;
	unsigned int ret = 0;

	ret =
	    pmic_read_interface_nolock((unsigned int)pFlag->offset, &val, (unsigned int)(pFlag->mask),
				(unsigned int)(pFlag->shift));

	return val;
}

unsigned short pmic_set_register_value(PMU_FLAGS_LIST_ENUM flagname, unsigned int val)
{
	return mt6353_set_register_value(flagname, val);
}

unsigned short pmic_get_register_value(PMU_FLAGS_LIST_ENUM flagname)
{
	return mt6353_get_register_value(flagname);
}

unsigned short pmic_set_register_value_nolock(PMU_FLAGS_LIST_ENUM flagname, unsigned int val)
{
	return mt6353_set_register_value_nolock(flagname, val);
}


unsigned short pmic_get_register_value_nolock(PMU_FLAGS_LIST_ENUM flagname)
{
	return mt6353_get_register_value_nolock(flagname);
}

unsigned short bc11_set_register_value(PMU_FLAGS_LIST_ENUM flagname, unsigned int val)
{
	return mt6353_set_register_value(flagname, val);
}

unsigned short bc11_get_register_value(PMU_FLAGS_LIST_ENUM flagname)
{
	return mt6353_get_register_value(flagname);
}
